computer architecture i: digital design dr. robert d. kent logic design decoders and multiplexers
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Computer Architecture I: Digital Design
Dr. Robert D. Kent
Logic DesignDecoders and Multiplexers
Review
• We have begun to study logic design in the contexts of Medium Scale Integration (MSI) of gate devices and programmable logic devices (PLD).
• We have studied the design of a number of specific, practical functional circuits, expressed in terms of Boolean expressions and their equivalent logic gates (SSI: Small Scale Integration) with a view to re-using those circuits as components in MSI design.
– 1-bit Half-Adder 1-bit Full-Adder
– Multi-bit Ripple Adder Subtractor
– Decade Adder Comparator
Goals
• We continue our study of simple, but functional Combinational circuits, namely Decoders/Encoders, Multiplexers, and PLD/PLA circuits:
– we continue constructing a small library of useful components
– through study of the solution process using Boolean algebra and Boolean calculus (simplification, etc.) we better understand the meaning of SSI design
– we seek to identify these components for their re-use potential
– through our study we will better understand how MSI increases the level of abstraction in solving problems - SSI design is relatively concrete.
Circuit # 9 : Decoders
Circuit # 9 : Decoders
• Decoders are most often used to transform one type of coding to another.
– Change data representations
– Design of address bus networks (specify an address to obtain data)
Circuit # 9 : Decoders
• Decoders are most often used to transform one type of coding to another.
– Change data representations
– Design of address bus networks
• A decoder is a multi-input, multi-output logic network.
Circuit # 9 : Decoders
• Decoders are most often used to transform one type of coding to another.
– Change data representations
– Design of address bus networks
• A decoder is a multi-input, multi-output logic network.
– Typically with N inputs and 2N outputs. N-to-2N
0 DEC 01 12 2. .. .. .N-1 2N-1
Circuit # 9 : Decoders
• Decoders are most often used to transform one type of coding to another.
– Change data representations
– Design of address bus networks
• A decoder is a multi-input, multi-output logic network.
– Typically with N inputs and 2N outputs.
• Other types of N-to-M decoders are alsoused, where M < 2N.
N-to-2N
0 DEC 01 12 2. .. .. .N-1 2N-1
Circuit # 9a : Simple Decoder
• The simplest decoder has N inputs and 2N outputs.
– The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0.
Circuit # 9a : Simple Decoder
• The simplest decoder has N inputs and 2N outputs.
– The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0.
• Example: a 2-line input to 4-line output decoder
Circuit # 9a : Simple Decoder
• The simplest decoder has N inputs and 2N outputs.
– The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0.
• Example: a 2-line input to 4-line output decoder
Truth table: Label the outputs DK, noting that the subscript value, K, is just the (unsigned) binary value Kradix-2 = [x1 x0]. Only one output line = 1 at a time.
x1 x0 D0 D1 D2 D3 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1
Circuit # 9a : Simple Decoder
• The simplest decoder has N inputs and 2N outputs.
– The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0.
• Example: a 2-line input to 4-line output decoder
Truth table: Label the outputs DK, noting that the subscript value, K, is just the (unsigned) binary value Kradix-2 = [x1 x0]. Only one output line = 1 at a time.
x1 x0 D0 D1 D2 D3 0 0 1 0 0 0 D0 = x1’ x0’ 0 1 0 1 0 0 D1 = x1’ x0 1 0 0 0 1 0 D2 = x1 x0’ 1 1 0 0 0 1 D3 = x1 x0
Circuit # 9a : Simple Decoder• The simplest decoder has N inputs and 2N outputs.
– The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0.
• Example: a 2-line input to 4-line output decoder
D0 = x1’ x0’ D1 = x1’ x0 D2 = x1 x0’ D3 = x1 x0
D0
D1
D2
D3
X0
X1
2-to-4 DEC
Circuit # 9a : Simple Decoder• The simplest decoder has N inputs and 2N outputs.
– The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0.
• Example: a 2-line input to 4-line output decoder
D0 = x1’ x0’ D1 = x1’ x0 D2 = x1 x0’ D3 = x1 x0
D0
D1
D2
D3
X0
X1
2-to-4 DEC
Note: Buffer-Inverter
=
Circuit # 9b : Simple Decoder
• The simplest decoder has N inputs and 2N outputs.
– The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0.
• We consider the example of a 3-input, 8-output decoder.
Circuit # 9b : Simple Decoder
• The simplest decoder has N inputs and 2N outputs.
– The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0.
• We consider the example of a 3-input, 8-output decoder.
x2 x1 x0 z0 z1 z2 z3 z4 z5 z6 z7 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1
Circuit # 9b : Simple Decoder
• The simplest decoder has N inputs and 2N outputs.
– The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0.
• We consider the example of a 3-input, 8-output decoder.
x2 x1 x0 z0 z1 z2 z3 z4 z5 z6 z7 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1
Note that each output, ZJ, is characterized by a single 1-value that can be immediately
represented as a single minterm.
Circuit # 9b : Simple Decoder
• The simplest decoder has N inputs and 2N outputs.
– The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0.
• We consider the example of a 3-input, 8-output decoder.
x2 x1 x0 z0 z1 z2 z3 z4 z5 z6 z7 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1
Z0 = X2 X1 X0
Z1 = X2 X1 X0
Z2 = X2 X1 X0
Z3 = X2 X1 X0
Z4 = X2 X1 X0
Z5 = X2 X1 X0
Z6 = X2 X1 X0
Z7 = X2 X1 X0
3-to-8 DEC 0
0 1
2
1 3
4
2 5
6
7
X0
X1
X2
Circuit # 9b : Simple Decoder
• The simplest decoder has N inputs and 2N outputs.
– The set of all N inputs is interpreted as an unsigned binary number that, in turn, selects a particular output line to output a value 1 with all other output lines having value 0.
• We consider the example of a 3-input, 8-output decoder.
x2 x1 x0 z0 z1 z2 z3 z4 z5 z6 z7 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1
Z0 = X2 X1 X0
Z1 = X2 X1 X0
Z2 = X2 X1 X0
Z3 = X2 X1 X0
Z4 = X2 X1 X0
Z5 = X2 X1 X0
Z6 = X2 X1 X0
Z7 = X2 X1 X0
3-to-8 DEC 0
0 1
2
1 3
4
2 5
6
7
X0
X1
X2
minterms
Circuit # 9b : Simple Decoder
• The decoder that we have developed is called a minterm generator decoder.
Circuit # 9b : Simple Decoder• The decoder that we have developed is called a minterm generator decoder.
• This type of MSI circuit is particularly valuable for constructing other types of circuits, based on the use of minterm expressions:
Circuit # 9b : Simple Decoder• The decoder that we have developed is called a minterm generator decoder.
• This type of MSI circuit is particularly valuable for constructing other types of circuits, based on the use of minterm expressions:
– Example: Consider two functions
F(X2 X1 X0) = Sum m(1,2,4,5)
G(X2 X1 X0) = Sum m(1,5,7)
Circuit # 9b : Simple Decoder• The decoder that we have developed is called a minterm generator decoder.
• This type of MSI circuit is particularly valuable for constructing other types of circuits, based on the use of minterm expressions:
– Example: Consider two functions
F(X2 X1 X0) = Sum m(1,2,4,5)
G(X2 X1 X0) = Sum m(1,5,7)
– These can be constructed immediately using the decoderand or gates.
Circuit # 9b : Simple Decoder• The decoder that we have developed is called a minterm generator decoder.
• This type of MSI circuit is particularly valuable for constructing other types of circuits, based on the use of minterm expressions:
– Example: Consider two functions
F(X2 X1 X0) = Sum m(1,2,4,5)
G(X2 X1 X0) = Sum m(1,5,7)
– These can be constructed immediately using the decoderand or gates.
F
3-to-8 DEC 0
0 1
2
1 3
4
2 5
6
7
X0
X1
X2
G
Circuit # 9c : Simple Decoder
• We note that various functions can be transformed from one form to another.
Circuit # 9c : Simple Decoder
• We note that various functions can be transformed from one form to another.
• For example:
H(X2 X1 X0) = Sum m(0,3,6,7)
Circuit # 9c : Simple Decoder
• We note that various functions can be transformed from one form to another.
• For example:
H(X2 X1 X0) = S m(0,3,6,7) = S m(0,3,6,7) double complement
Circuit # 9c : Simple Decoder
• We note that various functions can be transformed from one form to another.
• For example:
H(X2 X1 X0) = S m(0,3,6,7) = S m(0,3,6,7) double complement
= S m(1,2,4,5) complement canonical minterm
Circuit # 9c : Simple Decoder
• We note that various functions can be transformed from one form to another.
• For example:
H(X2 X1 X0) = S m(0,3,6,7) = S m(0,3,6,7) double complement
= S m(1,2,4,5) complement canonical minterm
= F(X2 X1 X0)
Circuit # 9c : Simple Decoder
• We note that various functions can be transformed from one form to another.
• For example:
H(X2 X1 X0) = S m(0,3,6,7) = m(0,3,6,7) double complement
= S m(1,2,4,5) complement canonical minterm
= F(X2 X1 X0)
H
3-to-8 DEC 0
0 1
2
1 3
4
2 5
6
7
X0
X1
X2
G
Circuit # 9c : Simple Decoder
• We note that various functions can be transformed from one form to another.
• For example:
H(X2 X1 X0) = S m(0,3,6,7) = m(0,3,6,7) double complement
= S m(1,2,4,5) complement canonical minterm
= F(X2 X1 X0)
H
3-to-8 DEC 0
0 1
2
1 3
4
2 5
6
7
X0
X1
X2
G
Note the inverter on the
output H, equivalent to using a nor
gate.
Circuit # 9d : Decoders with Enable Input
• Normally, decoders have one or more additional input lines referred to as enable inputs.
– These line values determine whether the circuit is operational or not.
Circuit # 9d : Decoders with Enable Input
• Normally, decoders have one or more additional input lines referred to as enable inputs.
– These line values determine whether the circuit is operational or not.
• Example: a 2-to-4 decoder with enable input
Truth table: Outputs DK can only have value 1 if enabled, E = 1.
E x1 x0 D0 D1 D2 D3 0 - - 0 0 0 0 Note: x1 x0 don’t matter
1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 1
Circuit # 9d : Decoders with Enable Input
• Normally, decoders have one or more additional input lines referred to as enable inputs.
– These line values determine whether the circuit is operational or not.
• Example: a 2-to-4 decoder with enable input
Truth table: Outputs DK can only have value 1 if enabled, E = 1.
E x1 x0 D0 D1 D2 D3 0 - - 0 0 0 0 Note: x1 x0 don’t matter
1 0 0 1 0 0 0 D0 = E x1’ x0’ 1 0 1 0 1 0 0 D1 = E x1’ x0 1 1 0 0 0 1 0 D2 = E x1 x0’ 1 1 1 0 0 0 1 D3 = E x1 x0
Circuit # 9d : Decoders with Enable Input
• Example: a 2-to-4 decoder with enable input
D0 = E x1’ x0’ D1 = E x1’ x0 D2 = E x1 x0’ D3 = E x1 x0
D0
D1
D2
D3
X0
X1
2-to-4 DEC
EOn(1)Off(0)
Circuit # 9d : Decoders with Enable Input
• Example: a 2-to-4 decoder with enable input
D0 = E x1’ x0’ D1 = E x1’ x0 D2 = E x1 x0’ D3 = E x1 x0
D0
D1
D2
D3
X0
X1
2-to-4 DEC
EOn(1)Off(0)
D0
D1
D2
D3
X0
X1
E
2-to-4DEC
Circuit # 9e : Decoder as LED Controller
• We now consider using a decoder to control the output of a set of light emitting diodes (LED’s) that display a decimal digit.
LEDdigit
Circuit # 9e : Decoder as LED Controller
• We now consider using a decoder to control the output of a set of light emitting diodes (LED’s) that display a decimal digit.
• We use a 4-to-7 decoder with enable input (E = 1 ON, E = 0 OFF) LED
digit
1
0
2
3
54
6
1
0
2
3
54
6
Circuit # 9e : Decoder as LED Controller
• We now consider using a decoder to control the output of a set of light emitting diodes (LED’s) that display a decimal digit.
• We use a 4-to-7 decoder with enable input (E = 1 ON, E = 0 OFF)
E x3 x2 x1 x0 z0 z1 z2 z3 z4 z5 z6 0 - - - - 0 0 0 0 0 0 0
LEDdigit
1
0
2
3
54
6
Circuit # 9e : Decoder as LED Controller
• We now consider using a decoder to control the output of a set of light emitting diodes (LED’s) that display a decimal digit.
• We use a 4-to-7 decoder with enable input (E = 1 ON, E = 0 OFF)
E x3 x2 x1 x0 z0 z1 z2 z3 z4 z5 z6 0 - - - - 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 1 1
LEDdigit
1
0
2
3
54
6
Circuit # 9e : Decoder as LED Controller
• We now consider using a decoder to control the output of a set of light emitting diodes (LED’s) that display a decimal digit.
• We use a 4-to-7 decoder with enable input (E = 1 ON, E = 0 OFF)
E x3 x2 x1 x0 z0 z1 z2 z3 z4 z5 z6 0 - - - - 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 1 1 0 1 1 0 1 1
LEDdigit
1
0
2
3
54
6
Circuit # 9e : Decoder as LED Controller
• We now consider using a decoder to control the output of a set of light emitting diodes (LED’s) that display a decimal digit.
• We use a 4-to-7 decoder with enable input (E = 1 ON, E = 0 OFF)
E x3 x2 x1 x0 z0 z1 z2 z3 z4 z5 z6 0 - - - - 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 1 1 0 1 1 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 1
LEDdigit
1
0
2
3
54
6
Circuit # 9e : Decoder as LED Controller
• We now consider using a decoder to control the output of a set of light emitting diodes (LED’s) that display a decimal digit.
• We use a 4-to-7 decoder with enable input (E = 1 ON, E = 0 OFF)
E x3 x2 x1 x0 z0 z1 z2 z3 z4 z5 z6 0 - - - - 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 1 1 0 1 1 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 1 1 1 1 0 1 1 1 1 0 1 0 0 1 01 1 0 0 0 1 1 1 1 1 1 1
LEDdigit
1
0
2
3
54
6
Circuit # 9e : Decoder as LED Controller
• We now consider using a decoder to control the output of a set of light emitting diodes (LED’s) that display a decimal digit.
• We use a 4-to-7 decoder with enable input (E = 1 ON, E = 0 OFF)
E x3 x2 x1 x0 z0 z1 z2 z3 z4 z5 z6 0 - - - - 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 1 1 0 1 1 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 1 1 1 1 0 1 1 1 1 0 1 0 0 1 01 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 0
LEDdigit
Circuit # 9e : Decoder as LED Controller
• We obtain the canonical minterm expressions:
E x3 x2 x1 x0 z0 z1 z2 z3 z4 z5 z6 0 - - - - 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 1 1 0 1 1 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 1 1 1 1 0 1 1 1 1 0 1 0 0 1 01 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 0
Circuit # 9e : Decoder as LED Controller
• We obtain the canonical minterm expressions:
E x3 x2 x1 x0 z0 z1 z2 z3 z4 z5 z6 0 - - - - 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 1 1 0 1 1 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 1 1 1 1 0 1 1 1 1 0 1 0 0 1 01 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 0
Z0 = S m(0,2,3,5,7,8,9)
Z1 = S m(0,4,5,6,8,9)
Z2 = S m(0,1,2,3,4,7,8,9)
Z3 = S m(2,3,4,5,6,8,9)
Z4 = S m(0,2,6,8)
Z5 = S m(0,1,2,4,5,6,7,8,9)
Z6 = S m(0,2,3,5,6,8)
Circuit # 9e : Decoder as LED Controller
• And simplify, if possible (e.g. using complementation):
E x3 x2 x1 x0 z0 z1 z2 z3 z4 z5 z6 0 - - - - 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 1 1 0 1 1 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 1 1 1 1 0 1 1 1 1 0 1 0 0 1 01 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 0
Z0 = S m(0,2,3,5,7,8,9)
Z1 = m(0,4,5,6,8,9)
Z2 = m(0,1,2,3,4,7,8,9)
Z3 = m(2,3,4,5,6,8,9)
Z4 = m(0,2,6,8)
Z5 = m(0,1,2,4,5,6,7,8,9)
Z6 = m(0,2,3,5,6,8)
Z0’ = S m(1,4,6)
Z1’ = S m(1,2,3,7)
Z2’ = S m(5,6)
Z3’ = S m(0,1,7)
Z4’ = S m(1,3,4,5,7,9)
Z5’ = S m(3)
Z6’ = S m(1,4,7,9)
Z0’ = S m(1,4,6)
Z1’ = S m(1,2,3,7)
Z2’ = S m(5,6)
Z3’ = S m(0,1,7)
Z4’ = S m(1,3,4,5,7,9)
Z5’ = S m(3)
Z6’ = S m(1,4,7,9)
Circuit # 9e : Decoder as LED Controller
X0
X1
X2
X3
E
4-to-10 DEC 0
0 1
1 2
2 3
3 4
5
6
7
8
9
Z0’
Z1’
Z2’
Z3’
Z4’
Z5’
Z6’
1
0
2
3
54
6
Circuit # 10 : Encoders
Circuit # 10 : Encoders
• Encoders are essentially the inverse of decoders.
• Typical encoders are represented as 2N input lines to N output lines.
• In general, encoders are N-to-M decoders, where N > M.
2N-to-N
0 ENC 01 12 2. .. .. .2N-1 N-1
N-to-2N
0 DEC 01 12 2. .. .. .N-1 2N-1
Circuit # 11 : Multiplexers
Circuit # 11 : Multiplexers
• Multiplexers are used in many places within computers. One important use is in designing and constructing data buses.
I0
I1
I2
I3
E
S1 S0
F
4-to-1MUX
Circuit # 11 : Multiplexers
• Multiplexers are used in many places within computers. One important use is in designing and constructing data buses.
• For this reason they are also called data selectors.
I0
I1
I2
I3
E
S1 S0
F
4-to-1MUX
Circuit # 11 : Multiplexers
• Multiplexers are used in many places within computers. One important use is in designing and constructing data buses.
• For this reason they are also called data selectors.
• Assuming that data exists in 2N locations, I0, I1, … etc., the objective of the circuit is to obtain a copy of the data value, IK, at the output, F.
I0
I1
I2
I3
E
S1 S0
F
4-to-1MUX
Circuit # 11 : Multiplexers
• Multiplexers are used in many places within computers. One important use is in designing and constructing data buses.
• For this reason they are also called data selectors.
• Assuming that data exists in 2N locations, I0, I1, … etc., the objective of the circuit is to obtain a copy of the data value, IK, at the output, F.
• The data value, IK, is selected using theselector inputs, SJ, similar to the operationof the decoder.
I0
I1
I2
I3
E
S1 S0
F
4-to-1MUX
Circuit # 11 : Multiplexers
• Multiplexers are used in many places within computers. One important use is in designing and constructing data buses.
• For this reason they are also called data selectors.
• Assuming that data exists in 2N locations, I0, I1, … etc., the objective of the circuit is to obtain a copy of the data value, IK, at the output, F.
• The data value, IK, is selected using theselector inputs, SJ, similar to the operationof the decoder.
• The multiplexer, or MUX, may be enabled/disabled.
I0
I1
I2
I3
E
S1 S0
F
4-to-1MUX
Circuit # 11 : Multiplexers
• The details of the circuit are easily derived and laid out in the form:
I0
I1
I2
I3
S1 S0
F
E
I0
I1
I2
I3
E
S1 S0
F
4-to-1MUX
Circuit # 11 : Multiplexers
• The details of the circuit are easily derived and laid out in the form:
I0
I1
I2
I3
S1 S0
0
0
I0
I1
I2
I3
E
S1 S0
F
4-to-1MUX
Disabled MUX
Circuit # 11 : Multiplexers
• The details of the circuit are easily derived and laid out in the form:
I0
I1
I2
I3
E
S1 S0
F
4-to-1MUX
Enabled MUXI0
I1
I2
I3
1 0
I2
1
Circuit # 11 : Multiplexers
• Example. Consider a data bus intended to fetch 4-bits from a specified address.
Circuit # 11 : Multiplexers
• Example. Consider a data bus intended to fetch 4-bits from a specified address.
Address RAM Contents
B3 B2 B1 B000
B3 B2 B1 B001
B3 B2 B1 B010
B3 B2 B1 B011
Circuit # 11 : Multiplexers
• Example. Consider a data bus intended to fetch 4-bits from a specified address.
Address RAM Contents
B3 B2 B1 B000
B3 B2 B1 B001
B3 B2 B1 B010
B3 B2 B1 B011
Each memory unit contains 4 bits. Each bit has an
input/output line.
Note the important fact that each
memory unit has a separate and
unique address.
Circuit # 11 : Multiplexers
• Example. Consider a data bus intended to fetch 4-bits from a specified address.
Address RAM Contents
B3 B2 B1 B000
B3 B2 B1 B001
B3 B2 B1 B010
B3 B2 B1 B011
It is required to copy (obtain) the
4-bits of a specified address
to a different output location that can hold 4-
bits.
We use multiplexers to
achieve this goal.
Circuit # 11 : Multiplexers
• Example. Consider a data bus intended to fetch 4-bits from a specified address.
Address RAM ContentsMeans enableis ON.
B3 B2 B1 B000
B3 B2 B1 B001
B3 B2 B1 B010
B3 B2 B1 B011
4x1MUX
S1 S0
F0
F1
F2
F3
First, connect an Nx1 MUX to each of the N bits labeled bit-0, or B0.
Then, add L more such
MUX connections to
form a complete bus.
Circuit # 11 : Multiplexers
• Example. Consider a data bus intended to fetch 4-bits from a specified address.
Address RAM ContentsMeans enableis ON.
B3 B2 B1 B000
B3 B2 B1 B001
B3 B2 B1 B010
B3 B2 B1 B011
4x1MUX
4x1MUX
S1 S0
4x1MUX
F0
F1
F2
F3
4x1MUX
The full circuit shows how a
data bus architecture may
be defined.
Circuit # 11 : Multiplexers
• Example. Consider a data bus intended to fetch 4-bits from a specified address.
Address RAM ContentsMeans enableis ON.
B3 B2 B1 B000
B3 B2 B1 B001
B3 B2 B1 B010
B3 B2 B1 B011
4x1MUX
4x1MUX
0 1
4x1MUX
F0 = B0
F1 = B1
F2 = B2
F3 = B3
4x1MUX
The highlighte
d lines show how
data selection is achieved.
Address selection
Circuit # 11 : Multiplexers
• There are numerous applications of multiplexers in logic design.
• Review the examples discussed in the textbook
– Section 5.6.1 pages 266-276.
Summary - Part II
• We continue to study logic design in the contexts of Small Scale Integration (SSI) and Medium Scale Integration (MSI) of gate devices.
• We have studied the design of a number of specific, practical functional circuits with a view to re-using those circuits as components in MSI design.
Adders Subtractors Comparator
• We note the differing design approaches, or emphases, effected by differential layering of abstraction. (The same design issue arises in the context of software engineering as well.)
SSI: Boolean algebra / Simplification / Logic gates
MSI: Interconnection networks / Iterative re-use / Components
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