connect four project
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Connect Four ProjectFall 2011Anna Grimley & Josh MandichLab Section: F
Connect Four Game
Objectives1. Create Verilog Code for Connect Four Logic2. Synthesize Code3. Create Layout
Project Constraints
Inputs Outputs
PONE 0:3 Red 0:15
PTWO 0:3 GREEN 0:15
START PONEWIN
PTWOWIN
0Boolean: 0000
10001
20010
30011
40100
50101
60110
70111
81000
91001
101010
111100
121101
131110
141110
151111
Game as Two PlayersMust use 4x4 matrix of LED’sPlayer must be able to start by using the START inputPONE always starts, PONE&PTWO can not give input simultaneously Player must be able to start by using the START input
Other times to think aboutMust not allow a player to overwrite previous selection.Must not allow player to play out of turnGame must stop when player winsA 4x4
Strategy• Keep code simple• Take into consideration what is synthesizable and
what is not• Start building code early and seek for help
Truly elegant design incorporates top-notch functionality into a simple, uncluttered form.
— David Lewis
Verilog HDL• At Start==0
sets all registers to 0. and turn=1
• Continues to check PONEWIN & PTWOWIN are zero at all steps
Verilog Code
Input and Start
Verilog Code
Light LED from User Input
Verilog Code
Detect Winning Input
Testing Verilog Code
Test Bench• Wanted to Test
Player can not keep playing when LED already selected
• Proved that PONEWIN would work when PONE had won
VSIM Testbench Output
SynthesizingSchematic of elaborated Verilog Connect 4. (Code in RTL compiler)
SynthesizingSchematic of Optimized Connect 4(Code integrated with OSU lib)
SynthesizingSchematic of Optimized Connect 4(Code integrated with OSU lib)
Synthesizing Schematic cell view of synthesized Connect4 code in Virtuoso
Layout• Initial Floor Plan• Floorplan layout
with power rings
LayoutCell and IO pin Placemnent
Layout• Power and Ground
Routing• Power Routing
between die I/O and standard cells
LayoutFinal layout view of Connect4.v in Encounter with filler added
Yay! Celebrate!!!
Final LayoutUsing OSU_stdcells_ami05 library.
Major Take Away’s• Understand what verilog can be synthesized and
what can not• Keep Verilog simple• Be patient with synthesizing and layout in
encounter/virtuoso• Spending time on HDL pays off in synthesizing
Ha Ha HaNot this Connect Four
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