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Continuous Time Sigma DeltaModulators and VCO ADCs

Pieter Rombouts

Electronics and Information Systems Lab.,Ghent University,

Belgium

Pavia, March 2017

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 1 / 80

Outline

1 Sigma Delta Modulation

2 Continuous Time Sigma Delta Modulation

3 FoM Confusion

4 VCO ADC

5 Conclusion

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 2 / 80

A/D converter: traditional interpretation

UI

converts analog value into digitalnumber of bits n

I quantisation step q:

q = Vref /2n

error within ±q/2staircase I/O

I static nonlinearityI INL or DNL

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 3 / 80

A/D converter: other interpretationUI

UI

Q

converts analog signal into digital signalquantisation eror Q

I (white) noise signalI like other noise contributionsI number of bits not essential

F large enoughLeave margin for other noise sources

F effective bits

quantisation noise variance

σ2Q =

q2

12P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 4 / 80

Core concept 1: Oversamplingspectrum

spectrum

0.1 0.2 0.3 0.4 0.5

signal

white noise

0.1 0.2 0.3 0.4 0.5

frequency/fsample frequency/fsample

Oversampling ratio:

OSR =fS2f0

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 5 / 80

Core concept 1: Oversamplingspectrum

spectrum

0.1 0.2 0.3 0.4 0.5

signal

white noise

0.1 0.2 0.3 0.4 0.5

frequency/fsample frequency/fsample

ideal digital filter after quantizerI averaging mechanismI number of bits has increasedI less noiseI filters signal as well

F not Nyquist-rate anymore!

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 6 / 80

Core concept 1: Oversamplingspectrum

spectrum

0.1 0.2 0.3 0.4 0.5

signal

white noise

0.1 0.2 0.3 0.4 0.5

frequency/fsample frequency/fsample

quantisation noise variance

σ2Q =

q2

12OSR∼ 1

OSR

3dB/octave improvement

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 7 / 80

The Σ∆ control loop

(a) (b)

S quantVin Vin+ +

- -

DH S S

+ D

Q

H

DAC

ideal DACfilter

I discrete timeI continuous time

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 8 / 80

The Σ∆ control loop

(a) (b)

S quantVin Vin+ +

- -

DH S S

+ D

Q

H

DAC

D =H

1 + HVin +

1

1 + HQ

for low frequencies H ≈ ∞ −→ D ≈ Vin

nullator

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 9 / 80

The Σ∆ control loop

D =H

1 + HVin +

1

1 + HQ︸ ︷︷ ︸

error

input signal is also filtered

for low frequencies NTF = 11+H ≈ 0

for high frequencies NTF = 11+H 6= 0

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 10 / 80

Core concept 2: ”Noise” Shaping

NTF(z)

DC

freq.

fsample/2

1

for high frequencies NTF = 11+H 6= 0

spectral shaping

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 11 / 80

Core concept 2: “Noise” Shaping

(a) (b)

DC

freq.

fsample/2 DC

freq.

fsample/2

signalshaped noise

noise spectrum has the shape of NTF

combine with oversampling −→ most noise vanishes

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 12 / 80

Σ∆ Modulators

(a) (b)

S quantVin Vin+ +

- -

DH S S

+ D

Q

H

DAC

quantizerI very few bitsI accuracy from oversampling + noise shapingI 1 bit

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 13 / 80

Σ∆ Modulators

(a) (b)

S quantVin Vin+ +

- -

DH S S

+ D

Q

H

DAC

1-bit quantizerI simpleI inherent linearI noise is not white

F tonesF stability

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 14 / 80

Σ∆ Modulators

(a) (b)

S quantVin Vin+ +

- -

DH S S

+ D

Q

H

DAC

multi-bit quantizerI better performanceI DAC needs linearization

F DEMF calibration

I always larger area

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 15 / 80

Σ∆ Modulators

(a) (b)

S quantVin Vin+ +

- -

DH S S

+ D

Q

H

DAC

filterI cascade of integratorsI order: design parameter

F trade-off complexity-performanceI special design techniques

F Richard Schreier’s toolbox

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 16 / 80

1st order, 1bit Σ∆ ModulatorTypical circuit

+

-C

Vref

Vin

bi

C

+

- biD Q

clk

switched capdevices can be very small

I also CI (thermal) noise ↓ due to oversampling

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 17 / 80

High Order Σ∆ ModulatorsCascade of integrators with feedback

DAC

1z -1

b2

1z -1c2

-g1

-a3

b3 b4

-a2

c3

u(n)

v(n)y(n)x3(n)x2(n1z -1

b1

c1x1(n)

-a1

without extra feed insI high swing on internal nodesI ‘poor’ distortion performance

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 18 / 80

High Order Σ∆ ModulatorsCascade of integrators with feedforward

DAC

1z -1

b2

1z -1c3

-g1

b3 b4

a3

u(n)

v(n)y(n)x3(n)x2(n1z -1

b1

c2x1(n)

-c1a2

a1

without extra feed insI negligible swing on internal nodesI excellent distortion performance

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 19 / 80

Σ∆ ADC

Sigma Deltamodulator

lowpassfilter

Vin anti-aliasingprefilter

f < fcutoff S

fS 2f0 Dout

f = fcutoff 0

analog digital

decimation filter

several filters in chainI simple anti-aliasing filterI no sample-to-sample correspondence

number of bits in Dout high enough

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 20 / 80

Σ∆ ADC

Sigma Deltamodulator

lowpassfilter

Vin anti-aliasingprefilter

f < fcutoff S

fS 2f0 Dout

f = fcutoff 0

analog digital

decimation filter

scientific literatureI without filtersI accuracy calculated from ideal filter

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 21 / 80

OSR

Low OSR?I keep fs feasableI need many quantizer bitsI need high order filterI minimum 8

High OSR?I small devices

F noise is filtered

I low filter orderI 1-bit quantiser

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 22 / 80

Outline

1 Sigma Delta Modulation

2 Continuous Time Sigma Delta Modulation

3 FoM Confusion

4 VCO ADC

5 Conclusion

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 23 / 80

CTSDM vs DTSDM

Σ∆ modulatorsI oversampling and noise shapingI high-accuracy

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 24 / 80

CTSDM vs DTSDM

Discrete-timeI versatileI “simple” designI easy to “abuse”

standard cell IP core

Continuous-timeI potential for higher speedI potential for lower powerI anti-aliasingI non-trivial design (needs tuning)I performance and stability depend on fclkI common myth: sensitive to clock jitter

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 25 / 80

Continuous Time Σ∆ modulator

. . .Vin(s)

fs

Dout(z)

ZOH(s)ZOH(s)

a1sTs

aNsTs

. . .

−Σ Σ

−Σ

−quant

closed feedback loopI cascade of integrators with feedbackI cascade of integrators with feedforward . . .

loop filter = continuous time

sampler inside loop

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 26 / 80

Continuous Time Σ∆ modulatorLinearized model

. . .Vin(s)

fs

Dout(z)

ZOH(s)ZOH(s)

a1sTs

aNsTs

. . .

−Σ Σ

−Σ

−Σ

Q

output contains two contributionsI Input signalI Quantisation noise

superposition

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 27 / 80

Quantization noise

. . .f s

Dout(z)

ZOH(s)ZOH(s)

a1sTs

aNsTs

. . .

−Σ Σ

−Σ

−Σ

Q

−Σ

ZOH(s)H(s)

f s

Heq(z)

Dout(z)

Q

equivalent discrete time loop filter Heq(z)I fully equivalentI impulse invariant transform of H(s)I CT - DT relationship: z = esTclk

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 28 / 80

Quantization noise

−Σ

ZOH(s)H(s)

f s

Heq(z)

Dout(z)

Q

1

Heq + 1· Q = NTF · Q

equivalent to DT Σ∆ modulator

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 29 / 80

Quantization noise

−Σ

ZOH(s)H(s)

f s

Heq(z)

Dout(z)

Q

remarksI theory = mature

F e.g. c2d function in matlab

I Heq depends on Dac-pulseI Heq depends on fsI Heq sensitive to analog imperfections

F ‘excess’ loop delayF parasitic (opamp) poles

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 30 / 80

Continuous Time Σ∆ modulatorLinearized model

. . .Vin(s)

fs

Dout(z)

ZOH(s)ZOH(s)

a1sTs

aNsTs

. . .

−Σ Σ

−Σ

−Σ

Q

output contains two contributionsI Input signalI Quantisation noise

superposition

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 31 / 80

Input signal

. . .Vin(s)

f sDout(z)

ZOH(s)ZOH(s)

a1sTs

aNsTs

. . .

−Σ Σ

−Σ

Vin(s) Dout(z)G(s)

f s

−Σ

ZOH(s)H(s)

f s

Heq(z)

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 32 / 80

Input signal

Vin(s) Dout(z)G(s)

f s

−Σ

ZOH(s)H(s)

f s

Heq(z)

Vin(s) Dout(z)G(s)

f s

Vin(s) Dout(z)G(s)

f s

AAF(s)

NTF(z)

NTF(z)

equivalent to filter AAF (s) = G (s) ·NTF (z = esTclk)

followed by samplerP. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 33 / 80

Anti-Aliasing in CTSDM

AAF (s) = G (s)NTF (z)

Double filter effect in alias bands (around nfclk)I G (S) lowpass filterI NTF (z) notches at nfclk

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 34 / 80

Anti-Aliasing in CTSDM

2−8 2−7 2−6 2−5 2−4 2−3 2−2 2−1 20 21-100

-50

0

50

f/fs

Amplituderespon

se(dB)

NTFeq(esTs)

G(s)

AAF (s)

N = 2a1 = 0.3246a2 = 0.6667

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 35 / 80

Feedback vs Feedforward

. . .Vin(s)

fs

Dout(z)

ZOH(s)ZOH(s)

a1sTs

aNsTs

. . .

−Σ Σ

−Σ

−quant

cascade of integrators with feedbackI double anti-aliasing: G (s) and NTF

F less stringent prefiltering requirementsI large internal signal swing

F more demanding opamps

I ADC itself = power hungry but system may be moreefficient

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 36 / 80

Feedback vs Feedforward

Vin

-+

+

a1sT

quantansT T

H (s)DAC

a2sT

D+ +

cascade of integrators with feedforwardI single anti-aliasing: NTF but G (s) does not filter

F stringent pre-filtering requirementsI small internal signal swing

F no demanding opamps

I ADC itself = efficient but system may be power hungry

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 37 / 80

Noise and power

Vin

-+

+

a1sT

quantansT T

H (s)DAC

a2sT

D+ +

First stage noise dominatesI later stages scaled

F lower powerF still negligible noise

First stage power dominates as wellI increasing order ⇒ moderate impact on power

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 38 / 80

Circuit Noise

Ev 2n = 4kTReff · B

noise sees anti-aliasing filterI only in band noiseI no kT/C noise

in theory much better than SC

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 39 / 80

‘Excess’ Loop delayCTSDM problems

Vin

-+

+

a1sT

quantansT T

H (s)DAC

a2sT

D+ +

parasitic loop delay

also parasitic poles

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 40 / 80

‘Excess’ Loop delayCTSDM problems

Σc1sTs−

Vin(s) Σc2sTs

c3sTs

a3 Σ

fs

Vout(z)

a2

a1d

HDAC(s)

z−1

z−12

−g

e−sτHDAC(s)

parasitic loop delayI make loop delay explicitI add compensation path

also for parasitic poles

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 41 / 80

Process variationsCTSDM problems

Σc1sTs−

Vin(s) Σc2sTs

c3sTs

a3 Σ

fs

Vout(z)

a2

a1d

HDAC(s)

z−1

z−12

−g

e−sτHDAC(s)

large errors on RC productsI tuneI robust design

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 42 / 80

Slew rateCTSDM problems

opamp not allowed to slewinjection of quantisation noise

I multi-bitI some filtering (e.g. FIR)

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 43 / 80

JitterCTSDM problems

Σc1sTs−

Vin(s) Σc2sTs

c3sTs

a3 Σ

fs

Vout(z)

a2

a1d

HDAC(s)

z−1

z−12

−g

e−sτHDAC(s)

jitter in outer feedback DACI directly affects performanceI depends on DAC pulse

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 44 / 80

JitterCTSDM problems

clock

ZOH

clock

ZOH

ZOH

white jitterI catastrophicalI solution: multi-bit, FIR etc.

lowpass jitter (= reality)I no big deal

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 45 / 80

CTSDM vs DTSDM

Continuous-timeI inherent anti-aliasing

F no noise aliasingcfr kT/C noise in switched cam

F better power-noise trade offI common myth

F sensitive to clock jitter⇒ not as bad as widely assumed

I factsF performance and stability depend on fclkF non-trivial design

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 46 / 80

Outline

1 Sigma Delta Modulation

2 Continuous Time Sigma Delta Modulation

3 FoM Confusion

4 VCO ADC

5 Conclusion

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 47 / 80

Figure of Merit

Need for FOMI difficult to compare ADC architecturesI different Peak SNDR, Power, Bandwidth, Technology,

areaI which architecture for new design?

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 48 / 80

Figure of Merit

Walden’s FOM (1999)

FOMW =P

2ENOB 2 BW

I pJ/conversion code (or pJ/conversion step)I intended to reduce variablesI no justificationI used for many yearsI but meaningless . . .

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 49 / 80

Justifying Walden’s FOM?

FOMW =P

2ENOB 2 BW

in good design: P ∼ BWI OK

P ∼ 2N

I ???

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 50 / 80

Justifying Walden’s FOM?

P ∼ 2N ???

flash2N comparators

I OK if comparator powerconstant

comparator accuracy ∼ 2−N

I comparator power ∼ 2N

I comparator power ∼ 22N

oops . . .

Vin

+

+

+

+

-

-

-

-

D

D

D

D

Q

Q

Q

Q

clk

clk

clk

clk

Vref

0

1

1

1

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 51 / 80

Impedance Scaling laws

I

R

(a)

W

L

C

V

2I

R/2

2W

L

2C

V

(b)

start from best design possibleneed 3dB better SNR

I scale impedances: factor 2

power: factor 4 per bit

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 52 / 80

FOM confusion

FOMW =P

2ENOB 2 BW

Walden fixed (scaling laws)

FOMW ,fixed =P

22·ENOB 2 BW

all high accuracy designs were rated bad . . .SAR’s were overrated . . .

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 53 / 80

FOM confusion

FOMW ,corrected =P

22·ENOB 2 BW

Walden fixed (scaling laws)I not used

correct FOM: Schreier’s FOM (2005)

FOMS = Peak SNDR + 10log10

(BW

P

)

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 54 / 80

Outline

1 Sigma Delta Modulation

2 Continuous Time Sigma Delta Modulation

3 FoM Confusion

4 VCO ADC

5 Conclusion

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 55 / 80

VCO-ADC: drivers

++

++

++

Ctrl

N stages Vdd

Ctrl

W

2W

maininverters

auxinverters

4x

4x

1x 1x

vin+

vin-

vout-

vout+

quest for more digital ADC’sI ring oscillatorsI ‘digital’ signalsI no opamps

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 56 / 80

VCO-ADC naive

VCO1

Vi n resetcounter

kv fc

D

f sf s f sf s

accuracy ∼ fVCOfs

I e.g. 6-bit for fs = 1GHz, fVCO = 64GHz,

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 57 / 80

VCO-ADC equivalent

VCO1

Vi n resetcounter

kv fc

D

f sf s f sf s

VCO1

Vi n counter

kv fcD

f sf s

I1 - z-1

D

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 58 / 80

VCO-ADC in phase domain

VCO1

Vi n counter

kv fcD

f sf s

I DVCO1

i n

quant

kv fcD

f sf s

I D

Vi nkv

fc

D

ss

I Di n1/skv

fc

D

sf

s

I

1 - z-1

D+

1 - z-1

phase = integral of frequency

edge occurs when phase = n · 2πphase information is quantized with step = 2π

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 59 / 80

VCO-ADC in phase domain

Vi nkv

fc

D

f sf s

I Di n1/skv

fc

D

f sf s

I D+ +

Q

1 - z-1

D(z) ∼(Vin

(1− z−1

)s

)∗+(1− z−1

)︸ ︷︷ ︸NTF

Q

like 1st order CTSDMI anti-aliasingI noise shapingI boost accuracy by oversampling

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 60 / 80

multi-phase VCO-ADC

++

++

++

Ctrl

N stages Vdd

Ctrl

W

2W

maininverters

auxinverters

4x

4x

1x 1x

vin+

vin-

vout-

vout+

untill now 1 VCO outputI ring oscillator has N output phases

use all N VCO-phasesI now phase transition at 2π/NI quantization error: N times smallerI higher effective number of bits

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 61 / 80

multi-phase VCO-ADC

use all N VCO-phasescounter triggered by N clock inputs?

I use parallelism

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 62 / 80

multi-phase VCO-ADC

VCOVi n

resetcounter

D

f sf s f sf s

resetcounter

f sf s f sf s

resetcounter

f sf s f sf s

adder

E.g. N = 64 phases, fs = 1GHz, fVCO = 1GHz,I equivalent fs = 1GHz, fVCO = 64GHz,I 6-bit

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 63 / 80

multi-phase VCO-ADC

VCOVi n

resetcounter

D

f sf s f sf s

resetcounter

f sf s f sf s

resetcounter

f sf s f sf s

adder

Reset counter?I special case: 1 bit counterI possible if fVCO ≤ fs

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 64 / 80

1-bit counter for VCO-ADCs

clk

D QVCO[i]

DFF

clk

DQ

^

Dout

^

fs

+1

0

+1

0

+1

0

><

(a)

(b)

VCO3

CLK

Dout

TS><TS

t

t

t

><TS

reacts on both edgesI effectively fVCO,eff = 2fVCO

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 65 / 80

multi-phase VCO-ADC

w1(t)fff

w2(t)D Q D Q

fs

D Q D Q

fs

D Q D Q

fs

wM(t)

w1(t)

x(t)

+

......

y[n]

M-phases ring oscillator Readout circuit (xM)

2 important properties

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 66 / 80

multi-phase VCO-ADC

w1(t)fff

w2(t)D Q D Q

fs

D Q D Q

fs

D Q D Q

fs

wM(t)

w1(t)

x(t)

+

......

y[n]

M-phases ring oscillator Readout circuit (xM)

output = barrel shifted thermometer encodedI inherent DWAI can drive unit element DACI summation = ‘thermometer to binary” coder

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 67 / 80

multi-phase VCO-ADC

w1(t)fff

w2(t)D Q D Q

fs

D Q D Q

fs

D Q D Q

fs

wM(t)

w1(t)

x(t)

+

......

y[n]

M-phases ring oscillator Readout circuit (xM)

condition on fVCO :I 0 < fVCO < fs/2

typical sizing:I free running fVCO,0 = fs/4I KV for full scale swingI some tuning

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 68 / 80

VCO-ADC challenges

higher order noise shapingI current research

VCO non-linearity

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 69 / 80

VCO-ADC with high-order noise shaping

Current work at UGent‘digital’ 3rd order VCO ADC

I prototype in 65 nm CMOSI 12bits@10MHz (with digital calibration)I 11bits@10MHz (without digital calibration)I 3.5 mWI 0.01 mm2

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 70 / 80

VCO-ADC challenges

higher order noise shapingVCO non-linearity

I best: 11-bit linearity (UGent)I other solutions

F digital (self)-calibrationF swing reductionF embed in Sigma Delta Loop

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 71 / 80

Ghent University linear VCO circuitring oscillator VCO non-linearity

++

++

++

Ctrl

N stagesRing-Osc

Vin Ctrl

R1

R2

Vdd

A. Babaie-Fishani and P. Rombouts,

“Highly linear VCO for use in VCO-ADCs,” Electron. Lett. 2016.

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 72 / 80

Ghent University linear VCO circuitring oscillator VCO non-linearity

0 0.2 0.4 0.6 0.8 1100

150

200

250

300

350

400

450

500

(a) Input voltage [volt]

VCO

Fre

quen

cy [M

Hz]

0 0.2 0.4 0.6 0.8 1−3

−2

−1

0

1

2

3

(b) Input voltage [volt]VC

O F

requ

ency

erro

r [M

Hz]

almost 12 bit linearity in pseudo differentialconfiguration

some noise penalty

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 73 / 80

digital (self)-calibrationring oscillator VCO non-linearity

Doutnon-linearity

f( )oversamplingnoise-shaping

modulator

digitalnon-linearity

correction

f-1( )Ddec

decimationVi n

look-up tableI nonlinearity is smoothI can be very small (11 points excellent results)

some calibration mechanism

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 74 / 80

Input swing reductionring oscillator VCO non-linearity

VCO resetcounter

f skv , fc

+−

Vi n

AD

Cf

DAC

f +Dout(z)

0-1 mash structureI aux ADC and DAC

F uncritical

I sensitive to mismatch

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 75 / 80

VCO-ADC in sigma delta loopring oscillator VCO non-linearity

VCOresetcounter Dout(z)

f skv , fc

loopfilter

+

-

DAC

Vi n

embed in Sigma Delta LoopI Original work by Perrott’s groupI input signal of VCO still large

for e.g. 2nd order loop filterI 3rd order noise shapingI 2nd order suppression of VCO nonlinearity

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 76 / 80

Phase domain VCO-ADCVCO in feedback loop

VCO2

kv , fc

outVCO1

kv , fc

Vin

+

-

PD+- VCO2

kv , fc

VCO1

kv , fc

+

-

PD+-

register

f s

sampler

Dout(z)+−

DAC

Vi n

VCO performs integrationI pseudo differential

Phase detectorI can be largely digital

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 77 / 80

Phase domain VCO-ADCVCO in feedback loop

VCO2

kv , fc

VCO1

kv , fc

+

-

PD+-

register

f s

sampler

Dout(z)+−

DAC

Vi n

VCO performs integrationI pseudo differential

Phase detectorI can be largely digitalI can be multi-phase

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 78 / 80

VCO-ADC in sigma delta loopring oscillator VCO non-linearity

VCO2

kv , fc

VCO1

kv , fc

+

-

PD+-

register

f s

sampler

Dout(z)

DAC

loopfilter

+

-

Vi n

for e.g. 2nd order loop filterI 3rd order noise shapingI input signal of VCO smallI 3rd order suppression of VCO nonlinearity

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 79 / 80

ConclusionReview of

1 Sigma Delta Modulation

2 Continuous Time Sigma Delta Modulation

3 FoM Confusion

4 VCO ADC

5 Conclusion

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 80 / 80

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