continuous time sigma delta modulators and vco adcsims.unipv.it/casws2017/slides/rombouts.pdf ·...

Continuous Time Sigma DeltaModulators and VCO ADCs

Pieter Rombouts

Electronics and Information Systems Lab.,Ghent University,

Belgium

Pavia, March 2017

P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 1 / 80

Outline

1 Sigma Delta Modulation

2 Continuous Time Sigma Delta Modulation

3 FoM Confusion

4 VCO ADC

5 Conclusion

A/D converter: traditional interpretation

converts analog value into digitalnumber of bits n

I quantisation step q:

q = Vref /2n

error within ±q/2staircase I/O

I static nonlinearityI INL or DNL

A/D converter: other interpretationUI

converts analog signal into digital signalquantisation eror Q

I (white) noise signalI like other noise contributionsI number of bits not essential

F large enoughLeave margin for other noise sources

F effective bits

quantisation noise variance

σ2Q =

12P. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 4 / 80

Core concept 1: Oversamplingspectrum

spectrum

0.1 0.2 0.3 0.4 0.5

signal

white noise

0.1 0.2 0.3 0.4 0.5

frequency/fsample frequency/fsample

Oversampling ratio:

OSR =fS2f0

spectrum

0.1 0.2 0.3 0.4 0.5

signal

white noise

0.1 0.2 0.3 0.4 0.5

ideal digital filter after quantizerI averaging mechanismI number of bits has increasedI less noiseI filters signal as well

F not Nyquist-rate anymore!

spectrum

0.1 0.2 0.3 0.4 0.5

signal

white noise

0.1 0.2 0.3 0.4 0.5

quantisation noise variance

σ2Q =

12OSR∼ 1

3dB/octave improvement

The Σ∆ control loop

(a) (b)

S quantVin Vin+ +

DH S S

ideal DACfilter

I discrete timeI continuous time

(a) (b)

S quantVin Vin+ +

DH S S

1 + HVin +

1 + HQ

for low frequencies H ≈ ∞ −→ D ≈ Vin

nullator

1 + HVin +

1 + HQ︸︷︷︸

input signal is also filtered

for low frequencies NTF = 11+H ≈ 0

for high frequencies NTF = 11+H 6= 0

Core concept 2: ”Noise” Shaping

NTF(z)

fsample/2

for high frequencies NTF = 11+H 6= 0

spectral shaping

Core concept 2: “Noise” Shaping

(a) (b)

fsample/2 DC

fsample/2

signalshaped noise

noise spectrum has the shape of NTF

combine with oversampling −→ most noise vanishes

Σ∆ Modulators

(a) (b)

S quantVin Vin+ +

DH S S

quantizerI very few bitsI accuracy from oversampling + noise shapingI 1 bit

Σ∆ Modulators

(a) (b)

S quantVin Vin+ +

DH S S

1-bit quantizerI simpleI inherent linearI noise is not white

F tonesF stability

Σ∆ Modulators

(a) (b)

S quantVin Vin+ +

DH S S

multi-bit quantizerI better performanceI DAC needs linearization

F DEMF calibration

I always larger area

Σ∆ Modulators

(a) (b)

S quantVin Vin+ +

DH S S

filterI cascade of integratorsI order: design parameter

F trade-off complexity-performanceI special design techniques

F Richard Schreier’s toolbox

1st order, 1bit Σ∆ ModulatorTypical circuit

- biD Q

switched capdevices can be very small

I also CI (thermal) noise ↓ due to oversampling

High Order Σ∆ ModulatorsCascade of integrators with feedback

1z -1c2

v(n)y(n)x3(n)x2(n1z -1

c1x1(n)

without extra feed insI high swing on internal nodesI ‘poor’ distortion performance

High Order Σ∆ ModulatorsCascade of integrators with feedforward

1z -1c3

v(n)y(n)x3(n)x2(n1z -1

c2x1(n)

without extra feed insI negligible swing on internal nodesI excellent distortion performance

Σ∆ ADC

Sigma Deltamodulator

lowpassfilter

Vin anti-aliasingprefilter

f < fcutoff S

fS 2f0 Dout

f = fcutoff 0

analog digital

decimation filter

several filters in chainI simple anti-aliasing filterI no sample-to-sample correspondence

number of bits in Dout high enough

Σ∆ ADC

Sigma Deltamodulator

lowpassfilter

Vin anti-aliasingprefilter

f < fcutoff S

fS 2f0 Dout

f = fcutoff 0

analog digital

decimation filter

scientific literatureI without filtersI accuracy calculated from ideal filter

Low OSR?I keep fs feasableI need many quantizer bitsI need high order filterI minimum 8

High OSR?I small devices

F noise is filtered

I low filter orderI 1-bit quantiser

Outline

3 FoM Confusion

4 VCO ADC

5 Conclusion

CTSDM vs DTSDM

Σ∆ modulatorsI oversampling and noise shapingI high-accuracy

CTSDM vs DTSDM

Discrete-timeI versatileI “simple” designI easy to “abuse”

standard cell IP core

Continuous-timeI potential for higher speedI potential for lower powerI anti-aliasingI non-trivial design (needs tuning)I performance and stability depend on fclkI common myth: sensitive to clock jitter

Continuous Time Σ∆ modulator

. . .Vin(s)

Dout(z)

ZOH(s)ZOH(s)

−Σ Σ

−quant

closed feedback loopI cascade of integrators with feedbackI cascade of integrators with feedforward . . .

loop filter = continuous time

sampler inside loop

Continuous Time Σ∆ modulatorLinearized model

. . .Vin(s)

Dout(z)

ZOH(s)ZOH(s)

−Σ Σ

output contains two contributionsI Input signalI Quantisation noise

superposition

Quantization noise

. . .f s

Dout(z)

ZOH(s)ZOH(s)

−Σ Σ

ZOH(s)H(s)

Heq(z)

Dout(z)

equivalent discrete time loop filter Heq(z)I fully equivalentI impulse invariant transform of H(s)I CT - DT relationship: z = esTclk

Quantization noise

ZOH(s)H(s)

Heq(z)

Dout(z)

Heq + 1· Q = NTF · Q

equivalent to DT Σ∆ modulator

Quantization noise

ZOH(s)H(s)

Heq(z)

Dout(z)

remarksI theory = mature

F e.g. c2d function in matlab

I Heq depends on Dac-pulseI Heq depends on fsI Heq sensitive to analog imperfections

F ‘excess’ loop delayF parasitic (opamp) poles

Continuous Time Σ∆ modulatorLinearized model

. . .Vin(s)

Dout(z)

ZOH(s)ZOH(s)

−Σ Σ

output contains two contributionsI Input signalI Quantisation noise

superposition

Input signal

. . .Vin(s)

f sDout(z)

ZOH(s)ZOH(s)

−Σ Σ

Vin(s) Dout(z)G(s)

ZOH(s)H(s)

Heq(z)

Input signal

Vin(s) Dout(z)G(s)

ZOH(s)H(s)

Heq(z)

Vin(s) Dout(z)G(s)

AAF(s)

NTF(z)

equivalent to filter AAF (s) = G (s) ·NTF (z = esTclk)

followed by samplerP. Rombouts (Ghent University) CTSDMs and VCO ADCs Pavia 2017 33 / 80

Anti-Aliasing in CTSDM

AAF (s) = G (s)NTF (z)

Double filter effect in alias bands (around nfclk)I G (S) lowpass filterI NTF (z) notches at nfclk

Anti-Aliasing in CTSDM

2−8 2−7 2−6 2−5 2−4 2−3 2−2 2−1 20 21-100

Amplituderespon

se(dB)

NTFeq(esTs)

AAF (s)

N = 2a1 = 0.3246a2 = 0.6667

Feedback vs Feedforward

. . .Vin(s)

Dout(z)

ZOH(s)ZOH(s)

−Σ Σ

−quant

cascade of integrators with feedbackI double anti-aliasing: G (s) and NTF

F less stringent prefiltering requirementsI large internal signal swing

F more demanding opamps

I ADC itself = power hungry but system may be moreefficient

Feedback vs Feedforward

quantansT T

H (s)DAC

cascade of integrators with feedforwardI single anti-aliasing: NTF but G (s) does not filter

F stringent pre-filtering requirementsI small internal signal swing

F no demanding opamps

I ADC itself = efficient but system may be power hungry

Noise and power

quantansT T

H (s)DAC

First stage noise dominatesI later stages scaled

F lower powerF still negligible noise

First stage power dominates as wellI increasing order ⇒ moderate impact on power

Circuit Noise

Ev 2n = 4kTReff · B

noise sees anti-aliasing filterI only in band noiseI no kT/C noise

in theory much better than SC

‘Excess’ Loop delayCTSDM problems

quantansT T

H (s)DAC

parasitic loop delay

also parasitic poles

‘Excess’ Loop delayCTSDM problems

Σc1sTs−

Vin(s) Σc2sTs

Vout(z)

HDAC(s)

z−12

e−sτHDAC(s)

parasitic loop delayI make loop delay explicitI add compensation path

also for parasitic poles

Process variationsCTSDM problems

Σc1sTs−

Vin(s) Σc2sTs

Vout(z)

HDAC(s)

z−12

e−sτHDAC(s)

large errors on RC productsI tuneI robust design

Slew rateCTSDM problems

opamp not allowed to slewinjection of quantisation noise

I multi-bitI some filtering (e.g. FIR)

JitterCTSDM problems

Σc1sTs−

Vin(s) Σc2sTs

Vout(z)

HDAC(s)

z−12

e−sτHDAC(s)

jitter in outer feedback DACI directly affects performanceI depends on DAC pulse

JitterCTSDM problems

white jitterI catastrophicalI solution: multi-bit, FIR etc.

lowpass jitter (= reality)I no big deal

CTSDM vs DTSDM

Continuous-timeI inherent anti-aliasing

F no noise aliasingcfr kT/C noise in switched cam

F better power-noise trade offI common myth

F sensitive to clock jitter⇒ not as bad as widely assumed

I factsF performance and stability depend on fclkF non-trivial design

Outline

3 FoM Confusion

4 VCO ADC

5 Conclusion

Figure of Merit

Need for FOMI difficult to compare ADC architecturesI different Peak SNDR, Power, Bandwidth, Technology,

areaI which architecture for new design?

Figure of Merit

Walden’s FOM (1999)

FOMW =P

2ENOB 2 BW

I pJ/conversion code (or pJ/conversion step)I intended to reduce variablesI no justificationI used for many yearsI but meaningless . . .

Justifying Walden’s FOM?

FOMW =P

2ENOB 2 BW

in good design: P ∼ BWI OK

P ∼ 2N

Justifying Walden’s FOM?

P ∼ 2N ???

flash2N comparators

I OK if comparator powerconstant

comparator accuracy ∼ 2−N

I comparator power ∼ 2N

I comparator power ∼ 22N

oops . . .

Impedance Scaling laws

start from best design possibleneed 3dB better SNR

I scale impedances: factor 2

power: factor 4 per bit

FOM confusion

FOMW =P

2ENOB 2 BW

Walden fixed (scaling laws)

FOMW ,fixed =P

22·ENOB 2 BW

all high accuracy designs were rated bad . . .SAR’s were overrated . . .

FOM confusion

FOMW ,corrected =P

22·ENOB 2 BW

Walden fixed (scaling laws)I not used

correct FOM: Schreier’s FOM (2005)

FOMS = Peak SNDR + 10log10

Outline

3 FoM Confusion

4 VCO ADC

5 Conclusion

VCO-ADC: drivers

N stages Vdd

maininverters

auxinverters

quest for more digital ADC’sI ring oscillatorsI ‘digital’ signalsI no opamps

VCO-ADC naive

Vi n resetcounter

f sf s f sf s

accuracy ∼ fVCOfs

I e.g. 6-bit for fs = 1GHz, fVCO = 64GHz,

VCO-ADC equivalent

Vi n resetcounter

f sf s f sf s

Vi n counter

kv fcD

f sf s

I1 - z-1

VCO-ADC in phase domain

Vi n counter

kv fcD

f sf s

I DVCO1

kv fcD

f sf s

Vi nkv

I Di n1/skv

1 - z-1

phase = integral of frequency

edge occurs when phase = n · 2πphase information is quantized with step = 2π

VCO-ADC in phase domain

Vi nkv

f sf s

I Di n1/skv

f sf s

I D+ +

1 - z-1

D(z) ∼(Vin

(1− z−1

)∗+(1− z−1

)︸︷︷︸NTF

like 1st order CTSDMI anti-aliasingI noise shapingI boost accuracy by oversampling

multi-phase VCO-ADC

N stages Vdd

maininverters

auxinverters

untill now 1 VCO outputI ring oscillator has N output phases

use all N VCO-phasesI now phase transition at 2π/NI quantization error: N times smallerI higher effective number of bits

multi-phase VCO-ADC

use all N VCO-phasescounter triggered by N clock inputs?

I use parallelism

multi-phase VCO-ADC

VCOVi n

resetcounter

f sf s f sf s

resetcounter

f sf s f sf s

resetcounter

f sf s f sf s

E.g. N = 64 phases, fs = 1GHz, fVCO = 1GHz,I equivalent fs = 1GHz, fVCO = 64GHz,I 6-bit

multi-phase VCO-ADC

VCOVi n

resetcounter

f sf s f sf s

resetcounter

f sf s f sf s

resetcounter

f sf s f sf s

Reset counter?I special case: 1 bit counterI possible if fVCO ≤ fs

1-bit counter for VCO-ADCs

D QVCO[i]

TS><TS

reacts on both edgesI effectively fVCO,eff = 2fVCO

multi-phase VCO-ADC

w1(t)fff

w2(t)D Q D Q

D Q D Q

......

M-phases ring oscillator Readout circuit (xM)

2 important properties

multi-phase VCO-ADC

w1(t)fff

w2(t)D Q D Q

D Q D Q

......

output = barrel shifted thermometer encodedI inherent DWAI can drive unit element DACI summation = ‘thermometer to binary” coder

multi-phase VCO-ADC

w1(t)fff

w2(t)D Q D Q

D Q D Q

......

condition on fVCO :I 0 < fVCO < fs/2

typical sizing:I free running fVCO,0 = fs/4I KV for full scale swingI some tuning

VCO-ADC challenges

higher order noise shapingI current research

VCO non-linearity

VCO-ADC with high-order noise shaping

Current work at UGent‘digital’ 3rd order VCO ADC

I prototype in 65 nm CMOSI 12bits@10MHz (with digital calibration)I 11bits@10MHz (without digital calibration)I 3.5 mWI 0.01 mm2

VCO-ADC challenges

higher order noise shapingVCO non-linearity

I best: 11-bit linearity (UGent)I other solutions

F digital (self)-calibrationF swing reductionF embed in Sigma Delta Loop

Ghent University linear VCO circuitring oscillator VCO non-linearity

N stagesRing-Osc

Vin Ctrl

A. Babaie-Fishani and P. Rombouts,

“Highly linear VCO for use in VCO-ADCs,” Electron. Lett. 2016.

Ghent University linear VCO circuitring oscillator VCO non-linearity

0 0.2 0.4 0.6 0.8 1100

(a) Input voltage [volt]

0 0.2 0.4 0.6 0.8 1−3

(b) Input voltage [volt]VC

almost 12 bit linearity in pseudo differentialconfiguration

some noise penalty

digital (self)-calibrationring oscillator VCO non-linearity

Doutnon-linearity

f( )oversamplingnoise-shaping

modulator

digitalnon-linearity

correction

f-1( )Ddec

decimationVi n

look-up tableI nonlinearity is smoothI can be very small (11 points excellent results)

some calibration mechanism

Input swing reductionring oscillator VCO non-linearity

VCO resetcounter

f skv , fc

f +Dout(z)

0-1 mash structureI aux ADC and DAC

F uncritical

I sensitive to mismatch

VCO-ADC in sigma delta loopring oscillator VCO non-linearity

VCOresetcounter Dout(z)

f skv , fc

loopfilter

embed in Sigma Delta LoopI Original work by Perrott’s groupI input signal of VCO still large

for e.g. 2nd order loop filterI 3rd order noise shapingI 2nd order suppression of VCO nonlinearity

Phase domain VCO-ADCVCO in feedback loop

kv , fc

outVCO1

kv , fc

PD+- VCO2

kv , fc

register

sampler

Dout(z)+−

VCO performs integrationI pseudo differential

Phase detectorI can be largely digital

Phase domain VCO-ADCVCO in feedback loop

kv , fc

register

sampler

Dout(z)+−

VCO performs integrationI pseudo differential

Phase detectorI can be largely digitalI can be multi-phase

VCO-ADC in sigma delta loopring oscillator VCO non-linearity

kv , fc

register

sampler

Dout(z)

loopfilter

for e.g. 2nd order loop filterI 3rd order noise shapingI input signal of VCO smallI 3rd order suppression of VCO nonlinearity

ConclusionReview of

3 FoM Confusion

4 VCO ADC

5 Conclusion

continuous time sigma delta modulators and vco adcsims.unipv.it/casws2017/slides/rombouts.pdf ·...

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