vco report
TRANSCRIPT
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University of Southern California
EE599
Professor Hashemi
VCO3/31/06
Samuel Jia-Chi Chieh
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Introduction:
For this project assignment, we were to design a Voltage Controlled Oscillator
with low Phase noise. This problem of designing a VCO with low phase noise is a topic
that is reoccurring in Academia. Various methods have been examined, but the one that
has taken the most interest is the LC Oscillator. There has been a lot of work in the LCOscillator and many reasons why it is more superior. Proving that this topology is the
best is beyond the scope of this assignment, but the biggest reason why I choose this
topology is because of the simplicity behind it. Its differential nature gives it even morekudos. This is the basic design topology that I used:
As you can see, there are two setsof cross coupled transistors. The ideal
behind this is very similar to the currentsharing LNA that Razavi discusses. By
having both nMOS and pMOS crosscoupled pairs, the negative resistance is
pretty much doubled, making start-up even
safer than just defining a safety factor of 2.However, the downside of doing this is that
the swing will be constrained Vdd because
now the LC tank will sit at a DC level ofVdd/2. Using a plain cross coupled nMOS
LC oscillator has the advantage of having aswing of 2Vdd because the DC level that
the LC Tank sits at is Vdd. However, for
this project, since the design spec is aswing of 3V differential, this topology will
work just fine!
For this design, one of the most important things, if not the most important thing, is thedesign of the Inductor. As seen in class from both the Linear Time Variant theory and
Leesons equation, for an LC oscillator, one of the two degrees of freedoms that we have
to reduce the phase noise is through the design of the inductor. The higher the Q of theLC tank, the lower the phase noise will be. That is one of the more important things for
this topology, and the way we can do that is just by running ASITIC and giving it a
thorough amount of dimensions to sweep through to determine what the highest Q
inductor will be at 1.8GHz.
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Achieved Specs:
PerformanceMetric
SpecResults w/Asitic
Model and Gamma
Enhacement
Meet Specs??
fosc (GHz) 1.8 1.8 Yes
Tuning Range 10% 7.5% No
Supply Voltage (V) 1.8 1.8 Yes
Total Current (mA) < 10mA 5.893mA Yes
Total Power (mW) 18mW 10.6mW Yes
Phase Noise
(dBc/Hz)
f = 600kHz
< -120 -127 Yes
Differential Swing
(V)3 3 Yes
Output Load (pF)
Each side150 150 Yes
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Design Approach:
Since this is an LC Oscillator, the most important thing to do is to optimize the
LC Tank Q. As we saw in class, the Q of the inductor is our best attempt at lowering the
phase noise of the VCO.
Inductor Design:
How did I design the highest Q inductor at 1.8GHz? I harnessed the power ofASITIC and made it my slave. I ran a lengthy simulation sweeping a wide range of
values including the size, the width, the spacing, and the number of turns. After runningASITIC overnight, I had my results! Here is the highest Q inductor that I could design in
ASITIC at 1.8GHz.
ASITIC:
Spiral edge to edge: 500umMetal width: 80um
Metal Spacing: 7umTurns: 1.25
Toplevel metal: m6
Exit: m5
Pi Model:
L=1.397nH R=1.247C1= 374f R1=106.2
C2=331.7f R2=126
Q @ 1.8GHz = 9.33
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Design Cross Coupled pairs:
Now that the design of the inductor is complete, we have to design the actual
cross coupled pairs. To do this, the paper by Ham and Hajimiri is very helpful.
They propose that the tank loss is:
The first term, gon is the output conductance of the nMOS device. Likewise, gop is theoutput conductance of the pMOS device. Also, gv is conductance loss of the varactors.
Finally, gL is a familiar term, the loss of the inductor, what we solved for earlier.
To make things simple, I will assume that the dominant factor is the loss of the inductor
so:
Also, the effective transconductance is:
For oscillation startup to occur, these parameters must be met.(from Design and optimization of LC oscillators Hajimiri, Lee)
A Safety margin of 3 for startup!
Knowing what the transconductances of what the devices should be, we can size the
devices as well if we know what the current is:
The key to determining what current to use is knowing what region we want to operate
the oscillator in. For this project, since we want max swing, we probably want to operate
at the edge of the current limited region where we are starting to enter the voltage limitedregion.
W/L = 20u/0.25u 3 fingers
Lvoponk ggggg +++=tan2
Lk gg tan2
mpmntotalm ggg +=_2
k
mpmng
ggtan)3(
2
+
2
, tanL
kmpmn
ggandgg ==
mSggThus mpmn 5.8, =
Doxn IL
WCgmn 2=
ktotalm gg tanmin_
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Using the following relationship, we can solve for what the tail current should be. First
we need to note that at any one time, current is flowing through one of each of the crosscoupled pairs.
Therefore, Itail = 4.26mA
Knowing the gm and the current, the sizes of the transistors can be solved for. One
important thing is that the length of the transistor should be minimum so that the effectivecapacitance will be small as well.
Comparison:
Simulation Calculation
gm = 11mS gm = 8.5mS
Itail = 4.6mA Itail = 4.26mASingle-ended Swing = 1.5V Single-ended Swing = 1.5V
As can be seen, the calculated swing and simulated swing turn out to be the same. Mycalculations match my simulation. The only thing is the gm turns out to be just a little
higher than expected, but thats not even a bad thing, itll provide even more chance ofoscillation start-up.
Varactor Design:
The next component to design is the varactor. This is the key to making this
oscillator voltage controlled. Basically, itll provide the capacitance needed for the LCTank, but itll also be adjustable so that we can control the resonating frequency and thus
the frequency of oscillation. The one thing about the inversion mode varactor is that the
minimum value and maximum value of capacitance will dictate the maximum andminimum oscillation frequencies as well.
In designing the varactor, this is the design guide equation:
woscmin < wosc < woscmax
)176*(2*I1.5V
nodeatsignalended-singleafrom1.5Vofamplitudepeakpeak toaFor
2/
tail
_sin
max,tan
=
L
tailendedgle
tailk
gIV
II
minvar,maxvar,
11
LCw
LCosc
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A simple DC parametric simulation will determine the characteristics of the varactor.
This was the schematic I used and here are the results of my simuation:
As you can see, by varying the voltage V1, the capacitance will change, changing the
resonance frequency of the Tank as well.
W/L = 20u/0.25u 122 fingers
Phase Noise:
As defined by Thomas Lee and Ali Hajimiri, a general form for an ideal singlesideband noise spectral density is:
{ }
=
2
2
2log10
QP
kTL o
sig
where:
o = 1.8GHz
= 600KHzkT = 4.14E-21
Q = 9.33 (assuming inductor main limiting factor for LC Tank)
Psig = V2
max/Rloss = 0.01278
{ } HzdBcL /76.137=
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This would be a very rough estimate of what the phase noise really is, because there are
many other factors that this equation does not take into account. However, it does providea ball park figure of what the lowest achievable phase noise would be. It is actually pretty
close to the simulated value.
Calculation Simulation
-137.76 dBc/Hz -127 dBc/Hz
As a final note, as you can see in my design, I included a Tail capacitor. By adding this
capacitor, the drain current in effect gets shorted to ground, which is a good thing if youthink about noise. It reduces the duty cycle of the drain current, and this becomes
extremely important during the zero crossings, because this is where the oscillator is most
susceptible to perturbations. Therefore, this added capacitor can improve the overallphase noise behavior of the LC Oscillator. You can actually see the difference in
simulation:
Phase Noise (dBc/Hz)
Without Tail Cap -127
Without Tail Cap -125
Although its not that large of a change, it does improve the phase noise!
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Bibliography:
The Design of Low Noise Oscillators, Ali Hajimiri, Thomas Lee, Kluwer Academic
Publisher, 1999
Wireless CMOS Frequency Synthesizer Design, J. Craninckx, M. Steyaert, Kluwer
Academic Publisher, 1998
The Design of CMOS Radio-Frequency Integrated Circuits, Thomas Lee, Cambridge
Press 1998
Design of Analog CMOS Integrated Circuits, Behzad Razavi, McGraw-Hill, 2001
RF Microelectronics, Behzad Razavi, Prentice Hall, 1998
Concepts and Methods in Optimization of Integrated LC VCOs, Donhee Ham, AliHajimir, IEEE JSSC, Vol.36, No.6, June 2001
Design and Optimization of a Low Noise 2.4GHz CMOS VCO with Integrated LC Tank
and MOSCap Tuning, Donhee Ham, Ali Hajimiri, IEEE JSSC
Design and optimization of LC oscillators, Ali Hajimiri, Thomas Lee, IEEE JSSC,
1999
Design Issues in CMOS Differential LC Oscillators, Ali Hajimiri, Thomas Lee, IEEE
JSSC, 1999
Oscillator Phase Noise: A Tutorial, Thomas Lee, Ali Hajimiri, IEEE, JSSC, Vol 35,
NO. 3, March 2000
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PSS Testbench:
VCO Transient Testbench:
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VCO Core:
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Gamma Enhacement Model:
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The Whole Shabangabang:
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High Q Inductor loss:
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Single Ended PSS: (1.8GHz)
Node 1:
Node 2:
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Transient Differential: (1.8GHz)
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Transient Single Ended: (1.8GHz)
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Transient Drain Current: (1.8GHz)
As you can see from the waveforms, the Tail transistor is in Triode Region!
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VCO Tuning Characteristics
1.65
1.7
1.75
1.8
1.85
1.9
1.95
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
Tuning Voltage (Vctrl)
Tuning
Fre
quency(GHz)
VCO Tuning Characteristics:
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Phase Noise: