design and analysis of a novel 8t sram cell december 14, 2010 department of microelectronic...

Design and Analysis of A Novel 8T SRAM Cell

December 14, 2010

Department of Microelectronic Engineering&

Centre for Efficiency Oriented LanguagesUniversity College Cork, Ireland

&Synopsys, Ireland

Jiaoyan Chen, Dilip Vasudevan, Emanuel Popovici, Michel Schellekens, Peter Gillen

Email: chenj@ue.ucc.ie

ContentsContents

Motivation Architectures of 6T SRAM, 9T SRAM and our 8T SRAM Adiabatic and Non-Adiabatic Operations SNM Comparison Dynamic Power Static Power Conclusion

MotivationMotivation

Roadmap –Cell Area Trend(ITRS 2008)

Consumer Portable Power Consumption Trend

(ITRS 2008 update)

SOC Consumer Stationary Power Consumption (2008)

SRAM consumes a lot of power and area in chips.

Our aim is to built an efficient SRAM.

Conventional 6T SRAMConventional 6T SRAM

4

Technology:

90nm,65nm,45nm, 28nm…

Stability:

Static Noise Margin (SNM) is getting Down.

Leakage Power:

a) Subthreshold leakage current b) Gate oxide leakage current

9T SRAM9T SRAM

5

Features:

a) 2 sub-circuits:

Upper : Writing

Lower: Readingb) Minimal Sizing for the upper part

c) SNM is much better

d) Lower leakage Power (in super cut-off mode)

Z. Liu and V. Kursun, “Characterization of a novel nine-transistor sram cell,” IEEE Trans. Very Large Scale Integr. Syst., vol. 16, no. 4, pp. 488–492, 2008

Proposed 8T SRAMProposed 8T SRAM

6

Features:

a) 2 sub-circuits:

Upper :1. No GND Connection

2. Add One Sharing

transistor

Lower: Using PMOS

b) Half swing

BL and BL’ return to VDD/2

after writing or reading.

Adiabatic Operations: WritingPMOS P3 is used to meet the Adiabatic Principle:

No voltage difference before the transistor turns on

Adiabatic Operations: Reading

Simulation Waveforms

SNM Comparison (45nm)SNM Comparison (45nm)

Proposed 8T SRAM

Conventional 6T SRAM

Dynamic Power Comparison (1)Dynamic Power Comparison (1)

8*8

Array

1 Bit Cell

Dynamic Power Dynamic Power Comparison (2)Comparison (2)

62% 67%

Leakage Power AnalysisLeakage Power Analysis

Temperature VariationTemperature Variation

>90%

Process Variation (65nm)Process Variation (65nm) – TOX, VTH, U0 – TOX, VTH, U0

>90%

Process Variation (45nm)Process Variation (45nm) – TOX, VTH, U0 – TOX, VTH, U0

90%

ConclusionConclusion

Summary Efficient 8T SRAM architecture Improved SNM compared with 6T SRAM Very Low Dynamic and Leakage power

Future work Use 36nm, 28nm…Check performance particularly for

leakeage Further Enhance the Stability Fabricate and validate the proposed architecture

Thank You

Questions?