digital integrated circuits arithmetic circuits -...

Digital ICIntroduction

Digital Integrated Circuits

Arithmetic Circuits

Fuyuzhuo

Digital IC

A Generic Digital Processor

2

Inp

ut-

Ou

tpu

tMemory

Control

Datapath

Digital IC

Building Blocks for Digital

Architectures

• Arithmetic unit

• Bit-sliced datapath (adder, multiplier, shifter,

comparator, etc.)

• Memory

• RAM, ROM, Buffers, Shift registers

• Control

• Finite state machine (random logic.)\Counters

• Interconnect

• Switches\Arbiters\ Bus

3

Digital IC

An Intel Microprocessor

4

9-1

Mu

x9

-1 M

ux

5-1

Mu

x2

-1 M

ux

ck

1

CARRYGEN

SUMGE

N

+ LU

1000um

b

s0

s1

g6

4

su

m sumb

LU : Logical

Unit

SU

MS

EL

a

to Cache

node

1

RE

G

Itanium has 6 integer execution units like this

Digital IC

Bit-Sliced Design

5

Bit 3

Bit 2

Bit 1

Bit 0

Reg

iste

r

Ad

der

Sh

ifte

r

Mu

ltip

lex

er

ControlD

ata

-In

Da

ta-O

ut

Tile identical processing elements

Digital IC

Bit-Sliced Datapath

6

Adder stage 1

Wiring

Adder stage 2

Wiring

Adder stage 3

Bit s

lice

0

Bit s

lice

2

Bit s

lice

1

Bit s

lice

63

Sum Select

Shifter

Multiplexers

Lo

op

ba

ck B

us

From register files / Cache / Bypass

To register files / CacheL

oo

pb

ack B

us

Lo

op

ba

ck B

us

Digital IC

outline

• Adder• Datapath functional unit

• Comparators

• Shifters

• Multi-input Adders

• Multipliers

7

Digital ICIntroduction

Adders

Multitudes of contrivances were designed,and almost

endless drawings made, for the purpose of economizing

the time and simplifying the mechanism of carriage

__charles babbage, on difference engine No.1,1864

8

Digital IC

Outline

• Single-bit Addition

• Carry-Ripple Adder

• Carry-Skip Adder

• Carry-Lookahead Adder

• Carry-Select Adder

• Carry-Increment Adder

• Tree Adder

9

Digital IC

Outline

• Single-bit Addition

• Carry-Ripple Adder

• Carry-Skip Adder

• Carry-Lookahead Adder

• Carry-Select Adder

• Carry-Increment Adder

• Tree Adder

Slide 10

Digital IC

PGK• For a full adder, define what happens to carries

• Generate: Cout = 1 independent of C

• Propagate: Cout = C

• Kill: Cout = 0 independent of C

Slide 11

Digital IC

PGK• For a full adder, define what happens to carries

• Generate: Cout = 1 independent of C

G = A • B

• Propagate: Cout = C

P = A B

• Kill: Cout = 0 independent of C

K = ~A • ~B[Note]: sometimes using an alternate definition for (only for carry)

Slide 12

P = A +B → Co= AB+(A+B)Ci

P’ = A B → Co=AB+(AB)Ci

A=B=1,P=1,P’=0

Co=1+Ci Co=1+0

Co(G,P)=G+PCi

S(G,P)=PCi

Digital IC

Single-Bit Addition

Half Adder Full Adder

Slide 13

A B Cout S

0 0

0 1

1 0

1 1

A B C Cout S

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

A B

S

Cout

A B

C

S

Cout

out

S A B

C A B

out ( , , )

S A B C

C MAJ A B C

)C,B,A(MAJ=C)B+A(+BA=

C)B+A(+AB=C

C⊕P=C⊕B⊕A=

ABC+CBA+CBA+CBA=S

out

Digital IC

Single-Bit AdditionHalf Adder Full Adder

Slide 14

A B Cout S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

A B C Cout S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

A B

S

Cout

A B

C

S

Cout

out ( , , )

S A B C

C MAJ A B C

Kill

propagate

generate

),,()(

)(

CBAMAJCBABA

CBAABC

CPCBA

ABCCBACBACBAS

out

⊕⊕⊕

ABC

BAS

out

⊕

Digital IC

Full Adder Design 1

• implementation from eqns

Slide 15

out ( , , )

S A B C

C MAJ A B C

ABC

S

Cout

MA

J

ABC

A

B BB

A

CS

C

CC

B BB

A A

A B

C

B

A

CBA A B C

Cout

C

A

A

BB

Fewer than mentioned above because of

sharing some transistors for XOR gate)C,B,A(MAJ=C)B+A(+BA=

C)B+A(+AB=C

C⊕P=C⊕B⊕A=

ABC+CBA+CBA+CBA=S

out 26+3*2=32Tran.s

Digital IC

Full Adder Design 2• Factor S in terms of Cout

S = ABC + (A + B + C)(~Cout) Cout=MAJ(A,B,C)

• Critical path is usually C to Cout in ripple adder

Slide 16

)( ioi

iio

CBACABCS

ACBCABC

)C,B,A(MAJ=C)B+A(+BA=

C)B+A(+AB=C

C⊕P=C⊕B⊕A=

ABC+CBA+CBA+CBA=S

out

Digital IC

Full Adder Design 2

17

A B

B

A

Ci

Ci A

X

VDD

VDD

A B

Ci BA

B VDD

A

B

Ci

Ci

A

B

A CiB

Co

VDD

S

CMOS Full Adder 28 Transistors

)( ioi

iio

CBACABCS

ACBCABC

Digital IC

Mirror Adder-Stick Diagram

18

Ci

A B

VDD

GND

B

Co

A Ci

Co

Ci

A B

S

)( ioi

iio

CBACABCS

ACBCABC

Digital IC

The Mirror Adder

• NMOS and PMOS chains symmetrical.

• Transistor connected to Ci closest to the output

• Critical issue is the minimization of the

capacitance at node Co. The reduction of the

diffusion capacitances is particularly important

• The capacitance at node Co is composed of 4

diffusion cap., 2 internal gate cap., and 6 gate cap.

in the connecting adder cell

• All transistors in the sum stage can be mini. size

19

Digital IC

Inversions

• Critical path passes through majority gate

• Built from minority + inverter

• Eliminate inverter and use inverting full adder

Slide 20

Cout

Cin

B1

A1

B2

A2

B3

A3

B4

A4

S1

S2

S3

S4

C1

C2

C3

Digital IC Slide 21

Transmission Gate

S

S

D0

D1

YS

Mux

B

B

A

F=AB

0

AND

B

B

A

F=A+~B

1

Digital IC 22

Pass-Transistor Based

AM2

M1

B

S

S

S F

VDD

A

B

F

B

A

B

B

M1

M2

M3/M4

Multiplexer XOR

Digital IC 23

Complementary Pass

Transistor Logic

A

B

A

B

B B B B

A

B

A

B

F=AB

F=AB

F=A+B

F=A+B

B B

A

A

A

A

F=A@B

F=A@B

OR/NOR EXOR/NEXORAND/NAND

F

F

Pass-Transistor

Network

Pass-Transistor

Network

A

ABB

A

ABB

Inverse

(a)

(b)

Digital IC

A

C

S

S

B

B

C

C

C

B

BC

out

Cout

C

C

C

C

B

B

B

B

B

B

B

B

A

A

A

Full Adder Design 3

• Complementary Pass Transistor Logic (CPL)

• Slightly faster, but more area

Slide 24

)( ioi

iio

CBACABCS

ACBCABC

A@B~(A@B)~(A@B@C)

~A~B

A+B

(~A~B)C+~(AB)~C

AB

Digital IC

Full Adder Design 4

25

A@B

CBABAA

CBABAAAABCBAABC

CPCBA

ABCCBACBACBAS

out

)⊕()⊕(

)⊕()⊕(

⊕⊕⊕

Digital IC

A B C Cout S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

Manchester Carry Chain

26

Kill

propagate

generate

Partition

Digital IC

Manchester Carry Chain

CoC

i

Gi

Di

Pi

Pi

VDD

CoC

i

Gi

Pi

VDD

27

Digital IC

Manchester Carry Chain

28

G2

C3

G3

Ci,0

P0

G1

VDD

G0

P1

P2

P3

C3

C2

C1

C0

Digital IC

Stick Diagram

29

Pi + 1

Gi + 1

Ci

Inverter/Sum Row

Propagate/Generate Row

Pi

Gi

Ci - 1

Ci + 1

VDD

GND

Digital IC

Carry Propagate Adders

• N-bit adder called CPA

• Each sum bit depends on all previous carries

• How do we compute all these carries quickly?

Slide 30

+

BN...1

AN...1

SN...1

Cin

Cout

11111

1111

+0000

0000

A4...1

carries

B4...1

S4...1

Cin

Cout

00000

1111

+0000

1111

Cin

Cout

Digital IC

Carry-Ripple Adder

• Simplest design: cascade full adders

• Critical path goes from Cin to Cout

• Design full adder to have fast carry delay

Slide 31

Cin

Cout

B1

A1

B2

A2

B3

A3

B4

A4

S1

S2

S3

S4

C1

C2

C3

Digital IC

Generate / Propagate

• Equations often factored into G and P

• Generate and propagate for groups spanning i:j

• Base case

• Sum:

Slide 32

0:00:00inGCP0:00:00inGCP:

:

i j

i j

G

P

:

:

i i i

i i i

G G

P P

0:0 0

0:0 0

G G

P P

iS

Digital IC

G/ P Recursion Definition

• Equations often factored into G and P

• Generate and propagate for groups spanning i:j

• Base case

• Sum:

Slide 33

0:00:00inGCP𝑮𝒊:𝒋 = 𝑮𝒊:𝒌+𝑷𝒊:𝒌𝑮𝒌−𝟏:𝒋

𝑷𝒊:𝒋 = 𝑷𝒊:𝒌𝑷𝒌−𝟏:𝒋

𝑮𝒊:𝒊 = 𝑮𝒊 = 𝑨𝒊𝑩𝒊

𝑷𝒊:𝒊 = 𝑷𝒊 = 𝑨𝒊⊕𝑩𝒊

𝑮𝟎:𝟎 = 𝑮𝟎 = 𝑪𝒊

𝑷𝟎:𝟎 = 𝑷𝟎 = 𝟎

𝑺𝒊 = 𝑷𝒊⊕𝑮𝒊−𝟏:𝟎

Digital IC

PG Logic

Slide 34

S1

B1A1

P1G1

G0:0

S2

B2

P2G2

G1:0

A2

S3

B3A3

P3G3

G2:0

S4

B4

P4G4

G3:0

A4 Cin

G0 P0

1: Bitwise PG logic

2: Group PG logic

3: Sum logic

C0C1C2C3

Cout

C4

𝑮𝟎:𝟎 = 𝑮𝟎 = 𝑪𝒊

𝑷𝟎:𝟎 = 𝑷𝟎 = 𝟎

𝑮𝒊:𝒊 = 𝑮𝒊 = 𝑨𝒊 𝑩𝒊

𝑷𝒊:𝒊 = 𝑷𝒊 = 𝑨𝒊⊕𝑩𝒊

𝑮𝒊:𝒋 = 𝑮𝒊:𝒌+𝑷𝒊:𝒌𝑮𝒌−𝟏:𝒋

𝑷𝒊:𝒋 = 𝑷𝒊:𝒌𝑷𝒌−𝟏:𝒋

𝑺𝒊 = 𝑷𝒊⊕𝑮𝒊−𝟏:𝟎

Digital IC

Carry-Ripple Revisited

Slide 35

S1

B1

A1

P1

G1

G0:0

S2

B2

P2

G2

G1:0

A2

S3

B3

A3

P3

G3

G2:0

S4

B4

P4

G4

G3:0

A4

Cin

G0

P0

C0

C1

C2

C3

Cout

C4

𝑮𝒊:𝟎 = 𝑮𝒊+𝑷𝒊𝑮𝒊−𝟏:𝟎

Digital IC

Carry-Ripple PG Diagram

Slide 36

Dela

y

0123456789101112131415

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

Bit Position

𝒕𝒓𝒊𝒑𝒑𝒍𝒆 = 𝒕𝒑𝒈 + 𝑵− 𝟏 𝒕𝑨𝑶 +𝒕𝑿𝑶𝑹

Digital IC

PG Diagram Notation

i:j

i:j

i:k k-1:j

i:j

i:k k-1:j

i:j

Gi:k

Pk-1:j

Gk-1:j

Gi:j

Pi:j

Pi:k

Gi:k

Gk-1:j

Gi:j G

i:j

Pi:j

Gi:j

Pi:j

Pi:k

Black cell Gray cell Buffer

Slide 37

Digital IC

Higher-Valency Cells

i:j

i:k k-1:l l-1:m m-1:j

Gi:k

Gk-1:l

Gl-1:m

Gm-1:j

Gi:j

Pi:j

Pi:k

Pk-1:l

Pl-1:m

Pm-1:j

Slide 38

Did you know?

Digital IC

Manchester Carry Chain

39

))((

)(

:

:

:

:

0112233033

01122022

011011

0000

CPGPGPGGC

CPGPGGC

CPGGC

CGC

Digital IC

Manchester Carry Chain

40