ee141 digital integrated circuit design manufacturing 1 manufacturing process digital integrated...

Post on 05-Jan-2016

232 Views

Category:

Documents

1 Downloads

Preview:

Click to see full reader

TRANSCRIPT

EE141Digital Integrated Circuit Design Manufacturing1

ManufacturingManufacturingProcessProcess

Digital Integrated Digital Integrated Circuit DesignCircuit DesignAndrea BonfantiDEIBVia Golgi 40, Milano

EE141Digital Integrated Circuit Design Manufacturing2

CMOS ProcessCMOS Process

n-well CMOS Processn-well CMOS Process

EE141Digital Integrated Circuit Design Manufacturing3

Twin-well CMOS ProcessTwin-well CMOS Process

p-well n-well

p+

p-epi

SiO2

AlCu

poly

n+

SiO2

p+

gate-oxide

Tungsten

TiSi2

Twin-well Trench-Isolated CMOS ProcessTwin-well Trench-Isolated CMOS Process

EE141Digital Integrated Circuit Design Manufacturing4

Triple-well CMOS ProcessTriple-well CMOS Process

EE141Digital Integrated Circuit Design Manufacturing5

Circuit Under DesignCircuit Under Design

VDD VDD

VinVout

M1

M2

M3

M4

Vout2

EE141Digital Integrated Circuit Design Manufacturing6

Its Layout ViewIts Layout View

metal1

poly

contact

nwell

p+ diffusion

p+ diffusion

n+ diffusion

n+ diffusion

EE141Digital Integrated Circuit Design Manufacturing7

Its Layout View (2)Its Layout View (2)

EE141Digital Integrated Circuit Design Manufacturing8

Its Layout View (2)Its Layout View (2)

EE141Digital Integrated Circuit Design Manufacturing9

Its Layout View (2)Its Layout View (2)

EE141Digital Integrated Circuit Design Manufacturing10

oxidation

opticalmask

processstep

photoresist coatingphotoresistremoval (ashing)

spin, rinse, dryacid etch

photoresist

stepper exposure

development

Typical operations in a single photolithographic cycle (from [Fullman]).

Photo-Lithographic ProcessPhoto-Lithographic Process

EE141Digital Integrated Circuit Design Manufacturing11

Patterning of SiOPatterning of SiO22

Si-substrate

Si-substrate Si-substrate

(a) Silicon base material

(b) After oxidation and depositionof negative photoresist

(c) Stepper exposure

PhotoresistSiO2

UV-light

Patternedoptical mask

Exposed resist

SiO2

Si-substrate

Si-substrate

Si-substrate

SiO2

SiO2

(d) After development and etching of resist,chemical or plasma etch of SiO2

(e) After etching

(f) Final result after removal of resist

Hardened resist

Hardened resist

Chemical or plasmaetch

EE141Digital Integrated Circuit Design Manufacturing12

CMOS Process at a GlanceCMOS Process at a GlanceDefine active areasEtch and fill trenches

Implant well regions

Deposit and patternpolysilicon layer

Implant source and drainregions and substrate contacts

Create contact and via windowsDeposit and pattern metal layers

EE141Digital Integrated Circuit Design Manufacturing13

CMOS Process Walk-ThroughCMOS Process Walk-Through

p+

p-epi (a) Base material: p+ substrate with p-epi layer

p+

(c) After plasma etch of insulatingtrenches using the inverse of the active area mask

p+

p-epiSiO2

3SiN

4

(b) After deposition of gate-oxide andsacrificial nitride (acts as abuffer layer)

EE141Digital Integrated Circuit Design Manufacturing14

CMOS Process Walk-ThroughCMOS Process Walk-ThroughSiO2

(d) After trench filling, CMP planarization, and removal of sacrificial nitride

(e) After n-well and VTp adjust implants

n

(f) After p-well andVTn adjust implants

p

EE141Digital Integrated Circuit Design Manufacturing15

CMOS Process Walk-ThroughCMOS Process Walk-Through

(g) After polysilicon depositionand etch

poly(silicon)

(h) After n+ source/drain andp+ source/drain implants. These

p+n+

steps also dope the polysilicon.

(i) After deposition of SiO2insulator and contact hole etch.

SiO2

EE141Digital Integrated Circuit Design Manufacturing16

CMOS Process Walk-ThroughCMOS Process Walk-Through

(j) After deposition and patterning of first Al layer.

Al

(k) After deposition of SiO2insulator, etching of via’s,

deposition and patterning ofsecond layer of Al.

AlSiO2

EE141Digital Integrated Circuit Design Manufacturing17

MetallizationMetallization

EE141Digital Integrated Circuit Design Manufacturing18

Advanced MetallizationAdvanced Metallization

EE141Digital Integrated Circuit Design Manufacturing19

Design RulesDesign Rules

EE141Digital Integrated Circuit Design Manufacturing20

3D Perspective3D Perspective

Polysilicon Aluminum

EE141Digital Integrated Circuit Design Manufacturing21

Design RulesDesign Rules

Interface between designer and process engineer

Guidelines for constructing process masks Unit dimension: minimum line width

scalable design rules: lambda parameter absolute dimensions (micron rules)

EE141Digital Integrated Circuit Design Manufacturing22

Single-well CMOS Process LayersSingle-well CMOS Process Layers

Layer

Polysilicon

Metal1

Metal2

Contact To Poly

Contact To Diffusion (ntap, ptap)

Via

Well (n)

Active (diffuision n+ or p+)

Color Representation

Yellow

Green

Red

Blue

Magenta

Black

Black

Black

Select (n+) Green

EE141Digital Integrated Circuit Design Manufacturing23

Layers in 0.25 Layers in 0.25 m CMOS processm CMOS process

EE141Digital Integrated Circuit Design Manufacturing24

Intra-Layer Design RulesIntra-Layer Design Rules

Metal24

3

10

90

Well

Active3

3

Polysilicon

2

2

Different PotentialSame Potential

Metal13

3

2

Contactor Via

Select

2

or6

2Hole

EE141Digital Integrated Circuit Design Manufacturing25

Transistor Layout (PMOS)Transistor Layout (PMOS)

1

2

5

3

Tra

nsis

tor

EE141Digital Integrated Circuit Design Manufacturing26

Vias and ContactsVias and Contacts

1

2

1

Via

Metal toPoly ContactMetal to

Active Contact

1

2

5

4

3 2

2

EE141Digital Integrated Circuit Design Manufacturing27

Select LayerSelect Layer

1

3 3

2

2

2

WellSubstrate

Select3

5

EE141Digital Integrated Circuit Design Manufacturing28

CMOS Inverter LayoutCMOS Inverter Layout

A A’

np-substrate Field

Oxidep+n+

In

Out

GND VDD

(a) Layout

(b) Cross-Section along A-A’

A A’

EE141Digital Integrated Circuit Design Manufacturing29

Layout EditorLayout Editor

EE141Digital Integrated Circuit Design Manufacturing30

Design Rule CheckerDesign Rule Checker

EE141Digital Integrated Circuit Design Manufacturing31

Design Rule CheckerDesign Rule Checker

EE141Digital Integrated Circuit Design Manufacturing32

The final resultThe final result

EE141Digital Integrated Circuit Design Manufacturing33

PackagingPackaging

EE141Digital Integrated Circuit Design Manufacturing34

Packaging RequirementsPackaging Requirements

Electrical: low parasitics Mechanical: reliable and robust Thermal: efficient heat removal Economical: cheap

EE141Digital Integrated Circuit Design Manufacturing35

Bonding TechniquesBonding Techniques

Lead Frame

Substrate

Die

Pad

Wire Bonding

EE141Digital Integrated Circuit Design Manufacturing36

Tape-Automated Bonding (TAB)Tape-Automated Bonding (TAB)

(a) Polymer Tape with imprinted

(b) Die attachment using solder bumps.

wiring pattern.

Substrate

Die

Solder BumpFilm + Pattern

Sprockethole

Polymer film

Leadframe

Testpads

EE141Digital Integrated Circuit Design Manufacturing37

Flip-Chip BondingFlip-Chip Bonding

Solder bumps

Substrate

Die

Interconnect

layers

EE141Digital Integrated Circuit Design Manufacturing38

Package-to-Board InterconnectPackage-to-Board Interconnect

(a) Through-Hole Mounting (b) Surface Mount

EE141Digital Integrated Circuit Design Manufacturing39

Package TypesPackage Types

EE141Digital Integrated Circuit Design Manufacturing40

Package ParametersPackage Parameters

EE141Digital Integrated Circuit Design Manufacturing41

Multi-Chip ModulesMulti-Chip Modules

top related