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ENGR-4300 Test 3 Spring 2010
1 of 12
ENGR-4300
Spring 2010
Test 3
Name ___________________
Section 1(MR 8:00) 2(MR 4:00) 3(TF 8:00)
(circle one)
Question I (20 points) ___________
Question II (20 points) ___________
Question III (20 points) ___________
Question IV (20 points) ___________
Question V (20 points) ___________
Total (100 points): ______________
On all questions: SHOW ALL WORK. BEGIN WITH FORMULAS, THEN
SUBSTITUTE VALUES AND UNITS. No credit will be given for numbers that
appear without justification. Be sure to read the entire quiz before solving any
problems.
ENGR-4300 Test 3 Spring 2010
2 of 12
Question I – Astable Multivibrator (20 points)
1. (4pt) The 555 timer circuit shown is to have a
duty cycle of 80% (4/5). For a given C1, what
ratio of resistors R1/R2 will produce this duty
cycle
T R R C1 0693 1 2 1 . ( )
T R R C 0693 1 2 2 1. ( )
T
T
R R C
R R C
R R
R R
1 0 693 1 2 1
0 693 1 2 2 1
1 2
1 2 28
. ( )
. ( * ).
R
R
1
23
2. (4pt) Using this ratio of R1/R2 and C1 = 10F, calculate the values for R1 and R2 needed to
yield a frequency of 20Hz.
fR R C R R
144
1 2 2 120
144
3 2 2 2 10 5
.
( )
.
( )
R k2 144 . and R k1 4 32 .
3. (2pt) For an ideal 555, what are the maximum and minimum voltages on pin 2 above during
normal operation?
Max = 6V, Min = 3 because of the internal divider of the 555
4. (4pt) For an ideal 555, what are the maximum and minimum voltages on pin 7 above during
normal operation?
Min = 0 since on pin 7 the transistor connects to zero
Max = 6V plus the voltage across R2 or 6 + (0.25)3=6.75V
On the next page, the freq must be 20 Hz so the period must be 1/20=50ms so the 3rd
plot is out.
The 2nd
plot has the correct frequency. The first plot does not have an 80% duty cycle, so it has
to be the middle plot. The individual curves must satisfy the voltages listed above so they are as
labeled.
X1
555D
GN
D1
TRIGGER2
OUTPUT3
RESET4
CONTROL5
THRESHOLD6
DISCHARGE7
VC
C8
V1
9Vdc
0
Rload
R1
R2
C1 C2 0.01u
ENGR-4300 Test 3 Spring 2010
3 of 12
Question I – Astable Multivibrator (continued)
5. (6pt) Which of the sets of plots below shows the voltages on pins 2, 3, 6 and 7 for the case
considered here? Label which plot is which in the correct figure.
Time
0s 0.05s 0.10s 0.15s 0.20s 0.25s 0.30s 0.35s 0.40s 0.45s 0.50s 0.55s 0.60s 0.65s 0.70s 0.75s 0.80s 0.85s 0.90s 0.95s 1.00s
V(R3:1) V(X1:TRIGGER) V(R1:2)
-2V
0V
2V
4V
6V
8V
10V
Time
0s 20ms 40ms 60ms 80ms 100ms 120ms 140ms 160ms 180ms 200ms 220ms 240ms 260ms 280ms 300ms 320ms 340ms 360ms 380ms 400ms
V(R3:1) V(X1:TRIGGER) V(R1:2)
-2V
0V
2V
4V
6V
8V
10V
Time
0s 20ms 40ms 60ms 80ms 100ms 120ms 140ms 160ms 180ms 200ms 220ms 240ms 260ms 280ms 300ms 320ms 340ms 360ms 380ms 400ms
V(R3:1) V(X1:TRIGGER) V(R1:2)
-2V
0V
2V
4V
6V
8V
10V
3
2,6
7
ENGR-4300 Test 3 Spring 2010
4 of 12
Question II – Combinational Logic Circuits (20 points)
1. Complete the table below for the circuit above (8 pts: all or nothing, continuation of mistakes
will be deducted)
A B Not A Not B G D E F C
0 0 1 1 0 1 1 0 1
0 1 1 0 1 0 0 1 1
1 0 0 1 0 1 1 0 1
1 1 0 0 0 1 1 0 1
2. Complete the table below for the circuit above (6 pts: all or nothing, continuation of mistakes
will be deducted)
A B Mehmed Chris C
0 0 Abouzar Dylan
0 1 David Dave
1 0 Yiran
1 1 Jun Last Names OK
U1A
7400
1
23
U1B
7400
4
56
U2A
7402
2
31
U2B
7402
5
64
U3A
7410
1122
13
A
B
C
U4A
7404
1 2
U4B
7404
3 4
U1A
7400
1
23
U2B
7400
4
56
U2C
7402
8
9 10
U3B
7402
5
6 4
U3C
7410
9810
11
B
A
C
U4A
7404
1 2
U5B
7404
3 4
U6A
7402
2
3 1
U7A
7400
1
23
D
E
F
G
ENGR-4300 Test 3 Spring 2010
5 of 12
Question II – Combinational Logic Circuits (continued)
3. Complete the table below for the circuit above (6pt: all or nothing, continuation of mistakes
will be deducted) This combination of gates performs the function of a single gate. Identify that
gate. XOR
A B D E F G C
0 0 1 1 0 1 0
0 1 1 0 0 0 1
1 0 0 1 0 0 1
1 1 0 0 1 0 0
U1A
7402
2
31
U1B
7402
5
64
U1C
7402
8
910
U1D
7402
11
1213
U2A
7402
2
31
A
CB
D
E
F
G
ENGR-4300 Test 3 Spring 2010
6 of 12
Question III – Sequential Logic Circuits (20 points)
CLKDSTM1OFFT IME = .5mS
ONTIME = .5mSDELAY = 0
ST ART VAL = 0OPPVAL = 1
CLKDSTM2OFFT IME = 1s
ONTIME = .02mDELAY = 0
ST ART VAL = 0OPPVAL = 1
U1A
74393
A1
QA3
QB4
QC5
QD6
CL
R2
U2A
7404
1 2
U2B
7404
3 4
U2C
7404
5 6
U2D
7404
9 8
U4A
74107
J1
K4
CL
R13
Q3
Q2CLK
12
U4B
74107
J8
K11
CL
R10
Q5
Q6CLK
9
U5A
7437
1
23
VV
VV
V
V
V
V
V
V
V
V
In the circuit pictured above, clock DSTM1 provides a clock signal to a counter and two flip
flops. The flip flops are clocked one half cycle after the counter to allow for propagation of the
signals through the gates. (The counter changes on the negative edge of DSMT1 and the flop
flops change on the negative edge of U2A:Y.) DSTM2 provides an initial reset pulse to both
chips. This is required by PSpice to ensure that all sequential devices start in a known state.
1. The timing diagram below shows the reset pulses and the clock signals. Sketch the following
signals in the space provided: the output from the counter (U1A:QA, U1A:QB, & U1A:QC); the
output from the combinational logic (U2C:Y=U4A:J, U5A:Y=U4A:K=U4B:J, &
U2D:Y=U4B:K); and the output from the flip flops (U4A:Q & U5A:Q). (2pt per trace = 16pt)
U1A:QA
U1A:QB
U1A:QC
U4A:J
U5A:Y
U4B:K
U4A:Q
U4B:Q Same problem as in fall 2008
ENGR-4300 Test 3 Spring 2010
7 of 12
2. A 4-bit counter is cleared and then receives a string of clock pulses. What are QA, QB, QC
and QD after 9 clock pulses? Clearly indicate the state of each signal. (2pt)
1001 is the number 9
3. A 4-bit counter is cleared and then receives a string of clock pulses. What are QA, QB, QC
and QD after 25 clock pulses? Clearly indicate the state of each signal. (2pt)
25 – 16 = 9 so it is 1001, it cycles through the entire 1 to 15 back to 0 (sixteen steps) then 9 more
steps to get to 25 clock pulses.
ENGR-4300 Test 3 Spring 2010
8 of 12
Question IV – Switching Circuits (20 points)
Another Switch from PSpice
1. In the PSpice library, there are many devices modeled that we have not yet studied. One such
device is shown in the circuit below.
The source voltage and the voltage at the bottom right pin of this device are shown below.
(4pt) Using the information from the circuit diagram and from the plot, determine the switching
rules for this device in terms of VT and VH.
It is switching at 1.5V and -.5V or at VT+VH and VT-VH
(1pt) What does the H stand for in VH?
Hysteresis … the hysteresis is actually 2VH
R1
100
+
-
+
-
S1
S_ST
VH = 1.0VVT = 0.5V
V1
FREQ = 1kVAMPL = 2VOFF = 0 V2
1Vdc
00
V
V
Time
0s 0.2ms 0.4ms 0.6ms 0.8ms 1.0ms 1.2ms 1.4ms 1.6ms 1.8ms 2.0ms 2.2ms 2.4ms 2.6ms 2.8ms 3.0ms
V(S1:1) V(R1:1)
-2.0V
-1.5V
-1.0V
-0.5V
0.0V
0.5V
1.0V
1.5V
2.0V
ENGR-4300 Test 3 Spring 2010
9 of 12
Relay Model
2. Using a variation of this switch, we can model a relay
(8pt) Running PSpice, we can observe the voltages at the 4 locations indicated above. Label
which is which in the figure below.
3. (6pt) Assume that we replace the source with a DC voltage of either 5V or 0V. Fill out the
following table with the voltages at the four locations. Close answers are OK.
A B C D
0V 3.15 0 0
5V .05 5 6
4. (1pt) In problem II, you will receive full credit for part 2 if you write the name (first or last) of
any teaching assistant in this course in the table. Now back to this question. For the following
figures, circle any that are not switches. All are switches
V3
TD = 0
TF = .5msPW = 0PER = 1ms
V1 = -2.5
TR = .5ms
V2 = 2.5
R2
1k
U1A
7414
1 2
Q1
Q2N2222
R3
1k
R4
1k
R5
1k
0
+
-
+
-
S2
S
VON = 4.0VVOFF = 3.0V
V4
9Vdc
R6
2k
R7
1k
VV
V
V
Time
0s 0.2ms 0.4ms 0.6ms 0.8ms 1.0ms 1.2ms 1.4ms 1.6ms 1.8ms 2.0ms 2.2ms 2.4ms 2.6ms 2.8ms 3.0ms 3.2ms 3.4ms 3.6ms 3.8ms 4.0ms
V(S2:1) V(R6:1) V(R2:1) V(R3:1)
-3.0V
-2.0V
-1.0V
0.0V
1.0V
2.0V
3.0V
4.0V
5.0V
6.0V
C
B A
D
D
A
B
C
ENGR-4300 Test 3 Spring 2010
10 of 12
Question V – Comparators and Schmitt Triggers (20 points)
There are almost unlimited applications of light sensors (more on these in Experiment 8)
including such simple and important devices as the beam break sensors used to protect children
from closing garage doors. The Schmitt Trigger plays a critical role in the design of such
devices. In the circuit below, the voltage source represents the signal coming from the light
sensor. The output of the Schmitt Trigger is then used to control the power to some device, such
as a garage door.
1. (2pt) What property of the Schmitt Trigger is being used in such an application?
Hysteresis
2. (3pt) Assume that we wish to design a system that turns off the garage door power when the
signal from the light beam drops to 2/3 of its typical value (call it Vo) and then turns it back on at
1/3 of its typical value. On the axes below sketch the general input-output curve for this
application. Be sure to scale both axes.
U1
uA741
+3
-2
V+7
V-4
OUT6
OS11
OS25
V1
12Vdc
V2
0Vdc
0
0
R1
1k
R2
R3
0
0
V3
0
V4
TD = 0.5ms
TF = .2ms
PW = 1ms
PER = 3ms
V1 = 0
TR = .2ms
V2 = 12
V
V
Vin
Vout
Vo
.33Vo
.67Vo
ENGR-4300 Test 3 Spring 2010
11 of 12
Question V – Comparators and Schmitt Triggers (continued)
3. (6pt) Set up the equations to find appropriate values for R2, R3, and V3 in the circuit above in
terms of the op-amp’s supply voltages and the desired switch points for the light beam detector.
vR
R Rv V Vout
3
2 3
3 3 so that vR
R RV V
3
2 3
12 3 3and
vR
R RV V
3
2 3
0 3 3
5. (4pt) Given that R3 = 2k, find the values of R2 and V3. (hint: two equations two unknowns:
simplify v+high and/or v+low)
R2 = 4k and V3 = 6V
6. (5pt) If the circuit below is built (note: new op-amp V+ supply), which of the following plots
correctly shows the voltage at the load for the given input conditions?
U1
uA741
+3
-2
V+7
V-4
OUT6
OS11
OS25
V1
15Vdc
V2
0Vdc
0
0
R1
1k
0
00
V4
TD = 0.5ms
TF = .2ms
PW = 1ms
PER = 3ms
V1 = 0
TR = .2ms
V2 = 12
R2
10k
R3
1k
V3
4Vdc
V
V
ENGR-4300 Test 3 Spring 2010
12 of 12
v 1
1115 4 4 5 and v
1
110 4 4 36. so it is the bottom plot. It is hard to read
the numbers exactly, but the others are quite far from these values.
Time
0s 0.2ms 0.4ms 0.6ms 0.8ms 1.0ms 1.2ms 1.4ms 1.6ms 1.8ms 2.0ms 2.2ms 2.4ms 2.6ms 2.8ms 3.0ms
V(V4:+) V(R2:2)
0V
2V
4V
6V
8V
10V
12V
14V
16V
Time
0s 0.2ms 0.4ms 0.6ms 0.8ms 1.0ms 1.2ms 1.4ms 1.6ms 1.8ms 2.0ms 2.2ms 2.4ms 2.6ms 2.8ms 3.0ms
V(V4:+) V(R2:2)
0V
2V
4V
6V
8V
10V
12V
14V
16V
Time
0s 0.2ms 0.4ms 0.6ms 0.8ms 1.0ms 1.2ms 1.4ms 1.6ms 1.8ms 2.0ms 2.2ms 2.4ms 2.6ms 2.8ms 3.0ms
V(V4:+) V(R2:2)
0V
2V
4V
6V
8V
10V
12V
14V
16V
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