eric allender rutgers university dual vp classes joint work with anna gál (u. texas) and ian mertz...

Eric AllenderRutgers University

Dual VP ClassesDual VP Classes

Joint work with

Anna Gál (U. Texas) and Ian Mertz (Rutgers)

MFCS, Milan, August 27, 2015

Eric Allender: Dual VP Classes < 2 >

Our ContributionsOur Contributions

New characterizations of ACC1 and TC1. New examples of fan-in reduction. Highlight connections between ACC1 and VP. Revisit the Immerman-Landau Conjecture,

and offer some new conjectures about circuit complexity classes.

But first …let’s review the relevant complexity classes.

Eric Allender: Dual VP Classes < 3 >

NP

P

AC1

NL

L

NC1

AC0

Log-Depth

Poly-size

Fan-in 2

Unbounded

Fan-in

Fan-in is

Important!

Eric Allender: Dual VP Classes < 4 >

NP

P

AC1

SAC1=LogCFL

NL

L

NC1

AC0

Log-Depth

Poly-size

Fan-in is

Important!

Semi-unbounded

fan-in

Λ fan-in 2

V fan-in nk

Eric Allender: Dual VP Classes < 5 >

NP

P

TC1

AC1

SAC1=LogCFL

NL

L

NC1

TC0

AC0

Components are

Important!

Log

depth

O(1)

depth

Majority gates

Eric Allender: Dual VP Classes < 6 >

P#P

NP

P

TC1

AC1

SAC1=LogCFL

NL

L

NC1

TC0

AC0

L#L = LDet(Q)

Eric Allender: Dual VP Classes < 7 >

P#P =PVNP(Q)

NP

P

TC1

AC1

SAC1=LogCFL

NL

L

NC1

TC0

AC0

L#L = LDet(Q)

L#LogCFL = LVP(Q)

Eric Allender: Dual VP Classes < 8 >

Valiant’s Class VPValiant’s Class VP

VP(R) is the class of families (fn) of multivariate polynomials over R such that

– fn has degree nO(1).

– There is a family of arithmetic circuits (Cn) of size poly(n) such that Cn computes fn.

Furthermore, Cn can be assumed to have depth O(log n) with fan-in 2 x and unbounded fan-in +. (Semiunbounded fan-in arithmetic circuits.)

#SAC1 = the functions in VP(N).

Eric Allender: Dual VP Classes < 9 >

P#P =PVNP(Q)

NP

P

TC1

AC1

SAC1=LogCFL

NL

L

NC1

TC0

AC0

L#L = LDet(Q)

L#LogCFL = LVP(Q)

Eric Allender: Dual VP Classes < 10 >

P#P =PVNP(Q)

NP

P

TC1

AC1

SAC1=LogCFL

NL

L

#NC1(Q)

NC1

TC0

AC0

L#L = LDet(Q)

L#LogCFL = LVP(Q) =L#SAC1

# AC1(Q)

Not contained in

P for a trivial reason:

The output has more

than poly-many bits.

Eric Allender: Dual VP Classes < 11 >

P#P =PVNP(Q)

NP

P

TC1

AC1

SAC1=LogCFL

NL

L

#NC1(Q)

NC1

TC0

AC0

L#L = LDet(Q)

L#LogCFL = LVP(Q) =L#SAC1

= # AC1(Fpn)

≈ # NC1(Fpn)

LVP(Fpn) =

The meaning of

Fpn is: Circuit

Cn is interpreted

modulo the

nth prime.

= # AC0(Fpn) ≈ # AC0(Q)

Eric Allender: Dual VP Classes < 12 >

P#P =PVNP(Q)

NP

P

TC1

ACC1

AC1

SAC1=LogCFL

NL

L

#NC1(Q)

NC1

TC0

ACC0

AC0

L#L = LDet(Q)

L#LogCFL = LVP(Q) =L#SAC1

= # AC1(Fpn)

LVP(Fpn) =

ACCi =

Um ACi[m]

= Uq # AC0(Fq)

= Uq # AC1(Fq)

Eric Allender: Dual VP Classes < 13 >

P#P =PVNP(Q)

NP

P

TC1

ACC1

AC1

SAC1=LogCFL

NL

L

#NC1(Q)

NC1

TC0

ACC0

AC0

L#L = LDet(Q)

L#LogCFL = LVP(Q) =L#SAC1

= # AC1(Fpn)

LVP(Fpn) =Our focus

lies here.

Eric Allender: Dual VP Classes < 14 >

Dual VP ClassesDual VP Classes

VP(R): Unbounded +

Bounded x

SAC1=LogCFL =

VP(B2): Unbounded V

Bounded Λ

But LogCFL is closed under complement!

[BCDRT]

Eric Allender: Dual VP Classes < 15 >

Dual VP ClassesDual VP Classes

VP(R): Unbounded +

Bounded x

SAC1=LogCFL =

VP(B2): Unbounded V

Bounded Λ

=

Unbounded Λ

Bounded V

Eric Allender: Dual VP Classes < 16 >

Dual VP ClassesDual VP Classes

VP(R): Unbounded +

Bounded x

SAC1=LogCFL =

VP(B2): Unbounded V

Bounded Λ

=

ΛP(B2): Unbounded Λ

Bounded V

ΛP(R): Unbounded x

Bounded +

Is this interesting??

Eric Allender: Dual VP Classes < 17 >

New Characterizations of ACC1New Characterizations of ACC1

ACC1= Uq #AC1(Fq)

= Uq ΛP(Fq) Fan-in Reduction

(from unbounded to semiunbounded) #AC1(Fq) = AC1[q(q-1)]

ΛP(Fq) = AC1[q-1]

Eric Allender: Dual VP Classes < 18 >

…and TC1…and TC1

ACC1= Uq #AC1(Fq)

= Uq ΛP(Fq) Fan-in Reduction

(from unbounded to semiunbounded) #AC1(Fq) = AC1[q(q-1)]

ΛP(Fq) = AC1[q-1]

TC1 = # AC1(Fpn) = LΛP(Fpn)

Eric Allender: Dual VP Classes < 19 >

Boolean Fan-In ReductionBoolean Fan-In Reduction

By definition, AC1[m] has poly size, log depth, with unbounded fan-in MODm, V and Λ gates.

Theorem: The fan-in of the V and Λ gates can be reduced to log n, with no loss of computational power.

– In symbols: AC1[m] = log-AC1[m]. Theorem: If m is not a prime power, then the

fan-in can be reduced to 2, with no loss of power. AC1[m] = 2-AC1[m].

…and to ZERO! AC1[m] = 0-AC1[m].

Eric Allender: Dual VP Classes < 20 >

ACC1 and VPACC1 and VP

That is: ACC1 corresponds to uniform families of MODm gates (with no other hardware).

Compare the circuit characterization of ACC1 with the circuit characterization of VP(Fq):

– For any odd prime q, VP(Fq) is the class of languages accepted by uniform families of MODq gates (with no other hardware).

Eric Allender: Dual VP Classes < 21 >

ACC1 and VPACC1 and VP

That is: ACC1 corresponds to uniform families of MODm gates (with no other hardware).

Compare the circuit characterization of ACC1 with the circuit characterization of VP(Fq):

– For any odd prime q, VP(Fq) is the class of languages accepted by uniform families of MODq gates (with no other hardware).

Thus, over finite fields, the difference between VP and ΛP (=ACC1) boils down to the difference between primes and composites.

Eric Allender: Dual VP Classes < 22 >

Degree ReductionDegree Reduction

We have seen examples of fan-in reduction for Boolean circuits (such as AC1[5] = log-AC1[5]).

And we have seen examples of fan-in reduction for arithmetic circuits (such as Uq #AC1(Fq) = Uq ΛP(Fq))…

…which only reduced the fan-in of + gates – and hence did not result in a reduction of the degree of the polynomial represented.

Should we expect any reduction of the fan-in of x gates to be possible?

Eric Allender: Dual VP Classes < 23 >

Degree ReductionDegree Reduction

Should we expect any reduction of the fan-in of x gates to be possible?

Consider the Immerman-Landau conjecture:

– TC1= LDet(Q)

– Equivalently: # AC1(Fpn

) = LDet(Q) = LVP(Q) = LVP(Fpn)

[Buhrman et al] argued that it would be unlikely for a high-degree arithmetic class to coincide with a polynomial-degree arithmetic class.

Eric Allender: Dual VP Classes < 24 >

Degree ReductionDegree Reduction

We present examples where degree reduction is possible.

Define #WSAC1 to be circuits with a “weak” form of the semiunbounded fan-in restriction: poly-size, log depth circuits with unbounded fan-in + gates, and logarithmic-fan-in x gates.

Theorem: For any prime q, AC1[q] = #WSAC1(Fq).

Corollary: #AC1(F2) = #WSAC1(F2).

Eric Allender: Dual VP Classes < 25 >

Degree ReductionDegree Reduction

Consider #AC1(F2) = #WSAC1(F2).

Polynomials in #AC1(F2) have degree nO(log n).

Polynomials in #WSAC1(F2) have degree nO(log log n).

This is proved using off-the-shelf techniques (isolation lemma, derandomization using walks on expanders). We see no reason why degree nO(log log n) should be optimal.

If it can be reduced to nO(1), then #AC1(F2) = VP(F2).

Eric Allender: Dual VP Classes < 26 >

Degree ReductionDegree Reduction

Consider #AC1(F2) = #WSAC1(F2).

Polynomials in #AC1(F2) have degree nO(log n).

Polynomials in #WSAC1(F2) have degree nO(log log n).

This is proved using off-the-shelf techniques (isolation lemma, derandomization using walks on expanders). We see no reason why degree nO(log log n) should be optimal.

If it can be reduced to nO(1), then #AC1(F2) = VP(F2) = ΛP(F3).

Eric Allender: Dual VP Classes < 27 >

Open QuestionsOpen Questions

We believe that the arguments presented against the Immerman-Landau conjecture – which are based on degree-reduction being unlikely – are weakened by examples of degree-reduction. Can one improve the degree reduction?

Can the connection between ACC1 and VP be strengthened?

Is Um LVP(Zm) equal to Um AC1[m] (= ACC1)?

This would imply AC1 is contained in LVP[Zm] for some m.

Eric Allender: Dual VP Classes < 28 >

Open QuestionsOpen Questions

We believe that the arguments presented against the Immerman-Landau conjecture – which are based on degree-reduction being unlikely – are weakened by examples of degree-reduction. Can one improve the degree reduction?

Can the connection between ACC1 and VP be strengthened?

Is Um LVP(Zm) equal to Um AC1[m] (= ACC1)?

This would imply AC1 is contained in LVP[Zm] for some m. (SAC1 is there, nonuniformly.)

Eric Allender: Dual VP Classes < 29 >

Thank you!Thank you!

Eric Allender: Dual VP Classes < 30 >

#P

NP

P

TC1

ACC1

AC1

SAC1=LogCFL

NL

L

#NC1

NC1

TC0

ACC0

AC0