final presentation encryption/decryption on embedded system supervisor: ina rivkin students: chen...

Final presentation

Encryption/Decryption on embedded system

Supervisor: Ina Rivkinstudents: Chen Ponchek

Liel Shoshan

Winter 2013Part A

motivation• Now days, there are many portable storage systems

with large memories which contains valuable data (such as disk on key, tablets, etc.)

• Therefore there is a concrete need for portable cryptography systems which are suitable for such devices.

• In our project, we will aspire to provide a suitable system which will answer this need.

Project Goalmain goal:

Implementation of data cryptography embedded

system using AES algorithm and finding the suitable

architecture for portable system.

Project Specifications• Implementing on a Zync SoPC by Xilinx.

• Suitable for portable systems (Disk-on-Key, tablets, etc.) - low power system.

• Transparent system (while storing/loading files) - The cryptography system won’t

create traffic bottle necks.

• Finding the best architecture – according to the requirements above:

• Profiling AES algorithm.

• Finding the balance between using the ARM processor and using the FPGA

(the hardware accelerator needs more power).

AES algorithm• Advanced Encryption Standard, also known as “Rijndael”, is a block cipher.

• The cipher is iterative, quick and comfortable to implement both by software

and hardware, and it doesn’t have high memory requirements.

• Most of the AES calculations are made through 10 rounds.

• In each state the data block is described as a 2D, 4X4 array of bytes.

• In each round a “Round Key” is created by the key-expansion process.

• Each round consists of 4 steps:

1. SubBytes

2. ShiftRows

3. MixColumns

4. AddRoundKey

PS

UART

DDR

System Block diagram

RS232

PL

ZEDBOARD

Encrypted data

Decrypted data

Zynq

BRAM

Zedboard Block Diagram

PS

UARTRS232

PL

ZEDBOARD

Encrypted data

Decrypted data Zynq

AES in software

System Block Diagramproject part A

Implementation of AES algorithm on ARM and code optimization.

DDR

BRAM

Software Engineering

• Each step is implemented as a separate function.

• Each function is independent of the other functions.

• The program can encrypt and decrypt the data.

Software Engineering

• The input data will be entered by the user via PuTTY terminal.

• The program’s output is the data after encryption and the encrypted data after decryption.

Encryption Process

Development stagesXPS/EDK-Configuring the ARM system:

Creation of the ARM processor interface to the RS-232 UART.

Addition of the Bram and Bram Controller IP and connection to the AXI Interconnect.

Development stagesPlanAhead

Creation of the Top level entity in VHDL code. Generation of the Bitstream. Exporting hardware to SDK.

Development stagesSDK - Generating the software platform project:• Creating Board Support package (BSP).• Selection of memory – DDR vs. Bram.

Test in Hardware:• Downloading the application to the ARM processor.• Running and profiling the application.

ProfilingBram vs. DDR

E n c r y p ti o n a n d d e c r y p ti o n o f 1 0 x 1 6 B y t e s

2.754 ms

111.54 ms

Software optimization #1

• The MixColumns and InvMixColumns functions takes around 65%-70% of the whole process execution time.

• Improving them will significantly reduce the delay time.

Software optimization #1

• We will implement the MixColumns function using LUTs instead of arithmetic commands and if/else statements.

• Should speed up the calculations.

MixColumns initial implementation

MixColumns improved implementation

2.626 ms

88.06 ms

ProfilingBram vs. DDR

W i t h a n i m p r o v e d M i x C o l u m n s i m p l e m e n t a ti o n

Software optimization #1

Bram : • The total execution time decreased from

111.5 msec to 88 msec.• Decreasing in 21%.

DDR : • The total execution time decreased from

2.754 msec to 2.626 msec.• Decreasing in 5%.

Software optimization #2

• We will implement the MixColumns and the InvMixColumns functions using LUTs and without using for loops.

• Should speed up even more the calculations.

MixColumns optimized implementation

InvMixColumns optimized implementation

With an optimized MixColumns and MixColumns implementation

1.145 ms47.427 ms

ProfilingBram vs. DDR

W i t h a n i m p r o v e d M i x C o l u m n s i m p l e m e n t a ti o n

Software optimization #2

Bram : • The total execution time decreased from

111.5 msec to 47.427 msec.• Decreasing in 57%.

DDR : • The total execution time decreased from

2.754 msec to 1.145 msec.• Decreasing in 58%.

Hardware optimization

The ARM processor clock:• At first, we used the default clock rate, which

was 160MHz.• We will now set the clock rate to 225MHz (the

maximum clock rate).

W i t h h i g h e r c l o c k r a t e ( 1 6 0 M H z 2 2 5 M H z )

0.819 ms34.798 ms

ProfilingBram vs. DDR

Bram : • The total execution time decreased from

111.5 msec to 34.8 msec.• Decreasing in 69%.

DDR : • The total execution time decreased from

2.754 msec to 0.82 msec.• Decreasing in 70%.

Hardware optimization

basic improved optimized higher clk rate0

20

40

60

80

100

120

0

0.5

1

1.5

2

2.5

3

111.54

88.06

47.427

34.798

2.754

2.626

1.145

0.819

BRAMDDR

mse

cOptimizations

E x e c u ti o n ’s ti m e i m p r o v e m e n t

OptimizationsE x e c u ti o n ’s s p e e d i m p r o v e m e n t

basic improved optimized higher clk rate0.00

0.50

1.00

1.50

2.00

2.50

3.00

3.50

4.00

4.50

5.00

0.00

50.00

100.00

150.00

200.00

250.00

1.43

1.82

3.37

4.60

58.10 60.93

139.74

195.36

BRAMDDRKB

/sec

Execution’s speed improvement• Every optimization that we have made has

decreased the total time and improved the speed.

• The most significant improve was attributed by the 2nd SW optimization.

• Both DDR and Bram speeds wereeventually increased by 3 times and more.

Bram vs. DDR• In every optimization : running the application

from BRAM was significantly slower then running from DDR.

• This is due to:– DDR has it own dedicated Bus.– The DDR clock rate is 550 MHZ, when BRAM clock

rate is 160 MHZ.– DDR works on both rising and falling edge.

Transmission rate

• The typical maximum data rate in USB is 1.5 MB/s (The typical rates are around 0.5 MB/s.)

• The encryption rate we were able to achieve at the end is 323 KB/s 1.5 times slower.

• Conclusion: An hardware accelerator is needed.

Project Specifications

• Implementing on a Zync SoPC by Xilinx.

• Suitable for portable systems (Disk-on-Key, tablets, etc.) - low power

system.

• Finding the best architecture – according to the requirements

above:

Profiling AES algorithm.

Demonstration