by: daniel barskynatalie pistunovich supervisors: rolf hilgendorfinna rivkin
TRANSCRIPT
Sub-Nyquist System Optimization
By: Daniel Barsky Natalie PistunovichSupervisors: Rolf Hilgendorf Inna Rivkin
Final Presentation
Reminder – Pre-simulation analysis
Memory
Controller
.
.
.
A†
CTF
Expander DSP
Support Change Detector
Q-FrameOMP
FPGA 1 FPGA 2 FPGA 3
73%
98% 75%
Reminder – Pre-simulation analysis (Cont.)
Timeline
New IncomingSample
Expander Delay
Q-Frame Delay
3.5usec
OMP Delay
11usec
Pseudo-Inverse Delay
5usec
Reconstruction Delay
Sample readyFor reconstruction
Reconstruction Delay: Expander - ~15 cycles (@120MHz) CTF – ~1450 cycles (@120 MHz) DSP - ~500 cycles (@120 MHz)
Test Environment Overview - Matlab
txt
Filter Coefficients
txt
A Matrix
txt
Beta
General Datatxt
Beta
txt
Filter Coefficients
txt
A Matrix
Test Environment Overview – Matlab (Cont.)
txt
Input Data
txt
N
txt
N_frame
txt
Threshold
txt
Support
txt
Input Data
txt
N
txt
N_frame
txt
Threshold
txt
Support
Dataset_1 Dataset_2 Dataset_3
Test Environment Overview – Matlab (Cont.)
VHDL
Matlab_pack
...\General Data…\Dataset_1…\Dataset_2…\Dataset_3
VHDL
Matlab_pack
Test Environment Overview – Modelsim (Cont.)
CTF
Expander
Su
pp
lyIn
pu
tS
am
ple
s
Input Samples
N
N_frame
Threshold DSPSCD
Samples FIFO
Filter Coefficient
FIFOFilter Coefficients
Expanded Samples
RecalculateSupport
Support
DelayedSamples
A Matri
xβ
A Matri
xRecord
Reconstructed
Data
Simulation Controller
Filter Coefficients FIFO ModuleReads the filter coefficients from
a fileUpon receiving a REQ, outputs a
line of 7 coefficients and an ACK signal
Test Environment Overview - Modelsim
CTF
Expander
Su
pp
lyIn
pu
tS
am
ple
s
Input Samples
N
N_frame
Threshold DSPSCD
Samples FIFO
Filter Coefficient
FIFOFilter Coefficients
Expanded Samples
RecalculateSupport
Support
DelayedSamples
A Matri
xβ
A Matri
xRecord
Reconstructed
Data
Simulation Controller
Supply Samples Module
Reads from the files generated by Matlab: The input samples The N, N_frame, Threshold values The correct support
Upon receiving a positive pulse on the OE signal, starts generating the input samples
Supply Samples Module (Cont.)
FSM:
IdleOpens the first Dataset files (input samples,Nframe , threshold) and waits for an OE command
Read next datas
et
Done
OEReads samples from the relevantdataset and feeds them to the expander
Dataset i<3doneWhen the dataset samples are done,
reads the samples and data for the nextdataset Dataset 3 doneWhen all samples are done, do nothing
Test Environment Overview – Modelsim (Cont.)
CTF
Expander
Su
pp
lyIn
pu
tS
am
ple
s
Input Samples
N
N_frame
Threshold DSPSCD
Samples FIFO
Filter Coefficient
FIFOFilter Coefficients
Expanded Samples
RecalculateSupport
Support
DelayedSamples
A Matri
xβ
A Matri
xRecord
Reconstructed
Data
Simulation Controller
A matrix, β coefficient modulesRead the appropriate data fromA fileUpon receiving an address,
outputThe appropriate data
Test Environment Overview – Modelsim (Cont.)
CTF
Expander
Su
pp
lyIn
pu
tS
am
ple
s
Input Samples
N
N_frame
Threshold DSPSCD
Samples FIFO
Filter Coefficient
FIFOFilter Coefficients
Expanded Samples
RecalculateSupport
Support
DelayedSamples
A Matri
xβ
A Matri
xRecord
Reconstructed
Data
Simulation Controller
Samples FIFO module
Upon receiving a WE, stores incoming samples from the expander
Upon receiving OE, outputs stored samples to the DSP for reconstruction
Maximum FIFO length – defined by a Generic
Actual FIFO length – 4294 samples (@20MHz)
Test Environment Overview – Modelsim (Cont.)
CTF
Expander
Su
pp
lyIn
pu
tS
am
ple
s
Input Samples
N
N_frame
Threshold DSPSCD
Samples FIFO
Filter Coefficient
FIFOFilter Coefficients
Expanded Samples
RecalculateSupport
Support
DelayedSamples
A Matri
xβ
A Matri
xRecord
Reconstructed
Data
Simulation Controller
Simulation Controller
The main part of the testbenchReceives all status signals from
all blocks, and sends control signalsto all blocks
Consists of 3 FSMs – Expander FSM, CTF FSM, DSP FSM
Simulation Controller (Cont.)
Expander FSM:
InitInitializes the expander and starts theprocess of loading the filter coefficients
Wait Read
y
Phase
Delay
Ready
InputSampl
es
Done
Counter
Samples Done
Waits until all coefficients have been loadedand the Expander is ready
Raises the “Data Valid” signal while supplyingzero samples (to generate phase shift)Raises the “Data Valid” signal and inputsreal samples to the ExpanderOnce the samples are finished, pauses theExpander
Simulation Controller (Cont.)
CTF FSM:
InitInitializes the CTF
Wait Read
yIdle
Ready
Wait DSP
Calculate
Support
SupportValid
DSP SupportACK
Support
Change
Waits until the CTF is readyInitiates the CTF support calculation andwaits for a “Support Valid” signalWaits until DSP acknowledges the newsupportWaits until the SCD indicates a changein the support, upon which time it willinitiate a recalculation of the support
Simulation Controller (Cont.)
DSP FSM:Wait
Support
DSP is ready and waiting for the CTF tocalculate a new support
Pseudo
Inverse
Support Change
Reconst-
ruction
DSP is calculating a new PseudoinversematrixPseudoinverse calculation done, samplesfrom the Samples FIFO are used for reconstruction
Support Valid
Pseudoinverse Done
SupportUnchanged
0 10 20 30 40 50 60 70 80 90-180
-160
-140
-120
-100
-80
-60
Frequency (MHz)
Pow
er/f
requ
ency
(dB
/Hz)
Spectrum of y1[n] (after expand)
0 10 20 30 40 50 60 70 80 90-180
-160
-140
-120
-100
-80
-60
-40
Frequency (MHz)
Pow
er/f
requ
ency
(dB
/Hz)
Reconstructed sequence #1
0 10 20 30 40 50 60 70 80 90-180
-160
-140
-120
-100
-80
-60
-40
Frequency (MHz)
Pow
er/f
requ
ency
(dB
/Hz)
Reconstructed sequence #2
Reconstruction Example #1 – AM + sine
0 10 20 30 40 50 60 70 80 90-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
Frequency (MHz)
Pow
er/f
requ
ency
(dB
/Hz)
Spectrum of y1[n] (after expand)
0 20 40 60 80-200
-190
-180
-170
-160
-150
-140
-130
-120
-110
-100
Frequency (MHz)
Pow
er/f
requ
ency
(dB
/Hz)
Reconstructed sequence #1
0 20 40 60 80-180
-160
-140
-120
-100
-80
-60
Frequency (MHz)P
ower
/fre
quen
cy (
dB/H
z)
Reconstructed sequence #2
Reconstruction Example #2 – AM + FM
Hardware Utilization
LEs Block RAM bits
DSP Half-Blocks
Previous Analysis (DSP Halfblocks)
Expander 43,856 5Mbit 448
CTF 31,000 6Mbit 604
DSP 62,913 1.2Mbit 752
Avaliable on Stratix III 260
203,520 15Mbit 768
21%
33% 58%
15%
40% 78%
31%
8% 98%
73%98%
75%
(based on synthesis results of the different groups, including arcitecture blocks)
Reconstruction Latency
Expander
CTF
DSP
15 Cycles
1087 Cycles
29,823 Cycles
Timeline
New IncomingSample
Expander Delay
CTF Delay
9.06usec
DSP Delay
248.5usec
Sample readyFor reconstruction
Timeline
New IncomingSample
Expander Delay CTF Delay
14.5usec
DSP Delay
5usec
Sample readyFor reconstruction
Previous Evaluation:
Further Conclusions
Support calculation is unstable, and extremely sensitive to input phase (relative to the NCO’s phase)
SCD is highly prone to misdetections & false positives!
The system seems to have more trouble with FM signals than with AM/sine
Future Work
Characterize the dependency of the support calculation on the input phase
Use fewer resources at a higher clock frequency at the reconstruction stage - in an attempt to squeeze it in with the Expander
Reimplement Pseudoinverse to share resources with the CTF, to fit them both in the same FPGA
Simulate & integrate implementation
Gantt Chart
Finish Part A Project Report
Characterize CTF dependency on phase(Matlab+Modelsim)
Reimplement reconstruction block
Simulate reconstruction block
Extract MaMu from CTF
Reimplement Pseudoinverse block
Simulate pseudoinverse block
Synthesize blocks
Simulate system with new blocks
Synthesize & Integrate Blocks
Final Part B Presentation
Write Part B Project Book
3/10/2011 3/30/2011 4/19/2011 5/9/2011 5/29/2011 6/18/2011 7/8/2011 7/28/2011 8/17/2011 9/6/2011