Performed by: Gidi Getter,Shir Borenstein

Supervised by: Ina Rivkin

Final Presentation21/07/2008

High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

הטכניון - מכון טכנולוגי לישראל

הפקולטה להנדסת חשמל

Technion - Israel institute of technologydepartment of Electrical Engineering

Space Wire Core for LEON3 System

Project Definition

• Design a Space Wire core for LEON3 system.

• Load Leon3 system with our own IP core to GR-RASTA board.

What is Space Wire?

• Space Wire is a spacecraft communication network. It is coordinated by the European Space Agency (ESA).

• Components are connected through low-cost, low-latency, full-duplex, point-to-point serial links.

• Uses data strobe encoding - differential ended signaling (DS-DE).

• Space Wire utilizes asynchronous communication and allows speeds between 2Mb/s and 400Mb/s.

• The protocol describes routing, flow control and error detection in hardware, with little need for software.

The Protocol

• Consists of Data characters and Control characters.

• Data characters are 10 bits long – 1 parity bit,1 flag bit set to ‘0’ and 8 data bits.

The Protocol

• Control characters are 4 bits long – 1 parity bit,1 flag bit set to ‘1’ and 2 control characters.

• Control codes is built with the ESC character following a FCT character / Data character.

Space Wire Usage

SW

SW Router

Component A

(Computer, Device, etc)

Satellite

Component B

LEON3 System

LEON3 Processor

AMBA AHB Bus

AHBController

JTAG Dbg Link

MemoryController

SERIAL Dbg Link

JTAG RS232

Space Wire Link

LVDS

RAM

SRAM, DRAM etc.

SIGNAL gotFCT : std_logic

S_out

d_out : std_logic

S_out : std_logic

SIGNAL gotNull : std_logic

clk : std_logic

SIGNAL sendFCTs : std_logicSIGNAL sendNchars : std_logic

SIGNAL sendTimeCodes : std_logicSIGNAL sendNulls : std_logic

SIGNAL rec_rst : std_logic

SIGNAL tr_rst : std_logic

SIGNAL gotNChar : std_logic

SIGNAL GotEOP : std_logicSIGNAL GotEEP : std_logic

SIGNAL empty : std_logic

U_1S_out

send

Nch

ars

send

Tim

eCod

es

gotF

CT

_ac

kgo

tFC

T_r

eq

sent

FC

T_a

ck

sent

FC

T_r

eq

SIGNAL wr_data_count : std_logic_VECTOR(5 downto 0)

SIGNAL gotFCT_ack : std_logic

my_project_libController

rst : std_logic

SIGNAL gotFCT_req : std_logic

SIGNAL control_flags_out : std_logic_vector(1 DOWNTO 0)

SIGNAL time_out : std_logic_vector(5 DOWNTO 0)

SIGNAL control_flags_in : std_logic_vector(1 DOWNTO 0)

SIGNAL time_in : std_logic_vector(5 DOWNTO 0)

SIGNAL tick_out : std_logicSIGNAL tick_in : std_logic

SIGNAL wr_en_tf : std_logic

SIGNAL rd_en_rf : std_logic

SIGNAL wr_clk_rf : std_logic

SIGNAL rd_en_tf : std_logic

SIGNAL rd_clk_tf : std_logic

SIGNAL Link_Disabled : std_logic

SIGNAL has_places : std_logic

SIGNAL sentFCT_req : std_logicSIGNAL sentFCT_ack : std_logic

SIGNAL CreditError : std_logic

SIGNAL tr_fifo_dout : std_logic_VECTOR(8 downto 0)SIGNAL tr_fifo_din : std_logic_VECTOR(8 DOWNTO 0)

SIGNAL RxError : std_logic

fifo_9bit

rd_clk

rd_en

rst

dout : (8:0)

empty

rd_data_count : (5:0)

SIGNAL rec_fifo_din : std_logic_vector( 8 DOWNTO 0 )

SIGNAL wr_en_rf : std_logic

SIGNAL rd_data_count : std_logic_VECTOR(5 downto 0)

d_in : std_logic

S_in : std_logic

SIGNAL rec_fifo_dout : std_logic_VECTOR(7 downto 0)

wr_clk

wr_en

SIGNAL got_EEP : std_logicSIGNAL got_EOP : std_logic

ahbo : std_logic --AHB_slv_out_type;

ahbi : std_logic --AHB_slv_in_type;

SIGNAL tick_out_req : std_logicSIGNAL tick_out_ack : std_logic

rd_en_tf

tr_

fifo_

din

: (8:

0)

wr_

data

_co

unt

: (5:

0)

cont

rol_

flags

_in

has_

pla

ces

Package ListLIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;USE IEEE.std_logic_unsigned.all;USE ieee.numeric_std.all;

DeclarationsPorts:

Diagram Signals:

d_outmy_project_libTransmitter

clk

D_outfifo_empty

tick

_in

time

_in

cont

rol_

flags

_in

has_

pla

ces

tr_fifo_dout

rst_dcm

tr_fifo_dout : (8:0)

empty

rst

my_project_lib

din : (8:0)

wr_en

rst

my_project_lib

control_flags_out : (1:0)

Cre

ditE

rro

r

gotE

EP

gotE

OP

gotF

CT

gotF

CT

_ac

kgo

tFC

T_r

eq

gotN

Cha

r

gotN

ull

gotT

ime

Cod

e

rst

Rx

Err

or

sent

FC

T_a

ck

sent

FC

T_r

eq

rec_rst

Cre

ditE

rro

r

sen

dNul

ls

gotN

ull

gotF

CT

Go

tEO

PG

otE

EP

gotF

CT

_ac

kgo

tFC

T_r

eq

sent

FC

T_a

ck

sent

FC

T_r

eq

Rx

Err

or

rstse

ndF

CT

str_clk

rd_en

U_2

gotEEPgotEOP

gotFCT

gotNChar

gotNull

gotTimeCoderec_

rst

sendFCTssendNchars

sendNullssendTimeCodes

tr_r

st

CreditErrorRxError

sendFCTssendNchars

sendTimeCodes

rec_

rst

tr_r

stsendNulls

rd_clk_tftr_rst

gotN

Cha

rtic

k_o

ut

d_in

S_in

RecieverU_0

D_in

S_in

sys_clkclk

din

rec_clk

rec_fifo_din : (8:0)

tick_out_acktick_out_reqtime_out : (5:0)

wr_en_rf

wr_clk_rf

rec_fifo_dinwr_en_rf

tick_out_reqtick_out_ack

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my_project_lib/SW/struct

rd_

clk

got_EEP

rd_e

n_rf

cont

rol_

flag

s_o

ut

time_

out

rec_fifo_dout : (7:0)

rd_data_count : (5:0)got_EEPgot_EOP

clk

rst

Link_Disabled

clk

rst

U_4

wr_

clk

full

wr_data_count : (5:0)

got_EOP

clk

Link_Disabled

clk

clk

clk

rst

my_project_libahbsw_ctrlU_3

add

_cre

dit

clk

cont

rol_

flags

_in

cont

rol_

flag

s_o

ut

d_in

d_o

ut

disable_link

Go

tEE

PG

otE

OP

Go

tTim

e

r_d

ata_

cou

nt

read

_en

rst

Tim

eCod

e

w_

data

_cou

nt

wr_

en

time_

out

ahbi

ahbo

tick_

out_

ack

tick_

out_

req

wr_

en_

tf

time

_in

tick

_in

Title:Path:Edited:

my_project_libReceiveFifoU_5

rd_data_count

dout

rd_en

Project:

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my_project

ahbo

ahbi

hindex = 11 ( integer ) haddr = 16#B00# ( integer ) hmask = 16#fff# ( integer )

Space Wire Core – Top Level

Space Wire Core – Controller

gotFCT

‘1’ Q

ctrl_rst

clk

D Q

ctrl_rst

D Q

ctrl_rst

D

Space Wire Core – Transmitter

Data serialization unit – translate the character into data-strobe logic

values

clk

tick

tr_clk

tick_tr

FCT synchronizer

req

ack

Early data fetch from FIFO

Transmitter control unit – decides which character to transmit and manages FCT

balance

Space Wire Core – Receiver

0 1 0 0 10 00

clk

D

Serial to parallel character decoder

Initialization Null decoder

DCM & reset generator

State controller and timer

State controller and timer

Time code synchronizer

FCT synchronizer

Clock restore

• Leon3 reads data one packet at a time.• All NChars are forwarded from FIFO1 to FIFO2 until

EOP/EEP is detected.• No further data is written into FIFO2 until is the packet

was read by Leon3 and FIFO2 is empty again.

Receiver FIFO

• Handles all requests from processor.• Reads and writes data from FIFOs to transfer between

core and processor.• Add bit for data/EOP.• Updates Status Register.• Informs available room in receive FIFO for FCT handling

by transmitter.

State Machine

StatusRegister

clk

reset

AHB_slave_in

AHB_slave_out

wr_enData

9

rd_enData

8

Tick_out

Time_in

AMBA AHB Controller

Tick_in

Time_out

• The Space Wire core with Leon3 system was checked in logic simulation only.

• The Leon3 system with a custom IP core was loaded into GR-RASTA board.

• Coming up next: Simulation results.

Logic Simulation

Logic Simulation – Transmit

The value of the status register is sent back to the processor.

The processor initiate a read cycle on the bus, to the write status register address.

volatile int *check_status = 0xB0000ABC;free_space = 64 - *check_status;

volatile int *send_addr4 = 0xB0000000;*send_addr4 = *nchar;

Logic Simulation – Transmit

Data is written into transmit FIFO.4 write cycles to transfer 4 nchars.Transmitter reads the nchars from the

FIFO

Transmitter sends the nchars across the linkTransmitter sends the nchars across the link

Logic Simulation – Receive

Receiver detectes arrival of nchar on link.

The nchars are written into FIFO 1.

Data is transferred from FIFO1 to FIFO2 as long as EOP was not recieved

Status register in AHB controller is updated by the number of nchars stored in FIFO2.

Logic Simulation – Receive

Receiver detectes arrival of EOP

A character marking arrival of EOP is written to

reciever FIFO1

FIFO controller reports arrival of EOP to AHB controller. No more nchar will be tranfered to FIFO2.

AHB status register is updated, to report arrival of EOP to processor.

Logic Simulation – Receive

The rest of the computation is done in software

The value of the status register is sent back to the processor.

The processor initiate a read cycle on the bus, to the status register address.

volatile int *check_status = 0xB0100AB0 ;status = *check_status;

Logic Simulation – Receive

The processor requests to read 4 nchars

The AHB controller reads 4 lines from receiver FIFO and collects them

The data is sent back to the processor, 4 nchars in parallel (32 bit data bus)

• LEON3 design configuration.• Add instantiation of the core to leon3mp.vhd (top

module).• Add VHDL file list of the core to Makefile. This will add

the files to simulation and synthesis scripts.• Write C code of the program. Compile using sparc-elf

cross compiler. Create an exec file to run on board, and a memory snapshot for simulation.

• Simulate design using testbench provided by gaisler.• Perform synthesis with synplify, using generated script.• Perform P&R with ISE tool, and load bit file to board.• Load exec file and run program using GRMON.

Configuring LEON3 System

• Add support for UART and DSU.

LEON3 Design Configuration

• Add support for UART and DSU.

LEON3 Design Configuration

• Add support for UART and DSU.

LEON3 Design Configuration

Add IP Core

• Add instantiation of the core to leon3mp.vhd (top module).

Add IP Core

AHB slave index number on the bus

12 MSB bits of slave address space

Number of AHB slaves on the bus.Default is 8, change to 16.

MakefileAdd the VHDL files of the core to “VHDLSYNFILES” parameter

Testbench

Change SDRAM file to the same as SRAM file.

Create scripts for Simulation

• “make scripts” command generates tool-specific compile scripts.

• “make vsim” compiles all VHDL files and testbench for simulation.

• “make xgrlib” – GUI interface for running these commands and more.

Compile C Program for LEON3

Compile C code using sparc-elf cross compiler:

• To create an exec file to run on board:sparc-elf-gcc -O2 -g prog.c -o prog.exe

• To create a memory image for simulation:sparc-elf-objcopy -O srec prog.exe sram.srec

Simulation and Synthesis

• Simulate design with Modelsim: run “make vsim” will compile all the files.

• Run synthesis: “make synplify” will create a project file (leon3mp_synplify.prj) for Synplify.

• These commands can be run from xgrlib GUI.

P&R with ISE

• Can be run directly from synplify after synthesis.

• Constrains file to be used in ISE is provided in the LEON3 package in:

“boards\gr-cpci-xc2v\leon3mp.ucf”

Problems Using GR-CPCI-XC2V

• Bit files can be programmed from PROM or Boundary Scan (JTAG).

• By default, the board is configured to be loaded from PROM at startup.

• To load a new bit file, the system must be reset. If a new bit file is loaded again before reset, the new system will not function.

Problems Using GR-CPCI-XC2V

• To configure the board to be loaded only from JTAG, set jumpers to Boundary Scan Programming (Mode='101').

LEON3 Debug Support Unit

LEON3 Debug Support Unit

RS232 DSU connection for serial connection to PC

JTAG connection for loading and debugging

GRMON

• GRMON is a general debug monitor for the LEON processor.

• Can be used to access all system registers and memory.

• Used for downloading and execution of LEON applications.

• Can access the DSU via RS232, JTAG, PCI, USB and ethernet.

• Can loopback UART in system and print its output on console.

GRMON

Starting GRMON:• With UART loopback via serial: grmon -u• With UART loopback via JTAG: grmon -u -jtagGRMON command-line interface:• Load a program: load <file>• To run a program: run• System information: info sys• Displaying register content: reg• Displaying memory contents: mem <addr>

GRMON

Achievements & Future Development

Project main steps:• Learn and implement Space Wire protocol.• Integrate SW core into LEON3 system.• Operate GR-CPCI-XC2V board with LEON3

system with our own IP core.Future improvements:• Operate the SW core on the board with loopback,

and check compatibility of protocol with SW bridge.

• Integrate SW core as master on AHB bus, implement interrupt and DMA for transactions.