hardware description language - imperial college london 1... · 6. verilog hdl –while you mostly...

WelcometomysecondyearcourseonDigitalElectronics.YouwillfindthattheslidesaresupportedbynotesembeddedwiththePowerpoint presentations.Allmyteachingmaterialsarealsoavailableonthecoursewebpage:www.ee.ic.ac.uk/pcheung/teaching/ee2_digital/.TheQRcodehereprovidesashortcuttogotothecoursewebpage.Iwillbeupdatingthenotes,thelaboratoryinstructionsandtutorialproblemsheetseachweekafterthelectures.AllmylectureswillberecordedwithPanopto.Therecordingswillalsobeuploadassoonaspossibleafterthelectures.

Thecourseconsistsofabout16hourslecturesinterleavedwith6problemsolvingclasses.ThesewillbeheldonTuesday4pmto6pmandThursday12noonto1pmstartingfrom10th ofOctober.

ThiscoursefollowsonfromthefirstyearDigitalElectronicsIcourse.Unlikethefirstyearcoursewhereallgatesandflip-flopsareassumedtoexhibitidealbehaviour,thiscoursewillteachyouaboutreal-lifedigitalcircuits.

Digitalcircuitsareubiquitous.Forexample,therearemoreelectronicmodulesincarsthesedaysthanmechanicalsystems.Amobilephonehasmanytimesmoretransistorsthanhumanaliveonearth,andmostofthesetransistoraredigital,i.e.workingason-offswitches.ThereforethissecondyeardigitalelectronicscourseisfundamentaltoanyEEEorEIEeducation.

Itisimportantforyoutoknowatthisstagewhatyouareexpectedtolearn(i.e.thelearningoutcomes)fromthismodule.LearningoutcomesspecifyWHATyoushouldbeabletodoasaresultoftakingthismodule.Letmegothroughthelistedoutcomesinsomedetails:1. Understandsynchronousdigitalsystems– ifyouaregivenacircuitwithgatesandflip-flops,youshouldbeabletopredicthowitbehaves.Forexample,youshouldbeabletodrawthetimingdiagramsforoutputsignalsgiventheinputstimuli,orwritedownthesequenceofstatesthatthecircuitmustgothrough.2. DesigncircuitstomeetspecificationInrealcircuits,outputsresponsetochangesininputsaftersomedelay.Inorderforadigitalcircuittoworkasintended,suchdelaymustbetakenintoaccount,andyouasadesignengineermustbesurethattherearenotimingviolations(i.e.circuitdelayscausingthecircuittofail).3. A/DandD/Aconversions– thephysicalworldisgenerallyanalogueinnatureandisnotjust‘1’sand‘0’s.However,electronicsystemsaremostlydigital.AnaloguetoDigital(ADC)andDigitaltoAnalogue(DAC)conversionprovidesthelinkbetweentheanaloguephysicalworldtothedigitalelectronicsworld.YouneedtounderstandHOWanaloguesignalsareconvertedtodigital,andhowtointerpretthedatasheetofsuchcomponents.4. FiniteStateMachines– Designingdigitalcircuitsinvolveunderstandingofvariousfields,andoneofthefieldofstudyisknownasFiniteStateMachine(FSM).Thisisasystematicwaysofthinkinghowadigitalsystemgoesthroughdifferentstates,andasaresult,controltheoperationofadigitalsub-system.5. FieldProgrammableGateArrays– FPGAsisoneoftheprimarytechnologyforimplementingdigitalcircuitsnowadays.Thishasreplacedmostoftheimplementationsin“discretelogic” (suchas16-pinpackagedTTLorCMOSgates).IthasalsoreplacedmanyApplicationSpecificIntegratedCircuits(ASICs)thattheindustryusedtodesign.FPGAsprovetobemuchlower-riskandmusteasiertodesignascomparedtootherapproaches.ThereforethiscoursewillbebasedaroundtheuseofFPGAs.(tocontinue…..)

6. VerilogHDL– Whileyoumostlyuseschematicdiagramstodescribeyourdigitaldesignsinyourfirstyear,youwillABANDONthisinfavour ofacomputerlanguagetospecifyanddesignyourdigitalcircuits.Youmayfindthisoddinitiallybecausediagramsaregenerallymoreintuitivethanacomputerlanguage.However,usingaHardwareDescriptionLanguage(HDLasitiscalled),andinourcase,usingVerilog,isthewaythatmostmoderndigitalsystemsarespecifiedanddesigned.Nomatterwhetheryoulikeprogrammingornot,asaelectronicengineer,youwillhavenochoicebuttolearnsuchalanguage.

ThiscoursewillbeassessedthroughanexaminationpaperinJune2017.TherewillalsobeanassociatedE2LaboratoryExperiment– VERI.

TheLaboratoryExperimentisEXTREMELYIMPORTANTinhelpingyoutolearnthissubject.ItisintendedtoteachyouhowtodesigndigitalcircuitsusingVerilogHDLtargetingimplementationsonFPGAs.TheLabsessionswillrunforFOURweeksstartingonthe13thofNovember,andassessmentforthisexperimentwilltakeplaceinthelastweekofterm(starting11thofDecember).Youmayalsoborrowtheexperimentboard(DE1-SOC)touseathomeandatyourleisure,oneweekatatime.Therewillbearoundonesuchboardforeveryfourstudentstoshare.

Therearethreerecommendedtextbook“FundamentalofDigitalLogicwithVerilogDesign3/e” byStephenBrownandZvonko Vranesic.Unfortunatelythisbookisinshortsupplyandisextremelyexpensivetobuynew.Youmaybeabletopickupasecondhandcopyontheinternet.AnotherpossiblebookbutlessrelevantisbyDallyandHarting.WhileitisNOTnecessarytoownatextbookformycoursebecauseIdonotfollowaparticulartextbookinmylecturesorinthelab,IwouldrecommendyoutogetholdofasecondhandcopyoraneBookindigitalasareference.Thethirdbook,alsonotcompulsory,is“DigitalDesign(Verilog)” andisveryVerilogspecific.ItisagoodbookifyouwanttolearnVerilogwell.Againitisnotcompulsory.

ThepracticalaspectsofthiscoursemoduleisbasedaroundaFPGAboard,theDE1-SoC.Hereisanoverallblockdiagramoftheboard.Don’tworryaboutthedetailsfornow.IwillbeexplainingtoyouthevariousbitsoftheboardlaterwhenyouareabouttostarttheVERIexperimentintheLabinmid-November.

ThereshouldoneDE1boardforeveryfourstudentstoborrowanduseathome.Thebasiclendingdurationisoneweek.YoucanrenewyourborrowingperiodbeyondoneweekiftherearefreeonesintheStores.

Toborrowaboard,bringyourIDCardtoLevel1store,andyoucancheckoutaboardtotakeaway.Butyoumustreturnitattheendoftheloanperiod.ThisboardhaseverythingyouneedtodotheexperimentandMORE.ItconsistsofaCycloneVFPGA(whichIwillexplaininmoredetailsinalaterlecture).Ithasvariousinputandoutputdevices.Thisisaverypowerfulboardanditcontainslotsofadditionalhardwareresourcesthatgobeyondthescopeofthismoduleandtheexperiment.Youareencouragedtoexploreit,particularlyifyouareanEIEstudent(andthereforehavealreadyusedFPGAsinyourfirstyearSummerTermProject).

Thisisthecurrentlectureplanforthecourse.Detailsmaychangeasweprogressthroughtheterm.Therewillbearound16lectures(slightlyhigherthanthenominal15lecturepermoduleinthesecondyear).

Iwillcoveranumberoftopicsthatformthebasiccourseindigitalelectronics.Bytheendofthecourse,youshouldbeabletoindependentlydesigndigitalcircuitsusingFPGAs.TherewillalsobeacoupleoflecturesonhowtointerfacedigitalsystemswiththeanaloguesystemviaD-to-AandA-to-Dconverters.

IwillbelinkingmylecturestotheLabExperimentwhereverpossible.Todowellonthiscourse,youreallyneedtotaketheLabseriously!

Thislectureisjustpartlyarevisionlecture,andIalsowanttointroduceyoutoalternativenotationsusedbothinthenotesandinsometextbooks.ThisfollowstheIEEEstandardfordigitalschematics.

Insteadofusingcurvesforgates,onecoulduserectangularblocksandasymboltodenotethelogicfunction.Inversioncouldbeontheinputoroutputterminal.Insteadofacircle,wecoulduseasmalltriangleasshownhere.

IEEEpublishesthestandards,andthereisanexcellenttutorialonthisdigitalcircuitnotationspublishedbyTexasInstrument(seethecoursewebpage).Youdon’treallyneedtospendmucheffortonthis– justneedtolearnthebasicssothatyoucanunderstandthemeaningofthesymbolsandthelabelsusedforsignals.

Inthefirstyear,youlearnedaboutthedifferentwaysofdescribingorspecifyingadigitalcircuit.

1. Schematicdiagramswithgates– thismethodisthefirstthingyoulearnedanditiseasytounderstand.However,aswillbeseeninLecture3,thisisnotnecessarilythebestwaytospecifyalargedigitalsystem.

2. Booleanequations– thisprovidesaformalwaytoexpresslogicalrelationshipsbetweenBooleanvariables.Usefulwhendesigningonpaper,butlessusefulinpractice.Inparticular,werarelyuseBooleanalgebratoperformlogicsimplificationinreal-life!

3. TruthTables– thisisauniversalwaytodescribethebehaviourofacircuitandwecontinuetousethisindatasheetsoreveninactualdesigns.

4. Timingdiagrams– thisisausefulwaytoexplainbehaviourofsequentialcircuitsandisusedindatasheets.However,notthatusefulasamethodtospecifyacircuitinaCADsystem.

5. HardwareDescriptionLanguages(HDLs)– thisisanewmethodyoulearnthisyear(exceptEIEstudentswhohavealreadyencounteredthisintheirgroupproject).Thisiswhatwewillbeusingtospecifyanddesigndigitalhardwarefromnowon.Forthiscourse,wewillbeusingVerilogHDL,whichisonethatisveryclosedtotheClanguage.ItisalsousedextensivelyfordesigningintegratedcircuitssuchasASICsandothertypeofchips.AnotherpopularHDLisVHDL.IpersonallyfindVHDLtoowordy(verbose).Finally,therearenowemerginghigherlevellanguagessuchasOpenCL,whichisattemptingtomakehardwaredesignmorelikeprogrammingacomputer.Thistopicislefttolateryears.

Youhavealsolearnedaboutthevariousbuildingblocksfordigitalelectronics.1. Primitivegates– WehavethebasicAND,OR,NAND,NOR,XORandXNORgates.2. MultiplexersMUXs– Thesearereallyusefulcomponent.Shownhereisa2-to-1MUXwithtwodatainputsandoneselectinput.Theoutputisoneortheotherdependingontheselectinput(sel).Weoftenputanumberofthesetogethertoprovidemultiplexingfunctiontoamult-bitdataword(asshownherewithtwo3-bitnumbers).3. Arithmeticcircuits– Commonlyfoundareaddersandmultipliers.Subtractor canbebuiltfromanadderifweuse2’scomplementrepresentationofsignedintegers.4. Encoders/Decoders– Thesetwoarerelated.Encoding isalogicmodulethatreduces(encodes)alargenumberofbitsandproducesfeweroutputbits.Decoders aretheopposite.Shownhereisa7-segmentdisplaydecoder,where4inputbitsaredecodedinto7logicsignalstodrivethesevensegmentsofthedisplay.Theencoder hereisknownasapriorityencoder.Itproducesa3-bitoutputshowingwherethefirst‘1’ isencountersfromthemost-significantbitD7totheleastsignificantbitD0.5. Flipflops andRegisters– Thesearethebuildingblocksforallsequentialcircuits.Aswillbeseenlater,wereallyonlyuseonetypeofflipflop – theD-FF.Theseareallimportantcomponentsthatalldigitalcircuitdesignersneedtobefamiliarwith.However,nowadays,werarelydesignlargedigitalsystemsatsuchlowlevels.Insteadwegenerallytrytoexpressthesebuildingblocksinamoreabstractmannerinahardwaredescriptionlanguage(aswewillseeinlaterlectures).Inadditiontothesebasicblocks,wealsohavememorydevicesandmicroprocessors.Thesearetopicsthatwewillcovertowardstheendofthismodule.

Alldigitalcircuitsexhibitpropagationdelay.Hereitshowsthedelaytablefora“discretelogic” CMOSNANDgate.Thedelaycouldbeintheregionofnanoseconds.However,withtheFPGAchipsweuseforthismodule,theinternal“gate”propagationdelayisapproximately100ps,whichismuchfasterthandiscretelogic.Ascanbeseenlater,the“gate” insidetheFPGAisalsomuchmorecomplexthanasimpleNANDgate.

Alsonotethatpropagationdelaydependsonthe“cause” (inputrisingorfalling,andontheslopeoftheedge)andthe“effect” (outputrisingorfalling).Delayalsodependsonwhatareconnectedtotheoutput(i.e.theloading).Ascanbeseenintheexamplehere,therisingedgeAtofallingedgeXdelayislowerthanthatofAfallingtoXrising.

NotethatIuseanarrowtoindicatethecause(thebluntend)andtheeffect(thepointedend)inatimingdiagram.

Youlearnedaboutvarioustypesofflipflops(FFs)inthefirstyear.Infact,allyouneedistheD-FF.WithaD-FF,youcanconstructcircuitstobehavelikevarioustypesofflipflops:Toggle(T-FF),set-reset(SR-FF)oraJK-FF.

Thereforeinthiscourse,wewillONLYuseD-FFforeverything.Thisisinfactwhathappensinpracticaldesigns.

WeusetheIEEEstandardsforthesymbolhere.Cmeanclockinput,thenumber1isanumericallabel(asclock1).Disfordatainput,and1Dmeansthisinputiscontrolledbyinput1.Qistheflipflopoutput.

Timinganddelayparametersforflipflopisdifferentfromthatwithgates.ShownhereisaD-FFthatresponsestoarisingedgeontheclocksignal.AD-FFislikeacamera,takinga“picture” fromthescene(inputisD).TheclockinputC1islikethetriggeronthecamera– whenpresseditsamplestheinputandtakeapicture.The“cause” hereistherisingedgeoftheCLOCKandthe“effect” istheQoutputsamplingtheDinput,andkeepthevalueuntilthenextrisingedgeoftheclock.

ThedelayhereisfromCLOCKrisingedgetoQoutputchanging.However,fortheD-FFtoworkproperly,therearetwoothertimingparameterswhichareimportant:thesetuptimeandtheholdtime.Iwillbetalkingabouttheseinalaterlecture.

HereisanexampleofaD-FFusedinaripplecounter.

Q0valueisfirstinverted(representedbythetriangle)andthenusedasDinputonthenextclockcycle.TheflipflopistriggeredontheFALLINGedgeofCLOCK.ThereforetheQoutput“TOGGLES” oneachactiveedgeoftheclock(i.e.fallingedge).Q0isthereforechangingathalftherateofCLOCK,hencethisflipflopactsasadivide-by-2circuit.

TheQ0signalisnowusedasclockinputtothenextD-FF.HenceQ1istogglingathalfthefrequencyofQ0.Thecircuitiseffectivelyabinarycounter.

Thisisasimplefinitestatemachine(FSM)becauseithas8stateswhichcyclesthroughinasequence.FSMwillbecoveredinsomelaterlecturesindetailsanditisaveryimportanttopicindigitaldesigns.

WethenusetheQ0outputastheclockinputthenextstageetc.Notethatbecausethe2nd stageonlystartstoworkoncethefirststageiscompleted,thepropagationofeffects“ripples” throughthecircuit– hencewecallthisa“ripplecounter”.

Thiscounterisalsoknownasanasynchronoussequentialcircuit.Itis“asynchronous” becausetheoutputsignalsareNOTsynchronisedtoasingleclocksignal(sincetherearemanyclocksignals),and“sequential” becauseitscurrentoutputvalue(orstate)dependsonpreviousoutputvaluesinthesequence.

Theripplecounterispotentiallyslow.Thedelaybetweentheactiveedgeoftheclockandthecounteroutputgivingthecorrectvalueisdependentonthenumberofflipflops inthecircuitandthereforethesizeofthecounter(i.e.howmanystages).

Afarbetterapproachistousetheflipflops TOGETHERasagroup,andclockthemusingTHESAMECLOCKsignalasshownhere.TheLogicBlockisacombinatorialcircuitwhichcomputesthenextDvalueD2:0fromthecurrentQvalueQ2:0.(DhasthreebitsD0,D1andD2.WeusethenotationD2:0torepresentthis.)TherelationshipbetweenDandQissimple:D2:0=Q2:0+1.

SincethethreeoutputbitsQ2:0changewithinafractionofananosecondofeachother,thiscircuitis:1)fasterthantheripplecounter;2)the“delay” isconstantinsteadofdependentonthesizeofthecounter.

Thiscircuitisknownasa synchronoussequentialcircuitbecauseitsfunctionissynchronoustoasingleclocksignal.IfyouregardtheQ2:0outputvalueasastatevalue,itfollowsafinitenumberofstatesinadefinedsequence.ThereforeitisalsoaformofFiniteStateMachine.

Notethenotationwiththearrows.

hardware description language - imperial college london 1... · 6. verilog hdl –while you mostly...

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