high speed and rf design considerations - ve2013
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Analog Design Conference 2013 High Speed/RF Design and Layout RFI/EMI Considerations
Zoltan Frasch
Legal Disclaimer
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3
Todays Agenda
Overview
Schematics
PCB Fundamentals
Component Placement and Signal Routing
Power Supply Bypassing
Parasitics
Signal Routing
Examples
Summary
4
Overview
What is high speed? The frequency above which a PCB can significantly degrade circuit
performance. 50MHz and above can be considered high speed.
Why High Speed PCB?
1 f 10 f 100 f 1 f
? To get this waveform Need this bandwidth
5
Overview
PCB layout is one of the final steps in the design process and often not given the attention it deserves. High Speed circuit performance is heavily dependent on board layout.
Today we will address Practical layout guidelines to: Improve the layout process Help ensure expected circuit performance Reduce design time Lower design cost
Schematics
7
Schematics
A good layout starts with good Schematics! Two Basic Functions of Schematic Represent actual circuit connections Generate NetList for layout.
Can it be made more effective? Can it represent functionality more clearly? Others can understand circuit
Can it show signal path? Aid layout Aid troubleshooting, debug Represent functionality
Can it be made more attractive? Can increase perceived value
More effective schematics decrease time to market
8
Schematics - Example A perfectly good schematic.
An alternative.
PCB Fundamentals
PCB Fundamentals
Top Copper Usually a signal layer. Normally a 1.4 mils (0.04 mm) thick (1 oz) copper
plate. Can be thicker.
Laminate Woven glass epoxy. Thickness adjustable from 0.05 mm (1.9 mils) to
suit requirements. Relative permittivity (dielectric constant) between
2.2 and 4.7. Value depends on material and construction.
Plane copper Contiguous copper sheet . Normally 0.7 mils (0.02 mm) thick (1/2 oz). Can
be thicker.
Etched to form signal traces, landing pads, vias. Minimum trace width is 4 mils (0.1 mm). Minimum space requirement between two objects
is 4 mils (0.1 mm). Each trace, pad, via forms a transmission line
with a characteristic impedance Zo. Zo depends on construction, width, height,
distance from plane copper.
A copper shape (trace, pad, via) terminated with its characteristic impedance: Forms a terminated transmission line. Signal integrity is not degraded.
Unterminated copper shapes: Form unterminated transmission lines Have capacitance and/or inductance Degrade signal integrity
Controlled impedance PCB: Manufactured to a specified Zo, applicable to one
specific trace width only.
To optimize PCB signal integrity: Keep all long traces the same width. Terminate all long traces at the load end with a
resistor R=Zo. Can double terminate with additional series
resistor at the source end but not necessary. Double termination reduces drive current requirement
from source at the expense of increased output source voltage requirement.
Keep all unterminated traces as short as possible. Design pads as small as possible.
The basic high speed PCB consists of 3 layers:
PCB Fundamentals - PCB Material selection examples
15
Isola – FR4 types Common general purpose material. High temperature versions for leadfree solder exist Higher permittivity 4.7-4.2. Generates manageable parasitic capacitances Low Cost Reasonable controlled impedance trace consistency. Specified to 1 GHz
Rogers – PTFE types High frequency, high temperature material Low permittivity. 2.2 and up. Can reduce parasitic capacitances Expensive Good impedance consistency. Specified to 10 GHz
Numerous other manufacturers. Some with performance specifications similar to above.
PCB Fundamentals - Component Landing pad design
16
Landing pad size Traditionally oversized by ≈ 30% from
component pad. Can fit soldering iron on it Can allow visual inspection of solder joint Can accommodate component with larger
placement errors.
Increases parasitic capacitance – lowers effective useful frequency Increases chances for solder bridging Requires more board space
Minimum oversizing: 0-5% from
component pad. Retains mechanical strength Contact area between component and PCB
remains the same Reduces parasitic capacitance – retains
higher useful frequency Reduces required board space
Pad shape Traditionally rectangular with sharp corners Rounded corners allow tighter pad-to-trace
spacing. Reduces board size.
This or This
This Or This
PCB Fundamentals - Via Placement
17 *Courtesy of Lee Ritchey
Conventional
Connecting trace
minimized
Via just inside pad
Via Centered in pad
Less Inductance Less capacitance Smaller board space
Increased probability of solder wicking
Fix wicking with tented vias
Component Placement and Signal Routing
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Component Placement and Signal Routing
Just as in real estate location is everything! Input/output and power connections on a board
are typically defined Component placement and Signal routing
require deliberate thought and planning
Component Placement and Signal Routing Use of Plane Layers
Plane Layer Prepreg Copper Signal Trace Solder Mask Signal Current Return Current follows the path of least inductance
Component Placement and Signal Routing Plane layer cutouts
Plane Layer Prepreg Copper Signal Trace Solder Mask Signal Current Return Current Not so good. Minimize Voids in plane layers
Component Placement and Signal Routing Signal Routing
Placement not optimized – Minimize crossings
Connector
Digital ADC
RF
Power Conditioning
Analog Temp
Sensor
Connector
ADC Driver
Placement optimized – Idealized
Component Placement and Signal Routing Return Path Routing
ClockCircuitry
AnalogCircuitry R
esis
tor
DigitalCircuitry
Sensitive Analog Circuitry Disrupted by Digital Supply Noise
Not so good
ID
Voltage Drop
A better way
Sensitive Analog Circuitry Safe from Digital Supply Noise
Use GND and PWR planes to reduce return path R and L.
Use separate AGND and DGND planes to minimize digital coupling into AGND plane.
Compartmentalize functions
Group components associated with functions.
Place functions to coincide with signal path.
Route functions first with input and output along signal path.
Route connections between functions next.
Voltage Drop
More Voltage Drop
ANALOG CIRCUITS
DIGITAL CIRCUITS VD VA
+ +
ID
IA
IA + ID
VIN
GND REF
Component Placement and Signal Routing Packaging and Pinout choices
Packaging plays a large role in high-speed applications
Smaller packages Improved high frequency response Compact layout Lower package parasitics
Low Distortion Pinout (dedicated feedback) Compact layout Streamline signal flow Lower distortion
1 2 3 4
8 7 6 5
FB
INP
INN VOUT
+
-
Low Distortion 1 2 3 4
8 7 6 5
VOUT +
-
Standard
INP
INN
25
Component Placement and Signal Routing CSP and SOIC Package Distortion
HA
RM
ON
IC D
ISTO
RTI
ON
(dB
c)
0.1–120
–100
–110
–80
–90
–60
–70
–50
1 10 50
0451
1-0-
085
SOLID LINES – SECOND HARMONICSDOTTED LINES – THIRD HARMONICS
G = +5VOUT = 2V p-pVS = ±5VRL = 100Ω
FREQUENCY (MHz)
SOIC
CSP
Improvement 10dB at 1MHz 14dB at 10MHz
Example - Component Placement and Signal Routing
Two Inputs. Carbon copies to ensure balance.
Gain and feedback. Carbon copies to ensure symmetry.
Outputs. Carbon copies to ensure symmetry.
Level shifting tapped into signal path. Carbon copies to ensure symmetry.
Auxiliary function.
Critical Signal path as short as possible.
Critical signal paths are carbon copies to maintain balance.
Example – PCB and component Placement
A perfectly good high frequency board
BUT: Excessive number of unnecessary vias Plane layer compromised with a large
cutout Unnecessarily long signal traces Landing pads are too large No internal plane layers
Same circuit with added provisions for an auxiliary function
A better alternative? More components yet smaller board size Vias are minimized Several internal plane layers “Properly” sized Landing pads
Example - Component Placement and Performance
RoHS Tg 170 6 layers HR370 6 layers
RoHS Tg 170 6 layers HR370 6 layers
Two resistors located as shown Move resistors closer to input pins
Example – PCB and Performance
• 6 layer PCB • RoHS Tg 170 & HR370 • No bypass caps • No GND plane on top • No plane cut outs • No “stitching” vias • Smaller size
RoHS Tg 170 6 layers HR370 6 layers FR4 2 layers
RoHS Tg 170 6 layers HR370 6 layers FR4 2 layers
• 2 layer FR4 PCB • 4 bypass caps • Top GND plane segmented • Plane cut outs • “Stitching” vias
Power Supply Bypassing
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Power Supply Bypassing
Bypassing is essential to high speed circuit performance.
It provides low impedance source and return paths to high frequency changes in load current.
Capacitors as close as possible to the supply pins of each IC provide localized bypassing.
Capacitors self-resonate.
Not all capacitors are equal.
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Power Supply Bypassing - Capacitor Model
ESR (Equivalent Series Resistance) Rs
Capacitance XC = 1/2πfC
ESL (Equivalent Series Inductance) XL=2πfL
Effective Impedance
At Series resonance XL=XC Z = R
Power Supply Bypassing - Capacitor Choices
0603 0612
*Courtesy of Lee Ritchey
*
Multiple Parallel Capacitors
1 x 330µF T520, 1 x 1.0µF 0603, 2 x 0.1µF 0603, and 6 x 0.01µF 0603
*Courtesy of Lee Ritchey
*
2 x (1 x 330µF T520, 1 x 1.0µF 0603, 2 x 0.1µF 0603, and 6 x 0.01µF 0603)
1µF 330µF 0.1µF
0.01µF
Example - Bypass Capacitor Placement
C
C
Tantalum
Tantalum
C
C
Tantalum capacitors provide low frequency bypassing for the area
Chip capacitors provide bypassing for higher frequencies for the area.
Chip capacitors on the supply pins provide additional high frequency bypassing for the IC.
Power Supply Bypassing Interplanar Capacitance
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TOP SILK TOP MASK TOP COPPER
2 X 106 0.009” 50Ω with 16 mils TRACE WIDTH
INNER COPPER GND
0.37” SPACER
INNER COPPER VCC 1 X 1080 0.0032” INNER COPPER GND 1 X 1080 0.0032” INNER COPPER VEE 1 X 1080 0.0032” BOTTOM COPPER GND BOTTOM MASK BOTTOM SILK
kA 11.3d C=
0.06
2”
6 LAYER STACKUP
Can replace most or all discrete bypass capacitors.
Uniformly distributed.
-160
-140
-120
-100
-80
-60
-40
-20
0
0.01 1 100 10000
Bare
Boa
rd G
ain
f (MHz)
AD4896-2 bare board Input-to-Output gain
6-layers2-layers
Power Supply Bypassing – Inter-planar and discrete bypassing method
37
-27
-24
-21
-18
-15
-12
-9
-6
-3
0
0.1 1 10 100 1000
Gai
n (d
B)
freq (MHz)
ADA4896-2 PCB responses. Input=-15dBm, G=1, Rf=100Ω, RL=100Ω
2-Layers
6-Layers
-27
-24
-21
-18
-15
-12
-9
-6
-3
0
0.1 1 10 100 1000G
ain
(dB
)
freq (MHz)
ADA4896-2 PCB responses. Input=-15dBm, G=1, Rf=0Ω, RL=100Ω
2-Layers
6-Layers
Power Supply Bypassing - Power Plane Capacitance
*Courtesy of Lee Ritchey
*
Parasitics
40
Parasitics
PCB parasitcs take the form of hidden
capacitors, inductors and resistors in the PCB
Parasitics degrade and distort performance
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113kXYC pF
Z=
K = relative dielectric constant X = Copper Length (mm) Y = Copper Width (mm)
Z = Distance to nearest Plane (mm)
20 2 0 5 2235X Y ZL X nHY Z X
. . ln . + = + + +
Trace/Pad Parasitics
X Y
Z
Top Solder mask Has effect on characteristic impedance
Top (Signal) layer Has signal traces and component landing
pads. Traces are transmission lines with
characteristic impedance
Controlled Impedance Plane Layer Traces on the top signal layer, the spacer
between and this plane forms transmission lines with a characteristic impedance.
Spacer Large distance to eliminate interaction with
Controlled Impedance Layer above it.
PWR-GND combination Two layers closely spaced layers form an
Interplanar capacitance.
Spacer eliminates interaction between the signal layer with its associated controlled impedance layer and all other layers below the controlled impedance layer.
Every unterminated trace and pad has capacitance and inductance.
EXAMPLES Choose FR4 PCB with 1 oz Cu on top
Need 50Ω controlled impedance for 10 mils and 0.2mm wide traces
K= 4.7, Z=0.16mm and 0.13mm
Example1: SOIC landing pad X = 0.51 mm Y = 1.27mm
Z = 0.16mm: C = 0.17 pF; L=0.08 nH Z = 0.13mm: C = 0.21 pF; L=0.08 nH
Example2: 3x3 mm CSP landing pad X = 0.6 mm Y = 0.3mm
Z = 0.16mm: C = 0.05 pF; L=0.05 nH Z = 0.13mm: C = 0.05 pF; L=0.05 nH
Minimize capacitance Reduce trace/pad area Increase spacing to plane layer Void plane under trace/pad
Minimize Inductance Reduce trace/pad length Increase trace/pad width Remove Voids in plane layer under
trace/pad Decrease spacing to plane layer
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Via Parasitics
𝐿 = 0.2𝐻 𝑙𝑙4𝐻𝑑 + 1 𝑙𝐻
𝐶 =0.055𝑘𝐻𝑑1𝑑2 − 𝑑1
𝑝𝑝
𝑤𝑤𝑤𝑤𝑤 𝑘 = 𝑑𝑑𝑤𝑙𝑤𝑑𝑑𝑤𝑑𝑑 𝑑𝑐𝑙𝑐𝑑𝑐𝑙𝑑.
𝐷𝑑𝑐𝑑𝑐𝑙𝑑𝑤𝑐 𝑐𝑤𝑤 𝑑𝑙 𝑚𝑚.
Example: A “10 mil via” on FR4 PCB d=0.254 mm, d1=0.55 mm, d2=1.1mm K=4.7, H=1.62 mm L=0.93 nH, C=0.48 pF
Vias are capacitive in signal traces, inductive when connecting to planes.
Vias are usually invisible to signals below 1 GHz.
Compare to a 10mm long 10 mils wide trace: L=8.8 nH, C=0.66 pF
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Simplified Component Parasitic Models
C = Capacitance RP = insulation resistance RS = equivalent series resistance (ESR) L = leads and plates series inductance RDA = dielectric absorption CDA = dielectric absorption
L
r
RP
C
RDA CDA
RS CP
R
L
R = Resistance CP = Parallel capacitance L= equivalent series inductance (ESL) Chip Resistors: Cp range from 0.25 – 1pF
Stray Capacitance Simulation Schematic
Frequency Response with 1.5pF Stray Capacitance
1.5dB peaking
Parasitic Inductance Simulation Schematic
24.5mm x .25mm” =29nH
Pulse Response With and Without Ground Plane
0.6dB overshoot
Signal Routing
Vias in signal path No hard evidence to their measurable degrading effect (up to ≈ 2GHz). Vias increase PCB real estate requirements.
Sharp corners, 90° bends in signal traces No hard evidence to their measurable degrading effect (up to ≈ 2GHz). Sharp corners and 90° turns can increase PCB real estate requirements.
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Signal Routing
51
Signal Routing
Use GND and PWR Planes Connect pads to planes using “Via-in-pad” method to minimize parasitics Use controlled impedance plane layer directly under or over a signal layer.
Place components of a functional block as close as possible 0.5 mm component-to-component spacing is sufficient for manual placement
Minimize vias in signal traces. The less the better. Keep traces within a functional block on the same layer.
Use interplanar capacitance for bypassing
Keep plane layers as contiguous as possible Avoid unnecessary vias perforating plane layers. Avoid cutouts in plane layers
Keep traces as straight as possible Minimize bends and turns
PCB Termination resistors
• Termination resistors as close to first component in signal path as possible.
• Long transmission line, minimized unterminated trace length.
• Optimized.
• Termination resistors as close to input connector as possible
• Short transmission line, long unterminated trace length.
• Not optimized.
PCB Don’t-s
• Too many vias. Internal plane layer perforated. Looks more of a mesh than a plane. Plane layer effectiveness is diminished.
• Copper plating is cheap. No resistance to corrosion. Landing pads are blemished after two months. PCB longevity is compromised.
• IC landing pads are too long. Increased parasitic capacitance.
• Silk screen text is not readable. Unnecessary expense in its current form.
• Component orientation appears ad hoc. Difficult to follow signal path during debug.
• Component designator placement not optimized. Difficult to locate components during debug.
Additional High Speed PCB Examples
Examples – Bandwidth improvement at 1 GHz
Small signal BW: New: 1.41 GHz Existing: 976 MHz This is nearly a 50% improvement
VOUT2
Pin4 – VN Pin8 – VP
R5
1 VOUT1
R13 IN1+
R7 2
3
IN1-
R1
R3
RS1
R11
R15
R9
7
5
6
R14 IN2+
R8 IN2-
R6
R2
R16
RS2
R12 R4
R10
C3 C2 C1
VP VN GND
C4 C5
Examples – Schematics and PCB
Examples – Bare board response
-160
-140
-120
-100
-80
-60
-40
-20
0
0.01 0.1 1 10 100 1000 10000
Bar
e B
oard
Gai
n
f (MHz)
AD4896-2 bare board Input-to-Output gain
6-layers2-layers
59
Summary Begin by selecting a strategy and putting a plan in place
Have a power supply bypass strategy in place.
Decide how to manage parasitics before you begin
A good layout starts with a good schematic
High speed PCB design requires deliberate thought and attention to detail!
Use multiple Ground, Power and controlled impedance planes
Component location on the board is just as important as to where you put entire circuits
Take the lead when laying out your board, don’t leave anything to chance
New packaging and pinouts allow for improved performance and more compact layouts
There are many options for signal distribution. Choose the right one for the application
Questions/Discussion
Design Resources Covered in this Session
Design Tools & Resources:
Ask technical questions and exchange ideas online in our EngineerZone™ Support Community Choose a technology area from the homepage: ez.analog.com
Access the Design Conference community here: www.analog.com/DC13community
[Other resources if available]
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Name Description URL
[Relevant tool]
[wiki site] Contains reference design materials, etc.
[other]
Selection Table of Products Covered Today
Part number Description
62
Visit the [name of demo] in the exhibition room
[Brief explanation of demo they will find in the exhibit hall]
Image of demo/board
63
This demo board is available for purchase: www.analog.com/DC13hardware
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Crosstalk and Coupling
65
Capacitive Crosstalk or Coupling This results from traces running on top of each other, which forms a
parasitic capacitor Solutions run traces orthogonal, to minimize trace coupling and lower area
profile
Inductive Crosstalk Inductive crosstalk exists due to the magnetic field interaction between long
traces parallel traces There are two types of inductive crosstalk; forward and backward Backward is the noise observed nearest the driver on the victim trace Forward is the noise observed farthest from the driver on the driven line
Minimize crosstalk by Increasing trace separation (improving isolation) Using guard traces Using differential signals
66
Electromagnetic compatibility (EMC)
There are two aspects of EMC: It describes the ability of electronic systems to operate without interfering with
other systems It also describes the ability of such systems to operate as intended within a
specified electromagnetic environment
Primary specifications are IEC-60050 and IEC1000
Extensive reviews in tutorial MT-095 and Analog Dialog 30-4 on Analog Devices website (www.analog.com)
Inability to meet these requirements will compromise your equipment
Inability to meet these requirements will severely limit the ability to sell the equipment to customers
67
Blank form
With the short signal transition times and high clock rates of modern digital circuitry, PCB traces need to be considered not as simple connections but as transmission lines.
The receiving aerial possesses a natural, or characteristic, impedance and electrical theory shows that for the aerial to transfer maximum power to the set (and to ensure the integrity of the electrical signal) the impedance both of the feeder and the receiver should match that of the aerial. In other words the signal should ideally be presented with a constant impedance as it travels from its source to its destination. Where a mismatch occurs only part of the signal will be transmitted; the rest will be reflected toward the source (this degrades the signal). Cable designers therefore take great care to ensure the accuracy and consistency of the cable dimensions and material characteristics. At high signal switching speeds, the electrical properties of the cable, such as the capacitance and inductance, must be taken into account, and cables can no longer be considered as simple wires. Cables designed for high signal speeds where these factors are taken into consideration are referred to as transmission lines. Similarly, as the speed of signal switching on a PCB increases, the electrical properties of the traces carrying signals between devices become increasingly more important. The impedance of a PCB trace is controlled by its configuration dimensions (trace width and thickness and height of the board material) dielectric constant of the board material As with a cable, when the signal encounters a change of impedance arising from a change in material or geometry, part of the signal will be reflected and part transmitted. These reflections are likely to cause aberrations on the signal which may degrade circuit performance (e.g. low gain, noise and random errors). In practice board designers will specify impedance values and tolerances for board traces and rely on the PCB manufacturer to conform to the specification.
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