laboratory exercise xilinx ise: vhdl synthesis andsimulation
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Department of Electrical and Computer Engineering, University of Cyprus
ECE314 - Computer Architecture Laboratory 1
Laboratory Exercise
Xilinx ISE: VHDL synthesis andsimulation
Aim
The lab exercise focuses on VHDL coding and simulation of simple logic circuits (full
adder and D flip-flop).
Objectives
Introduce Xilinx ISE software.
Become familiar with VHDL codingand useof the ISE simulator (ISim).
Be able to synthesize and map VHDL designs to FPGAs using ISE.
Equipment
Xilinx ISE13.3i
ISE Simulator (Isim)
Introduction
This is a step-by-step tutorial for building a 1-bit full adder and a D flip-flop in Xilinx
ISE 13, a Design Suite software that provides designers with the ability to code
designs in a hardware description language such as VHDL or Verilog. The ISE
Design Suite also provides the ability to apply FPGA pin and timing constraints,
analyse for errors and violations, and synthesize to generate configuration bit file
formats forFPGAs.
By the end of this tutorial, you should be able to:
• Create a new design by VHDL coding.
• Verify the function of a design by behavioral simulation.
• Map a design to an FPGA device through placement and routing procedures.
• Estimate the performance of the design by timing analysis.
• Use the 1-bit full adder and D flip-flop created in this tutorial to implement and
simulate a 16-bit accumulator (consisting of a 16-bit adder and a 16-bit register).
Department of Electrical and
Coding the Full Adder Circuit
An example 1-bit full adder block diagram
and (b), respectively. The objective of the lab i
and test its functionality using VHDL testbench
Tasks:
(1)Create a project file in Xilinx Project Navigator.
To launch the Project Navigator run
Xilinx ISE Design Suite 13.
project folder by selecting
tabs to name and store the project.
ISE does not support such ASCI
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Coding the Full Adder Circuit
block diagram and Boolean circuit are shown in Fig.1 (a)
and (b), respectively. The objective of the lab is to code the Boolean circuit in VHDL
test its functionality using VHDL testbench.
Fig.1 (a)
Fig.1 (b)
Xilinx Project Navigator.
To launch the Project Navigator run StartPrograms ECE Department
ISE Design Suite 13.3 ISE Design Tools Project Navigator
project folder by selecting FileNew Project. Use the Project Name and Location
name and store the project. (No spaces in the file path or file name
ISE does not support such ASCII characters)
A B C
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
and Boolean circuit are shown in Fig.1 (a)
s to code the Boolean circuit in VHDL
ECE Department
Project Navigator.Create a
. Use the Project Name and Location
(No spaces in the file path or file name – Xilinx
Cin Cout S
0 0 0
1 0 1
0 0 1
1 1 0
0 0 1
1 1 0
0 1 0
1 1 1
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In the Property tab set the Device to “XC5VLX100T-FF1136” (Virtex-5 device) and
the Design Flow to VHDL and Click NEXT. The next two windows ask for file
sources, these are not relevant at the moment so to continue press Next to both
windows.
Enter file name and path (no spaces in the path)
Enter FPGA device
details and required simulator
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(2) Create a VHDL module.
To create a VHDL module right-click on theicon xc5vlx110t-1ff1136(shown
below) and select New Source.
Now selectVHDL Module from the left-side of the menu and enter a name for the
file (for example “Full_Adder”) and click on Next (as shown below).
Create a new VHDL
Module
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In the Architecture Name tab write “Behavioral” and enter the appropriate inputs and
outputs of the 1-bit Full Adder in the Port Name tab. Select Next and Finish to create
the VHDL module. (Click through the remaining menu to complete). Select
FileSave-all. (Remember to regularly save your work)
A VHDL module should now appear in project navigator, as shown below. This
provides the entity and architecture layout for your circuit.
(3) Edit the VHDL file to realise the 1-bit full-adder circuit depicted in Fig.1 (b). The
VHDL code is highlighted in the red box of Fig 2(a). When you have coded the circuit
in VHDL run the syntax checker: This is available in the process window
underSynthesize-XST Check Syntax, see Fig.2(b) below. When the design is
error-free,synthesize the VHDL file: Double click onSynthesize-XST.
Specify the signal
names and directions for the new
VHDL Module
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Fig.2 (a)
Fig. 2 (b)
Design summary Tab
Synthesis Process
Adder VHDL Code
Synthesis report
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Fig. 2 (c)
Now examine the synthesis report – this is available by double-clicking Synthesize-
Report in the panel Design Summary, see Fig. 2(b). Scroll down the file to find the
section entitled Final Report, as shown in Fig. 2(c). Note the number of LUTs and
IBUF/OBUFs that have been synthesised to create the circuit.
Behavioral Simulation of a Full Adder
In this section, we will introduce the concept of test bench and show how to verify the
function of our full adder by behavioral simulation.
What is a test bench?
A test bench is an entity (usually a VHDL/Verilog program) which is used to verify
the correctness of a design. The design to be verified is called Unit Under Test (UUT).
The test bench supplies stimuli to the design, observes the outputs of the design, and
compares the observed outputs with the expected values. If any mismatch happens,
the test bench issues certain messages signifying that there are errors in the design.
Fig. 3 shows the concept of test bench.
Synthesis report
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Fig.3: Conceptual Diagram of a testbench.
Advanced EDA tools such as Xilinx ISE usually have the capability to automatically
generate the test bench. All theusers need to do is specifying the waveforms of the
stimuli and the expected outputs; the software produces the testbench program which
can be tailored later on.
Build the test bench by specifying waveforms
(1)In the Design Panel, select “Simulation”, click ‘Full_Adder - Behavioral’, and then
double-click ‘Simulate Behavioural Model’. You may need to hit the ‘+’ beside ‘ISim
Simulator’.
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(2) In the window that opens, change to the ‘Default.wcfg’ tab:
(3) You can rename the inputs/outputs by right-clicking them and hitting ‘rename’. If
you forget which ports are which, you can look back in ISE Project Navigator (not the
simulator). You can also right-click on a particular signal to initialize it to a constant
value, or define it as a clock.
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(4) Using the waveform display, fill in the truth table. You may need to scroll the
waveform to start at time 0. You can click on different times in the waveform and just
read S/Cout directly off. Fill in the observations based on this.
(5) Close the ISim window, it will ask if you really want to exit the application, hit
“Yes”.
Build the test bench using VHDL coding
Another way to simulate the circuit to verify its expected Boolean behaviour is by
manually creating a Testbench for the circuit.
Tasks
(1)Right click on xc5vlx110t-1ff1136 icon in the sources window and select New
Source, then select VHDL Test Bench and enter a filename and follow through to
finish
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(2) You should see a similar screen shot as shown in Fig.4.
Fig.4VHDL Testbench
Copy the following code into the Testbench file and select FileSave. Note: You
will need to remove the term <clock>_period in the file and replace it with
clock_period.You will also need to comment the lines of the process that generates
the clock, as our circuit is a combinational one. The screen shots above and below
provide a few examples of where these changes are required – complete all of them.
Appendix A provides the complete Testbench code.
Edit the Testbench to include the following
------- insert stimulus here ---------- A <= '1'; B <= '1';
Cin <= '1'; wait for clock_period*2;
A <= '0'; B <= '1';
Cin <= '1'; wait for clock_period*2;
A <= '1'; B <= '0';
Cin <= '0'; wait for clock_period*2;
----------------------------------------------
Make sure to select
Simulation in the view!!
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(3) Now select the Testbench file Full_Adder_test, in the top window in the left; the
following process will appear in the bottom window. Select the process Simulate
Behavioral Model and click-on RUN. This will invoke the ISim simulator and
execute the Testbench file Full_Adder_test.
(4) You should now have a similar screen shot as shown below with the Testbench
waveform to the right and its file equivalent to the left in the Sources window. The
simulation plot shown below shows the output from the circuit when the following
input values forA, B and Cin are stimulated. The values on S and Cout appear after
the simulation run.
A <= '0'; B <= '1'; Cin <= '1'; S<= ‘0’; Cout <= ‘1’;
A <= '1'; B <= '1'; Cin <= '1'; S<= ‘1’; Cout<= ‘1’;
A <= '1'; B <= '0'; Cin <= '0'; S<= ‘1’; Cout<= ‘0’;
Make sure to select
Simulation in the view!!
Select the testbenchfile
Select
Simulate Behavioral
Model process
Correct simulation outputs showsS=1and Cout=0when A=1,
B=0and Cin=0
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Coding and Simulation of a 16-bit accumulator Now that you have implemented and simulated your full adder circuit, you should be able to follow the same procedures to do the following:
- Use the 1-bit full adder to code and simulate a 16-bit adder - Code and simulate a D flip-flop - Use the D flip-flop to code and simulate a 16-bit register - Combine the 16-bit adder and register to implement an accumulator circuit
An accumulator is a synchronous digital circuit, which adds input value to its internal value.
Our accumulator should have the following ports: DIN - Data Input; DOUT - Data Output; CLK - Clock; CLR - Asynchronous clear (set register to 0); Deliverables The exercise (code, simulation files and report) will be submitted electronically through email (viktoros.stavros@ucy.ac.cy). Exercises submitted after the deadline will be penalized with the loss of 10 points for each day late.
GOOD LUCK
Department of Electrical and Computer Engineering, University of Cyprus
ECE314 - Computer Architecture Laboratory 14
APPENDIX A: -------------------------------------------------------------------------------- ---------- Testbench for Full Adder Circuit -------------------------- -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY Full_Adder_test IS END Full_Adder_test; ARCHITECTURE behavior OF Full_Adder_test IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT Full_Adder PORT( A : IN std_logic; B : IN std_logic; Cin : IN std_logic; Cout : OUT std_logic; S : OUT std_logic ); END COMPONENT; --Inputs signal A : std_logic := '0'; signal B : std_logic := '0'; signal Cin : std_logic := '0'; --Outputs signal Cout : std_logic; signal S : std_logic; -- No clocks detected in port list. Replace <clock> below with -- appropriate port name constant clock_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: Full_Adder PORT MAP ( A => A, B => B, Cin => Cin, Cout => Cout, S => S ); -- -- Clock process definitions -- clock_process :process -- begin -- clock <= '0'; -- wait for clock_period/2; -- clock <= '1'; -- wait for clock_period/2; -- end process; -- Stimulus process
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ECE314 - Computer Architecture Laboratory 15
stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; wait for clock_period*10; -- insert stimulus here A <= '1'; B <= '1'; Cin <= '1'; wait for clock_period*2; A <= '0'; B <= '1'; Cin <= '1'; wait for clock_period*2; A <= '1'; B <= '0'; Cin <= '0'; wait for clock_period*2; wait; end process; END;
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