logic design ii (17.342) spring 2012 lecture...

Logic Design II (17.342)

Spring 2012

Lecture Outline

Class # 09

April 05, 2012

Dohn Bowden

Today’s Lecture

• Finish … Reduction of State Tables State Assignments … Chapter 15

• Then … Sequential Circuit Design … Chapter 16

CourseAdmin

Administrative

• Admin for tonight …

– Syllabus review

• Lab #2 is due on 4/12 … changed this last week from 4/5

• Starting next week …

– The class will be split half lecture … half lab time

» Lab time to work on your project

– Lab will be held in BL-407

Syllabus Review

Week Date Topics Chapter Lab Report Due

1 01/26/12 Review of combinational circuits 1-10

2 02/02/12 Intro to sequential circuits. Latches and flip-flops 11

3 02/09/12 Registers and Counters 12

4 02/16/12 Registers and Counters … continued 12

5 02/23/12 Analysis of Clocked Sequential Circuits 13 1

X 03/01/12 Class Cancelled Due to Weather

6 03/08/12 Examination 1

X 03/15/12 NO CLASSES – Spring Break

7 03/22/12 Derivation of State Graphs and Tables 14

8 03/29/12 Reduction of State Tables State Assignments 15

9 04/05/12 Sequential Circuit Design 16

10 04/12/12 Circuits for Arithmetic Operations/ Lab for Project 18 2

1104/19/12

Examination 2 – Take Home 3

12 Circuits for Arithmetic Operations / State Machine Design with SM Charts / Lab for Project 18/19

13 04/26/12 Course Project – Build/Troubleshoot in Lab Project 4

14 05/03/12 Final Exam/Course Project Brief & Demo Demo

Course Project

• Guidelines are on the Class Web Page

• Any questions???

Questions?

Chapter 15 (con’t) …

Reduction of State Tables State Assignments

Guidelines for State Assignment

• Trying all nonequivalent state assignments is not practical in most cases

• The following guidelines are useful in making assignments which will place 1’s together (or 0’s together) on the next-state maps …

1. States which have the same next state for a given input should be given adjacent assignments

2. States which are the next states of the same state should be given adjacent assignments

3. States which have the same output for a given input should be given adjacent assignments– The application of Guideline 3 will place 1 's together on the

output maps10

• When using the state assignment guidelines …

– The first step is to write down all of the sets of states which should be given adjacent assignments according to the guidelines

– Then … using a K-map … try to satisfy as many of these adjacencies as possible

• A fair amount of trial and error may be required to fill in the map so that the maximum number of desired state adjacencies is obtained

• When filling in the map … keep in mind the following …

a) Assign the starting state (reset state) to the "0" square on the map

I. Nothing is to be gained by trying to put the starting state in different squares on the map because the same number of adjacencies can be found no matter where you put the starting state

II. Usually … assigning "0'' to the starting state simplifies the initialization of the circuit using the clear inputs on the flip-flops

• Con’t … When filling in the map … keep in mind the following …

b) Adjacency conditions from Guideline 1 and adjacency conditions from Guideline 2 that are required two or more times should be satisfied first

c) When guidelines require that three or four states be adjacent … these states should be placed within a group of four adjacent squares on the assignment map

• Con’t ... When filling in the map … keep in mind the following …

d) If the output table is to be considered … then Guideline 3 should also be applied

The priority given to adjacency conditions from Guideline 3 should generally be less than that given to Guidelines 1 and 2 if a single output function is being derived

If there are two or more output functions … a higher priority for Guideline 3 may be appropriate

Example …

According to Guideline 1 … S0, S2, S4, and S6 should be given adjacent assignments because they all have S1 as a next state (with input 0)

From Guideline 2 … S1 and S2 should be given adjacent assignments (both are next states of S0)

Example …

• Next State Map for the given State Table …

Example …

• Apply the state assignment guidelines to the state table and assignments …

• First … list the sets of adjacent states specified by each Guideline …

1. (b, d) (c, f) (b, e)

2. (a, c)2x (d, f) (b, d) (b, f) (c, e)

3. (a, c) (b, d) (e, f)

• Next … we try to arrange the states on a map so as to satisfy as many of these pairs as possible … giving preference to the duplicated pairs … (b,d) and (a,c)

1. (b, d) (c, f) (b, e)

2. (a, c)2x (d, f) (b, d) (b, f) (c, e)

3. (a, c) (b, d) (e, f)

• Derive D flip-flop input equations … • First … construct the transition table from the state table …

– Replace a with 100 … b with 111 … etc …

• Next plot the next-state and output maps…

• From the transition table … The D flip-flop input equations can be read directly from these maps …

Using a One-Hot State Assignment

• Sometimes reducing the number of flip-flops used is not as important as reducing the logic feeding into the flip-flops

• Using a one-hot state assignment may help accomplish this

• The one-hot assignment uses … one flip-flop for each state …

– So a state machine with N states requires N flip-flops

• Exactly one of the flip-flops is set to one in each state

Example …

• Write next-state and output equations by inspecting the state graph

• By simple inspection of the graph …

Q3+ = X1Q0 + X2Q1 + X3Q2 + X4Q3

Z2 = X2Q1 + X4Q3

Example …

• Write next-state and output equations by inspecting the state graph

• By simple inspection of the graph …

Q0+ = Q0St′ + Q3

Q1+ = Q0St + Q1K′M′ + Q2K′

Sh = Q1(K′M′ + KM′) + Q2(K′ + K) = Q1M′ + Q2

Chapter 16 …

SEQUENTIAL CIRCUIT DESIGN

Objectives

1. Design a sequential circuit using gates and flip-flops

2. Test your circuit by simulating it and by implementing it in lab

3. Design a unilateral iterative circuit. • Explain the relationship between iterative and sequential

circuits … and … convert from one to the other

4. Show how to implement a sequential circuit using a ROM or PLA and flip-flops

5. Explain the operation of CPLDs and FPGAs and show how they can be used to implement sequential logic

Summary of Design Procedure for Sequential Circuits

1. Given the problem statement … determine the required relationship between the input and output sequences and derive a state table

• For many problems it is easiest to first construct a state graph

2. Reduce the table to a minimum number of states

• First … eliminate duplicate rows by row matching … and then … form an implication table and determine state equivalence

3. If the reduced table has m states (2n – 1 < m ≤ 2n) … n flip-flops are required

• Assign a unique combination of flip-flop states to correspond to each state in the reduced table

4. Form the transition table by substituting the assigned flip-flop states for each state in the reduced state table

• The resulting transition table specifies the next states of the flip-flops and the output in terms of the present states of the flip-flops and the input

5. Plot next-state maps and input maps for each flip-flop and derive the flip-flop input equations

– Depending on the type of gates to be used, either determine the sum-of-products form from the 1’s on the map or the product-of-sums form from the 0’s on the map

– Derive the output functions

6. Realize the flip-flop input equations and the output equations using the available logic gates

7. Check your design by signal tracing … computer simulation … or … laboratory testing

Design Example … Code Converter

• Example … Design a sequential circuit to convert BCD to excess-3 code. This circuit adds three to a binary-coded-decimal digit in the range 0 to 9. The input and output will be serial with the least significant bit first. A list of allowed input and output sequences is shown in the Table below …

• The table lists the desired inputs and outputs at the associated times

• After receiving four inputs … the circuit should reset to the initial state … ready to receive another group of four inputs

• It is not clear at this point whether a sequential circuit can actually be realized to produce the output sequences without delaying the output

• For example … if at t0 some sequences required an output Z = 0 for X = 0 and other sequences required Z = 1 for X = 0 … it would be impossible to design the circuit without delaying the output

• Table below … at t0 … if the input is 0 … the output is always 1 … and if … the input is 1 the output is always 0 … therefore … there is no conflict at t0

• At time t1 only inputs received are t1 and t0 … – If … 00 has been received at t1 and to … output at t1 = 1 – If … 01 has been received … the output at t1 = 0 – If … 10 and 11 the outputs at t1 should be 0 and 1 respectively

• Therefore … there is no output conflict at t1

• Checking t2 and t3 in the same manner … – No output conflict exists

• Setting up the state table …

• The arrangement of next states in the table is different from before … because the input sequences are received with least significant bit first … before the first input bit received is listed first in the sequence

• Remainder of the State Table … • Dashes (don't-cares) … only 10 of the 16 possible 4-bit sequences

can occur as inputs to the code converter• If the circuit is in state B at t1 and a 1 is received … this means that

the sequence 10 has been received and the output should be 0

• Reduce the table using row matching … – When matching rows which contain dashes (don't-cares) …

• A dash will match with any state or with any output value

• Reduce the table using row matching … – Resulting in … H ≡ I ≡ J ≡ K ≡ L … and M ≡ N ≡ P

• Therefore … rows can be eliminated … states replaced

Alternate Procedure …

• An alternate approach to deriving the State Table is to …

– Start with a state graph

• The state graph has the form of a tree– Each path starting at the reset state represents one of the ten

possible input sequences

• After the paths for the input sequences have been constructed … the outputs can be filled in by working backwards along each path

• For example …– Starting at t3 … the path 0 0 0 0 has outputs 0 0 1 1 …and …– The path 1 0 0 0 has outputs 1 0 1 1

• Three flip-flops are required … there are seven states

• Each of the states must be assigned a unique combination of flip-flop states

• Some assignments will lead to economical circuits with only a few gates … while other assignments will require many more gates

• Using prior guidelines … below states should be given adjacent assignments in order to simplify the next-state functions … – B … and … C– D … and … E – H … and … M

• To simplify the output function … below states should be given adjacent assignments …– A … B … E … and M – C ... D … and …H

• A good assignment for this example is given on the map and table in Figure 16-2.

• Below shows a good assignment …

• Next … the transition table is filled in according to the assignment…

• Next … next-state maps are plotted …

• Next … The D input equations are then read off the Q+ maps …

• Finally … The resulting sequential circuit …

Design of Iterative Circuits

• Many of the design procedures used for sequential circuits can be applied to the design of iterative circuits

• An iterative circuit … consists of a number of identical cells interconnected in a regular manner

• The simplest form of an iterative circuit consists of …

– A linear array of combinational cells with signals between cells traveling in only one direction

• Each cell is a combinational circuit with one or more primary inputs … xi … and possibly one or more primary outputs … Zi …

• Each cell has one or more secondary inputs … ai … and one or more secondary outputs … ai + 1

• The … ai … signals carry information about the "state" of one cell to the next cell

• The primary inputs to the cells … x1 … … x2 ... Xn … are applied in parallel

• The ai signals then propagate down the line of cells

• The circuit is combinational … the time required for the circuit to reach a steady state condition is determined only by the delay times of the gates in the cells

• When steady state is reached … the outputs may be read

• Thus ... the iterative circuit can function as a parallel-input … parallel-output device … in contrast with the sequential circuit in which the input and output are serial

• An iterative circuit receives its inputs as a sequence in space … in contrast with …

– The sequential circuit which receives its inputs as a sequence in time

• Some operations … such as …

– Binary addition … naturally lend themselves to realization with an iterative circuit because …

• The same operation is performed on each pair of input bits

Design of a Comparator …

Design of a Comparator

• Example … Design a circuit which compares two n-bit binary numbers and determines if they are equal or which one is larger if they are not equal

X = x1x2 … xn … and …Y = y1y2 … yn

• x1 is the most significant … will be comparing from left to right

• Comparison proceeds from left to right

• The first cell compares x1 and y1 and passes on the result of the comparison to the next cell …

• The second cell compares x2 and y2 … etc …

• Finally xn and yn are compared by the last cell and the output circuit produces signals to indicate if X = Y … X > Y … or … X < Y

• We will now design a typical cell for the comparator

• To the left of cell i … three conditions are possible …

1. X = Y so far2. X > Y so far3. X < Y so far

• Designate these three input conditions … Si … as states …

S0 … S1 … and … S2 … ( X = Y so far … X > Y so far … X < Y so far)

• Output state at the right of the cell Si + 1 in terms of the xiyi inputs … and … the input state at the left of the cell … Si

– To the left of cell i … three possible conditions …

S0 = (X = Y) S1 = (X > Y) S2 = (X < Y)

• If the numbers are equal to the left of cell i and xi = yi …

– Then the numbers are still equal including cell i … so …

Si+1 = S0 Where … X = Y

• If Si = S0 … and … xiyi = 10 … then x1x2…xi>y1y2…yi and Si+1 = S1

– so …

Si+1 = S1 Where … X > Y

• If Si = S0 … and … xiyi = 01 … then x1x2…xi<y1y2…yi and Si+1 = S2

– so …

Si+1 = S2 Where … X < Y

• Resulting state table for the comparator …

• Using the guidelines … leads to the state assignment aibi = 00 for S0, 01 for S1, and 10 for S2 …

• K-maps … next-state equations … and the realization of a typical cell using NAND gates

• The output circuit …

• Conversion to a sequential circuit is straightforward

• If inputs are received serially instead of in parallel … the following table is interpreted as a state table for a sequential circuit … and the next-state equations are the same as before …

• If D flip-flops are used … the typical cell previously determined can be used as the combinational part of the sequential circuit …

• Below shows the resulting circuit• After all of the inputs have been read in … the output is determined

from the state of the two flip-flops

Design of Sequential Circuits Using ROMs and PLAs

• A sequential circuit can be designed using a and flip-flops

• For a Mealy sequential circuit … the combinational part of the sequential circuit can be realized using a ROM

– The ROM can be used to realize the output functions and the next-state functions

• The state of the circuit can then be stored in a register of D flip-flops and fed back to the input of the ROM

• The Moore sequential circuit can be realized in a similar manner to that of the Mealy

– The next-state and output combinational subcircuits of the Moore circuit can be realized using two ROMs

• Alternatively … a single ROM can be used to realize both the next-state and output functions

• Use of D flip-flops is preferable to J-K flip-flops because …

– The use of two-input flip-flops would require increasing the number of outputs from the ROM

• D flip-flop input equations would generally require more gates than the J-K equations …

– However … it is of no consequence because the size of the ROM depends only on the number of inputs and outputs and not on the complexity of the equations being realized

Example Using a ROM …

Design Example … Code Converter - Using a ROM

• Example … same example as earlier … Design a sequential circuit to convert BCD to excess-3 code. This circuit adds three to a binary-coded-decimal digit in the range 0 to 9. The input and output will be serial with the least significant bit first. A list of allowed input and output sequences is shown in the Table below …

• Realize the converter using a ROM and D flip-flops …

• The same state table as prior for the converter is shown below …

• Seven states … therefore … three D flip-flops required

• A ROM with four inputs … 24 words … and four outputs is required

• Create the transition table … using a straight binary state assignment … which gives the next state of the flip-flops as a function of the present state and input

• The truth table for the ROM is developed from the transition table

– The truth table gives the ROM outputs as functions of the ROM inputs …

• Realization using a ROM …

PLAs …

Design of Sequential Circuits Using PLAs

• Sequential circuits can also be realized using PLAs and flip-flops in a manner similar to using ROMs and flip-flops

• However … the state assignment may be important because the use of a good state assignment can reduce the required number of product terms … and … hence …

– Reduce the required size of the PLA

Example Using a PLA …

Design Example … Code Converter - Using a PLA

• Example … same Code Converter as earlier except use a PLA … Design a sequential circuit to convert BCD to excess-3 code. This circuit adds three to a binary-coded-decimal digit in the range 0 to 9. The input and output will be serial with the least significant bit first. A list of allowed input and output sequences is shown in the Table below …

• If the state assignment previously determined earlier in this lecture is used … the resulting output equation and D flip-flop input equations derived can be used …

• Output equation and D flip-flop input equations are …

D1 = Q1+ = Q2′

D2 = Q2+ = Q1

D3 = Q3+ = Q1Q2Q3 + X ′Q1Q3′ + XQ1′Q2′

Z = X ′Q3′ + XQ3

• The PLA table which corresponds to these equations is …

X Q1 Q2 Q3 Z D1 D2 D3 – – 0 – 0 1 0 0 – 1 – – 0 0 1 0 – 1 1 1 0 0 0 1 0 1 – 0 0 0 0 1 1 0 0 – 0 0 0 1 0 – – 0 1 0 0 0 1 – – 1 1 0 0 0

• Realization of the below table requires a PLA with …– Four inputs …– Seven product terms … and … – Four outputs …

X Q1 Q2 Q3 Z D1 D2 D3 – – 0 – 0 1 0 0 – 1 – – 0 0 1 0 – 1 1 1 0 0 0 1 0 1 – 0 0 0 0 1 1 0 0 – 0 0 0 1 0 – – 0 1 0 0 0 1 – – 1 1 0 0 0

Segment of Sequential PAL …

Segment of Sequential PAL

• PALs provide a convenient way of realizing sequential circuits

• PALs are available which contain D flip-flops that have their inputs driven from programmable array logic

• Below shows a segment of a sequential PAL …

• D flip-flop is driven from an OR gate which is fed by two AND gates

• The flip-flop output is fed back to the programmable AND array through a buffer

• The AND gate inputs can be connected to A, A‘, B, B', Q, or Q‘

• The X's on the diagram show the connections required to realize the next-state equation …

Q+ = D = A′BQ′ + AB′Q

Sequential Circuit Design Using CPLDs

• A typical CPLD contains a number of macrocells that are grouped into function blocks

– Connections between the function blocks are made through an interconnection array

• Some CPLDs are based on PALs … in which case each OR gate has a fixed set of AND gates associated with it

• Other CPLDs are based on PLAs … in which case any AND gate output within a function block can be connected to any OR gate input in that block

• Below shows the structure of a Xilinx CoolRunner II CPLD …– Which uses a PLA in each function block

• Below represents a CoolRunner-II macrocell and the associated AND array

• Below shows how a Mealy sequential machine with two inputs … two outputs … and … two flip-flops can be implemented by a CPLD

• Below shows how the 4-bit loadable right-shift register can be implemented using four macrocells of a CPLD

• Below shows how three bits of the parallel adder with accumulator can be implemented using a CPLD

Sequential Circuit Design Using FPGAs

• An FPGA usually consists of an array of configurable logic blocks (CLBs) surrounded by a ring of I/O blocks

• The FPGA may also contain other components such as memory blocks … clock generators … tri-state buffers … etc

• A typical CLB contains two or more function generators … often referred to as look-up tables or LUTs … programmable multiplexers … and … D-CE flip-flops

• The I/O blocks usually contain additional flip-flops for storing inputs or outputs and tri-state buffers for driving I/O pins

• Below shows a simplified block diagram for a Xilinx Virtex or Spartan II CLB … configurable logic blocks

• The CLB is divided into two nearly identical slices

• Each slice contains two 4-variable function generators (LUTs) … two D-CE flip-flops … and additional logic for carry and control

• Additional logic includes … MUXes for selecting the flip-flop inputs and for multiplexing the LUT outputs to form functions of five or more variables

• Below shows how a Mealy sequential machine with two inputs … two outputs … and … two flip-flops can be implemented by a FPGA

• Below shows how the 4-bit loadable right-shift register can be implemented using an FPGA

• Below shows how three bits of the parallel adder with accumulator can be implemented using an FPGA

Simulation and Testing of Sequential Circuits

• The state table of a sequential circuit can be checked out with a simulator or in lab as follows …

1. Using the direct set and clear inputs … set the flip-flop states to correspond to one of the present states in the table

2. For a Moore machine … check to see that the output is correctFor a Mealy machine … check to see that the output is correct for each input combination

3. For each input combination … clock the circuit and check to see if the next state of the flip-flops is correct– Reset the circuit to the proper state before each input

combination is applied4. Repeat steps …1 … 2 … and … 3 for each of the present states in

the table

• No two gates of a given type will have exactly the same delay

• The value of the delay may change depending on … temperature and voltage levels

• Manufacturers often specify a minimum and maximum delay value for each type of logic element

• Some simulators can take the minimum and maximum delay values into account …

– Instead of showing the exact time at which a signal changes … the simulator output indicates a time interval in which the signal may change

• Below shows the output from an inverter which has a nominal delay of 10 ns … minimum delay of 5 ns … maximum delay of 15 ns

• The shaded region indicates that the inverter output may change at any time during the interval

• Min-max delay simulators can be used to …

– Verify that a digital system will operate correctly as tong as the delay in each element is within its specified range

• Below shows a simulator screen for testing the Mealy sequential circuit …

• To step through the circuit one input at a time … switches are used for the Clock and X inputs …

• Another switch is used to reset both flip-flops … and two switches are used to set flip-flops A and B …

• Probes are used to observe the Z output and the state of the flip-flops …

• After X has been set to the desired value … the clock cycle is simulated by flipping the Clock switch to 1 and back to 0 …

• Instead of manually stepping through the input sequence …

– Simulated input waveforms may be defined for X and Clock

• The following shows the simulator input using the test sequenceX= 10101

• Run the simulator … the timing chart will be generated for …

… A … B … and … Z

• The simulator output assumes the unit delay model … – Each gate or flip-flop has one unit of delay

• The following shows the same simulation using a nominal delay of 10 ns for each gate and flip-flop …

Synchronization

• If we operate our circuits at a high clock rate … then synchronization becomes a problem

– One must either generate our input sequences in synchronization with the clock … or …

• Use a special circuit to synchronize the inputs with the clock

• The following is a special circuit to synchronize the inputs with the clock …

– Loading the inputs into a shift register … and then …

• Using the circuit clock to shift them into the circuit one at a time

• If the input changes are not synchronized with the clock … edge-triggered D flip-flops can be used to synchronize them …

• X 1 and X2 change at arbitrary times with respect to the clock …• X 1S and X2S change after the rising clock edge … and …• The inputs to the sequential circuit are properly synchronized …

• The design has an inherent problem and may occasionally fail to operate properly …

• If D input changes very close to the rising clock edge so that setup and hold times are not satisfied … one of the flip-flops may malfunction

More Reliable Synchronizer

• Below shows a more reliable synchronizer that uses two D flip-flops to synchronize a single asynchronous input … X …

• X can change from 0 to 1 in the critical region where the setup or hold time is not satisfied …

• This is the region of uncertainty and is indicated by the shading …

• Clock period is chosen so that Q1 will be settled in either the 0 or 1 state by t2 …

• Because X is an asynchronous input … normally it will not matter whether X1S is delayed by one or two clock periods

• The important thing is that X1S is a clean signal that is synchronized with the clock …

Overview of Computer-Aided Design

• A wide variety of computer-aided design (CAD) software tools are available to assist in the design of digital systems

• Several functions performed by CAD tools are …– Generation and minimization of logic equations– Generation of bit patterns for programming PLDs– Schematic capture– Simulation– SimUaid– Synthesis tools– IC design and layout– Test generation– PC board layout

• A method of designing a small digital system with an FPGA uses the following steps …

1. Draw a block diagram of the digital system. Define the required control signals and construct a state graph that describes the required sequence of operations.

2. Work out a detailed logic design of the system using gates, flip-flops, registers, counters, adders, etc.

3. Construct a logic diagram of the system using a schematic capture program.

4. Simulate and debug the logic diagram and make any necessary corrections to the design.

5. Run an implementation program that fits the design into the target FPGA. This program carries out the following steps …

(a) Partition the logic diagram into pieces that will fit into CLBs of the target FPGA.

(b) Place the CLBs within the logic cell array of the FPGA and route the connections between logic cells.

(c) Generate the bit pattern necessary to program the FPGA.

6. Run a timing simulation of the completed design to verify that it meets specifications. Make any necessary corrections and repeat the process as necessary.

7. Download the bit pattern into the internal configuration memory cells in the FPGA and test the operation of the FPGA.

• Lab #2 is on the Class Web Page

– Due … April 12th

Next Week …

Next Week Topics

• Chapter 18 … Circuits for Arithmetic Operations

• Pages 594 – 607

Home Work

Homework

1. Read …

– Chapter 18 … Circuits for Arithmetic Operations

– Pages 594 – 607

2. Chapter 16 … Exercises with answers in the back of book

3. Work on Lab #2 … due next week

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