migrating from sdram to ddr bill gervasi vice chairman, jedec memory timing technology analyst...

MIGRATING FROM MIGRATING FROM SDRAM TO DDRSDRAM TO DDR

Bill GervasiBill Gervasi

Vice Chairman, JEDEC Memory TimingVice Chairman, JEDEC Memory Timing

Technology AnalystTechnology Analyst

bilge@transmeta.combilge@transmeta.com

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Topics to CoverTopics to Cover About JEDEC & DDRAbout JEDEC & DDR Market Segments & FragmentsMarket Segments & Fragments Design ArchitecturesDesign Architectures DDR SolutionsDDR Solutions Changes from SDR to DDRChanges from SDR to DDR Timing DiagramsTiming Diagrams Impact to board designImpact to board design Why Not Rambus?Why Not Rambus?

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About JEDEC & DDRAbout JEDEC & DDR

Setting open standards for >25 yearsSetting open standards for >25 years Consortium of 350 companiesConsortium of 350 companies

Memory suppliersMemory suppliers Users from all market segmentsUsers from all market segments

Double Data Rate (DDR) SDRAMDouble Data Rate (DDR) SDRAM Latest approved JEDEC standardLatest approved JEDEC standard Results of collaborative market analysisResults of collaborative market analysis

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Segments & FragmentsSegments & FragmentsServers

Workstations

PC Segment 2

PC Segment 1

PC Segment 0

Mobile

Graphics

2H99 1H00 2H00 1H01

PC100 DDR

PC100 DDR

PC100 RambusDDR

PC100

PC100

PC66 PC100 DDR

PC133

PC133

SS167 DDR SDRAM (x16)

DDR

2H01

RambusDDR

PC133

PC133

PC133

DDR SDRAM(x32)

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Market FactorsMarket Factors

Server per-system memory capacity Server per-system memory capacity increasing faster than PCincreasing faster than PC

Segments 1, 2 split Intel & non-IntelSegments 1, 2 split Intel & non-Intel UMA graphics takes over Segs 0 & 1UMA graphics takes over Segs 0 & 1

““Sealed Box” PC for home marketSealed Box” PC for home market

Mobile market mostly skips PC-133Mobile market mostly skips PC-133 DDR power lower than SDRDDR power lower than SDR

Graphics early: short design cyclesGraphics early: short design cycles

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RAM EvolutionRAM Evolution

320MB/s400MB/s

1000MB/s

2100MB/s

MainstreamMemories

FPEDO

SDR

DDR

Simple,incrementalsteps

DDR II3200MB/s

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Continued TraditionContinued Tradition

DDR is the logical incremental stepDDR is the logical incremental step Performance enhancementsPerformance enhancements Detailed documentationDetailed documentation Full support from vendors & usersFull support from vendors & users

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System DesignsSystem Designs

Sockets & StubsSockets & Stubs 133MHz clock133MHz clock 2.1GB/s transfer2.1GB/s transfer

Point to pointPoint to point 200MHz clock200MHz clock 3.2GB/s transfer3.2GB/s transfer

Small

Systems

Controller

PC/Server

Memory

Controller*

* Single chip or separateclock, data & address chips

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DDR SolutionsDDR Solutions

PC-266 Devices

PC-2100 Modules

1-4 Slots

Long traces, < 8”

Termination

No dummy modules

SS-400 Devices

Direct connect2-8 DDR SDRAMs

Short traces, < 2”

No termination

Built for speed

PC/Server Applications Small Systems

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How Different is DDR?How Different is DDR?

Simple upgrade to SDR designsSimple upgrade to SDR designs Similar PCB characteristicsSimilar PCB characteristics Same fast RAS/CAS command setSame fast RAS/CAS command set

A few evolutionary improvementsA few evolutionary improvements Bidirectional data strobeBidirectional data strobe Low voltage swing I/OLow voltage swing I/O

JEDEC StandardsJEDEC Standards Data sheet including IBIS curvesData sheet including IBIS curves Module gerbers, application notesModule gerbers, application notes

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From SDR to DDRFrom SDR to DDR

Signaling Clocks

Data Strobe

Packages

Pin Count

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From SDR to DDRFrom SDR to DDR

Signaling Clocks

Data Strobe

Packages

Pin Count

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DDR SignalingDDR Signaling

SSTL_2 low voltage swing inputsSSTL_2 low voltage swing inputs 2.5V I/O with 1.25V reference voltage2.5V I/O with 1.25V reference voltage Low voltage swing with terminationLow voltage swing with termination Rail to rail if unterminatedRail to rail if unterminated

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From SDR to DDRFrom SDR to DDR

SignalingClocks

Data Strobe

Packages

Pin Count

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DDR ClocksDDR Clocks

Differential clocks on adjacent tracesDifferential clocks on adjacent traces Timing is relative to crosspointTiming is relative to crosspoint Helps insure 50% duty cycleHelps insure 50% duty cycle

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““Slow” Signal TimingSlow” Signal Timing

Based on CK Based on CK Loading mismatch, Loading mismatch, single data rate single data rate Addresses & Control signalsAddresses & Control signals

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From SDR to DDRFrom SDR to DDR

Signaling Clocks

Data Strobe

Packages

Pin Count

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““Fast” DDR Read TimingFast” DDR Read Timing

Data valid on rising & falling edgesData valid on rising & falling edges Source Synchronous:Source Synchronous:

Data Strobe “DQS” travels with dataData Strobe “DQS” travels with data

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Read Timing 200MHz CKRead Timing 200MHz CK

tDV insures worst case shift on DQS can’t happen(sufficient timing margin for system design!)

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A Totally Sync DesignA Totally Sync Design

Operate solely in memory clock Operate solely in memory clock timing domaintiming domain

Fast design for small systemsFast design for small systems Tight layout requiredTight layout required

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““Fast” DDR Write TimingFast” DDR Write Timing

DQS centered in data valid eyeDQS centered in data valid eye DM timing & loading DM timing & loading identicalidentical to DQ to DQ

Flexible to support large systemsFlexible to support large systems

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DDR Write Design HintDDR Write Design Hint

“Perfect” alignmentat 1.0 * tCK

Good solution forsingle chipcontrollers

Early DQS stresses back to back opsEarly DQS stresses back to back ops Late stresses the array updateLate stresses the array update

1.0 * t1.0 * tCKCK is best is best

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Emphasis on “Matched”Emphasis on “Matched” DM/DQS loading identical to DQDM/DQS loading identical to DQ Route as independent 8bit busesRoute as independent 8bit buses

DQ/DQS

DM

VREF

VREF

VREF

VREF

Disable

CONTROLLER DDR SDRAM

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64 = 8 x 864 = 8 x 8

64bit bus is 8 sync’ed 8bit buses64bit bus is 8 sync’ed 8bit buses Allows external “copper” flexibilityAllows external “copper” flexibility 8 buses resync upon entry to FIFO8 buses resync upon entry to FIFO

8 DQ1 DM1 DQS

8bit Buffer 8bit Buffer

8 DQ1 DM1 DQS

x16 DDRSDRAM

x16 DDRSDRAM

x16 DDRSDRAM

64bit Memory Controller Internal FIFOSync to

Controllerclock

Copperfrom

controllerto SDRAMs

InsideController

x16 DDRSDRAM

8 DQ1 DM1 DQS

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From SDR to DDRFrom SDR to DDR

Signaling Clocks

Data StrobePin Count

Packages

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PackagesPackages DeviceDevice

66pin TSOP same size as 54pin TSOP66pin TSOP same size as 54pin TSOP Same 400x875mil, .65mm vs .80mmSame 400x875mil, .65mm vs .80mm

DIMMDIMM 184pin same size as 168pin 184pin same size as 168pin Same 5.25”, same pin pitch (key filled)Same 5.25”, same pin pitch (key filled)

SO-DIMMSO-DIMM 200pin slightly longer than 144pin200pin slightly longer than 144pin 73mm vs. 68mm, .65mm vs. .80mm 73mm vs. 68mm, .65mm vs. .80mm

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From SDR to DDRFrom SDR to DDR

Signaling Clocks

Data Strobe

Packages

Pin Count

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Pin Count Versus SDRPin Count Versus SDR

One DQS for 8 DQ (x8, x16 SD)One DQS for 8 DQ (x8, x16 SD)--- or ------ or ---

One DQS for every 32 DQ (x32 SG)One DQS for every 32 DQ (x32 SG) One /CK adjacent to every CKOne /CK adjacent to every CK One VOne VREFREF

Additional VAdditional VDDDDQ, VQ, VSSSS?? DQ/DM/DQS:VDQ/DM/DQS:VDDDDQ:VQ:VSSSS ratio of 4:1:1 ratio of 4:1:1

Total: 5-12 more pinsTotal: 5-12 more pins

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Combined SDR/DDRCombined SDR/DDR

SDRSDR 3.3V I/O supply3.3V I/O supply Single ended CLKSingle ended CLK Echo CLK for readsEcho CLK for reads No write latencyNo write latency CAS latency 2, 3CAS latency 2, 3 Series terminationSeries termination Burst length 1, 2, 4, 8Burst length 1, 2, 4, 8 No reference voltageNo reference voltage

DDRDDR 2.5V I/O supply2.5V I/O supply Differential CK and CKDifferential CK and CK DQS for readsDQS for reads Write latency one clockWrite latency one clock CAS latency 2, 2.5, (3)CAS latency 2, 2.5, (3) Series & parallel term’nSeries & parallel term’n Burst length 2, 4, 8Burst length 2, 4, 8 Reference voltage VReference voltage VREFREF

Combined SDR & DDR controller is a Combined SDR & DDR controller is a reasonable way to minimize risksreasonable way to minimize risks

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Hints for the FutureHints for the Future

You’ll get the fastest designs if you:You’ll get the fastest designs if you: Don’t use command interruptsDon’t use command interrupts Don’t use autoprechargeDon’t use autoprecharge Fixed burst length 4Fixed burst length 4 Programmable drive impedanceProgrammable drive impedance

Weak and strong drivers are standardWeak and strong drivers are standard

Unbroken ground planes & islandsUnbroken ground planes & islands

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Why Not Rambus?Why Not Rambus?

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Compare DDR & RambusCompare DDR & Rambus

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DDR Versus RambusDDR Versus RambusDDRDDR

AdvantageAdvantage $10$10

+ royalties+ royalties 15% 15%

27%27% 33%33% 40%40%

ReasonReason Die, Heat sinks,Die, Heat sinks,

dummy modulesdummy modules 2828 ±10% vs. ±10% vs.

5555 ±15% ±15% Packet protocolPacket protocol Frequency * widthFrequency * width FrequencyFrequency

DIMM cost:DIMM cost:

PCB cost:PCB cost:

Latency:Latency:

Peak BW:Peak BW:

Power:Power:

Email me to get the white paper detailing this analysis

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Rambus Market IssuesRambus Market Issues

High latencyHigh latency Poor fit for UMA graphicsPoor fit for UMA graphics

High powerHigh power Poor fit for mobilePoor fit for mobile

Costly materialsCostly materials Poor fit for cost sensitive systemsPoor fit for cost sensitive systems

Leaves the $2500+ PC market as a fitLeaves the $2500+ PC market as a fit Insufficient volumes to create a marketInsufficient volumes to create a market Other solutions needed anywayOther solutions needed anyway

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SummarySummary

DDR is here todayDDR is here today Double the bandwidthDouble the bandwidth Evolutionary design change over SDREvolutionary design change over SDR Cheaper, faster, & cooler than RambusCheaper, faster, & cooler than Rambus Applies to all market segmentsApplies to all market segments

Industry StandardsIndustry Standards Detailed complete data sheet & modelsDetailed complete data sheet & models Module designs on the webModule designs on the web Visit http://www.jedec.orgVisit http://www.jedec.org

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Call to ActionCall to Action

Watch Watch allall the market trendsthe market trends Let your memory vendor know about Let your memory vendor know about

your commitment to DDRyour commitment to DDR Let the trade press know your choiceLet the trade press know your choice Use smart engineering to push limitsUse smart engineering to push limits Join JEDEC and influence the futureJoin JEDEC and influence the future

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Thank YouThank You