opamp design
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OpAmp Design
The design process involves two distinct activities:
• Architecture Design– Find an architecture already available and
adapt it to present requirements– Create a new architecture that can meet
requirements• Component Design
– Determine transistor sizes– Determine biasing voltages/currents– Design compensation network
All op amps used as feedback amplifier:
If not compensated well, closed-loop can be oscillatory or unstable.damping ratio z ≈ phase margin PM / 100
Value of z: 1 0.7 0.6 0.5 0.4 0.3Overshoot: 0 5% 10% 16% 25% 37%PM in deg: 70 60 50 40 30
UGF: frequency at which gain = 1 or 0 dBPM: phase margin = how much the phase is above critical (-180o) at UGF
Closed-loop is unstable if PM < 0
PM
UGFThis is the loop-return gain when used in closed-loop.
Only in buffer connection this is equal to O.L. gain.
z
GM<0
PM<0
p1 p2 z1
UGF
UGF
p1 p2
PM
GM
p1 p2 z1
UGF
Fully differential amplifiersHave two loops:
DM feedback loopCM feedback loop
• DM loop closed by user, • don’t know feedback at design stage, • needs stability for all user feedback
• CM loop closed by designer, • knows CMFB exactly, • but DM loop and CM loop share significant signal path,
• needs stability for all user DM feedback
Half circuit for DM and half circuit for CM can be used to simplify analysis.
Open loop gain can be analyzed to infer closed loop stability.
Will focus on DM path transfer function
Types of Compensation• Miller - Use of a capacitor feeding back around a
high-gain, inverting stage.– Miller capacitor only– Miller capacitor with an unity-gain buffer to block the
forward path through the compensation capacitor. Can eliminate the RHP zero.
– Miller with a nulling resistor. Similar to Miller but with an added series resistance to gain control over the RHP zero.
• Self compensating - Load capacitor compensates the op amp (later).
• Feedforward - Bypassing a positive gain amplifier resulting in phase lead. Gain can be less than unity.
VsA2A1
Cc
VoutA
Two stage Miller compensation
v1 v2=AVv1
i
i = (v1-v2)/Zf = v1(1-AV)/Zf = v1/{Zf /(1-AV)} = - v2(1-1/AV)/Zf = - v2/{Zf /(1-1/AV)}
i=v1/Z1 i=
-v2/Z2
v1 v2Miller Effect
Vs+A2-A1
C1
A-A2
C2
B Vout
Vs+A2-A1
C1
A-A3
C2
B Vout
Vs-A2-A1
C1
A+A3
C2
B Vout
-AF1
Vs+A2-A1
C1
A-A3
C2
B Vout
-AF1
+AF2
(a) (b)
(c) (d)
(a) Nested Miller Compensation (NMC), (b) Reverse Nested Miller Compensation
(RNMC), (c) Multipath Nested Miller Compensation
(MNMC), (d) Nested Gm-Cc Compensation (NGCC)
Vs+A2-A1
A-A3
Cm
B Vout
+gma
-gmf
Ca
HGB
HSB
Vs+A2-A1
A-A3
Cm
B Vout
gmf
Ca
(a) (b)
(a) Active feedback frequency compensation (AFFC),
(b) Transconductance with capacitance feedback frequency compensation (TCFC)
Single ended and differential have very similarCompensation needs
Vi+
Vo1
VBP
VBN
Vo
I2
Vi-
I1
Vi
Vo1
VBP
VBN
Vo
I2
I1
Not quite
VBP
Vi+ Vi-
VBNVb1
CC CC
Vo+
Vi
Vo1
VBP
Vb1
VoVo-
VBP
Vi+Vi-
VBN
Vb1
CC CC
Vo+Vi
Vo1
VBP
Vb1
VoVo-
If the first stage is cascode, the analysis stay similar
VBPc
VBNc
Composite MOST with large ro
IN- IN+
VDD
CC CC
Vo+ Vo-
Folded cascode same thing, except gm is from a different pair
Vi
Vo1
VBP
Vb1
Vo
Generic representative:
DC gain of first stage:
AV1 = -gm1/(gds2+gds4)= -gm1/(I4(l2+ l4))
DC gain of second stage:
AV2 = -gm6/(gds6+gds7)=- gm6/(I6(l6+ l7))
Total DC gain:
AV = gm1gm6
(gds2+gds4)(gds6+gds7)
GBW = gm1/CC
gm1gm6
I4I6 (l2+ l4)(l6+ l7)AV =
Zf = 1/s(CC+Cgd6) ≈ 1/sCC
When considering p1 (low freq), can ignore CL (including parasitics at vo):
Therefore, AV6 = -gm6/(gds6+gds7)
Z1eq = 1/sCC(1+ gm6/(gds6+gds7))C1eq=CC(1+ gm6/(gds6+gds7))≈CCgm6/(gds6+gds7)
-p1 ≈ w1 ≈ (gds2+gds4)/(C1+C1eq) ≈ (gds2+gds4)/(C1+CCgm6/(gds6+gds7))
≈ (gds2+gds4)(gds6+gds7)/(CCgm6)Note: w1 decreases with increasing CC
At frequencies much higher than w1, gds2
and gds4 can be viewed as open.
M7
C1
CC
CL
vo
Total go at vo:
gds6+gds7+gm6CC
CC+C1
Total C at vo:
CL+C1CC
CC+C1
-p2=w2=CCgm6+(C1+CC)(gds6+gds7)
CL(C1+CC)+CCC1
M6
Note that when CC=0, w2 = gds6+gds7
CL
As CC is increased, w2 increases also.
However, when CC is large, w2 does not increase as much with CC. w2 has a upperlimit given by: gm6+gds6+gds7
CL+C1
Hence, once CC is large, its main effect isto lower w1, and hence lower GBW.
≈ gm6
CL+C1
When CC=C1, w2 ≈ (½gm6+gds6+gds7)/(CL+½C1)≈ gm6/(2CL+C1)
Also note that, in contrast to single stage amplifiers for which increasing CL improvesPM, for the two stage amplifier increasingCL actually reduces w2 and reduces PM.
Hence, needs to design for max CL
There are two RHP zeros:
z1 due to CC and M6
z1 = gm6/(CC+Cgd6) ≈ gm6/CC
z2 due to Cgd2 and M2z2 = gm2/Cgd2 >> z1
z1 significantly affects achievable GBW.
gm6/(CL+C1)f (I6)
z1 ≈ gm6/Cgd6
A0
w2
-90
-180
w1 z2 ≈ gm2/Cgd2
No PM
gm6/(CL+C1)f (I6)
z1 ≈ gm6/Cgd6
A0
w2
-90
-180
w1
z2 ≈ gm2/Cgd2
No PM
z1 ≈ gm6/Cc
gm6/(CL+C1)f (I6)
z1 ≈ gm6/CC
A0
w2
-90
-180 PM
w1
gm1/CC
It is easy to see:PM ≈ 90o – tan-1(UGF/w2) – tan-1(UGF/z1)To have sufficient PM, need UGF < w2
and UGF << z1In such case, UGF ≈ GB ≈ gm1/CC = z1 * gm1/gm6.
PM ≈ 90o – tan-1(GB/w2) – tan-1(GB/z1)
Hence, need: GB < w2GB << z1
PM requirement decides how much lower:
Possible design steps for max GB• For a given CL and Itot• Assume a current share ratio q, i.e.
– I6+I5 = Itot, I5 = qI6 , I1 = I2 = I5/2• Size W6, L6 to achieve max gm6/(CL+Cgs6)
which is > w2– C1 W6*L6, gm6 (W6/L6)0.5
• Size W1, L1 so that gm1 ≈ 0.1gm6– this make z1 ≈ 10*GBW
• Select CC to achieve required PM– by making gm1/CC < 0.5 w2
• Check slew rate: SR = I5/CC• Size M5, M7, M3/4 for current ratio, IMCR, etc
Comment• If we run the same total current Itot through
a single stage common source amplifier made of M6 and M7– Single pole go/CL– Gain gm6/go– Single stage amp GB = gm6/CL >gm6/(CL+C1) > w2 > gm1/CC = GB of two stage amp
• Two stage amp achieves higher gain but speed is much slower!
• Can the single stage speed be recovered?
Other considerations• Output slew rate: SR = I5/CC
• Output swing range: VSS+Vdssat7 to VDD – Vdssat6
• Min ICM: VSS + Vdssat5 + VTN + Von1
• Max ICM: VDD - |VTP| - Von3 + VTN
• Mirror node approx. pole/zero cancellation– Closed-loop pole stuck near by– Can cause slow settling
When vin is short, the D1 node sees a capacitance CM and a conductance of gm3 through the diode con.So: p3 = -gm3/CMWhen vin is float and vo=0. gm4 generate a current in id4=id2=id1. So the total conductance at D1 is gm3 + gm4.So: z3 = -(gm3+gm4)/CM
=2*p3If |p3| << GB, one closed-loop pole stuck nearby, causing slow settling!
Eliminating RHP Zero at gm6/CC
CCdvCC/dt
vg= RZCCdvCC/dt +vcc
icc = vg gm6 = CCdvCC/dt
(gm6RZ-1)CCdvCC/dt + gm6vcc=0
VDD
VSS
M1 M2
M3 M4
VIN
M5
VIN
Vbb
Vxx
Vyy
Vzz
M3c M4c
M2cM1c
Vo1-Vo1+
For the zero at M6 and CC, it becomes
z1 = gm6/[CC(1-gm6Rz)]
So, if Rz = 1/gm6, z1 →
For such Rz, its effect on the p1 node can be ignored so p1 remains as before.
Similarly, p2 does not change very much.
similar design approach.
Realization of Rz
vb
M8
M9
VDD
M8
M9
VDD
VDD
VSS
M1 M2
M3 M4
VIN
M5
VIN
Vbb
Vxx
Vyy
Vzz
M3c M4c
M2cM1c
Vo1-Vo1+
Another choice of Rz is to make z1 cancelw2:
z1=gm6/CC(1-gm6Rz) ≈ - gm6/(CL+C1)
Rz = gm6CC
CC+CL+C1
= gm6
1 (1+ )CC
CL+C1
Let ID8 = aID6, size M6 and M8 so that VSG6 = VSG8
Then VSGz=VSG9
Assume Mz in triodeRz = bz(VSGz – |VT| - VSDz) ≈ bz(VSGz – |VT|) = bz(2ID8/b9)0.5
= bz(2aID6/b6)0.5(b6/b9)0.5
= bz/b6 *b6VON6 *(ab6/b9)0.5
= bz/b6 *1/gm6*(ab6/b9)0.5
Hence need: bz/b6 *(ab6/b9)0.5 =(CC+CL+C1)/CC
gm6/(CL+C1)f (I6)
-z1 ≈
A0
w2
-90
-180 PM
w1
gm1/CC
• With the same CC as before– Z1 cancels p2– P3, z3, z2, not affected– P1 not affected much– Phase margin drop due to p2 and z1 nearly
removed – Overall phase margin greatly improved– Effects of other poles and zero become more
important
• Can we reduce CC and improve GB?
gm6/CL
z1 ≈ p2
A0
w2
-90
-180
w1
z2 ≈ gm2/Cgd2
Operate not on this but on this or this z4 ≈ gm6/Cgd6
pz=-1/RZCC
Increasing GB by using smaller CC
• It is possible to reduce CC to increase GB if z1/p2 pole zero cancellation is achieved– Can extend to gm6/CL– Or even a little bit higher
• But cannot push up too much higher– Other poles, zeros– Imprecise mirror pole/zero cancellation– P2/z1 cancellation– GB cannot be too high relative to these p/z
cancellation• Z2, z4, and pz=-1/RZCC must be much higher
than GB
Possible design steps for max GB• For a given CL and Itot• Assume a current share ratio q, i.e.
– I6+I5 = Itot, I5 = qI6 , I1 = I2 = I5/2• Size W6, L6 to achieve max single stage GB1 =
gm6/(CL+Coutpara)– A good trade off is to size W6 so that Cgs6 ≈ CL– If L_overlap ≈ 5% L6, this makes z4=gm6/Cgd6 ≈ 20*GB1
• Choose GB = aGB1, e.g. 0.5gm6/(CL+C1)• Choose CC to make p2 < GB, e.g. Cc=CL/4, p2 ≈ GB/1.5• Size W1, L1 and adjust q so that gm1/CC ≈ GB
– Make z2=gm2/Cgd2 > (10~20)GB, i.e. Cgd2 < 0.1Cc• Size Mz so that z1 cancels p2• Make sure PM at f=GB is sufficient• Size other transistors so that para |p| > GB/(10~20)• Check slew rate, and size other transistors for ICMR,
OSR, etc
• If CL=C1=4Cc, -p2=gm6/(C1+CL+C1CL/Cc) =1/3 * gm6/(C1+CL)
• -pz=1/RzCc, Rz=1/gm6 *(1+CL/Cc+C1/Cc); -pz=gm6/(Cc+C1+CL) ≈ 3*(-p2)
• Pole/zero cancellation cancelled p2, but introduced a new pole pz at just a few times the p2 frequency, if done right;
For input common mode range• Vi+ = Vi- = Vicm should be allowed to vary
over a large range without causing transistors to go triode
• Vicm_max = (VDD – Vdssat_tail) – VT – Vdssat1
• Vicm_min = Vs of M1c – VT = VG of M1c/2c + Vdssat– VG of M1c must be low– But must be higher than Vo1 – VT1c– Room for Vo1 variation: +- VEB of 2nd stage
• Hence, Vicm_min depends on differential signal– bias M1c adaptively, based on actual input
signal
For Balanced Slew Rate• During output slewing
– All of 1st stage current goes to Cc network– I-Rz drop ≈ constant– 2nd stage Vg variation << Vd or Vo– |Cc d(Vo-Vg)/dt| ≈ |Cc dVo/dt| <= |I1st st |– Slew rate = max |dVo/dt| = I1st st /Cc
• On the otherhand– I2nd st bias - I1st st is to charge CL+Cdbs
• max |dVo/dt| = (I2nd st bias - I1st st )/(CL+Cdbs)• Want (I2nd st bias - I1st st )/(CL+Cdbs) = I1st st /Cc
– I2nd st drive max - I1st st is to discharge CL+Cdbs
VDDAv=gm6/go-p=go/(CL+Cdb)
GB=gm6 /(CL+Cdb)
To maximize GB, size M1 so thatCdb ≈ CL W1 ≈CL/(CjLd) GBmax ≈rt(I*uCox/(2L*CL*Cj*Ld)) =rt(SR*uCox/(2Cj*L*Ld))
This is greater than: gm6’/(CL+C1)≈gm6’/(CL+Cgs)
vin
vo
-vin
-vokk
VDD VDD
gm1vin+gds1vo+gds3vo-kvogm3=0
M1
M3
M2
M4
M5 AV=gm1
gds1+gds3-kgm3
AV= when k = gds1+gds3
gm3
GBW=gm1/Co = GBW of simple CS
VDD
Cascodewith positiveVx feedback
VDD
Cascodewith positiveVo feedback
-kVx
Vx
Vo-kVo
VDD
M2
M1
Vbb
Vin
CL
Rb
connecting D1 to S2cascoding
flip up-downfor source
M2
M1
Vbb
Vin
CL
M4
M3
Vyy
Vxx
VDD
flip left-rightto get thisdifferentialtelescopiccascodedamplifier
VDDVDD
M4
M2
Vbb
Vin-
CL
M8
M6
M3
M1Vin+
CL
M7
M5
Vyy
Vxx
M9add M9 to changegnd to virtual gnd GBW=gm1/Co
How to connectG3 to –Vx, –kVx, or – kVo
M4
M2Vin-
CL
M8
M6
M3
M1Vin+
CL
M7
M5
Vyy
M9
VDD VDD
Vx
Vo
Same GBWGain can be very high
How to connectG3 to –Vx, –kVx, or – kVo
M4
M2Vin-
CL
M8
M6
M3
M1Vin+
CL
M7
M5
Vyy
M9
VDD VDD
Vx
Vo
Same GBWGain can be very high
VDD
Vin+CL
VDD
Vin-
Vbb
folded cascode amp
Same GBW
VDD
Vin+CL
VDD
Vin-
Vbb
How to connect forpositive feedback?
Two-Stage Cascode Architecture• Why Cascode Op Amps?
– Control the frequency behavior– Increase PSRR– Simplifies design
• Where is the Cascode Technique Applied?– First stage -
• Good noise performance• Requires level translation to second stage• Requires Miller compensation
– Second stage -• Self compensating• Reduces the efficiency of the Miller compensation• Increases PSRR
-1/R2C2 -1/R1C2
pole splitting-1
gm2R2R1C1
-gm2C1+C2
gm2Cc
Direct (Miller) Compensation
VsA2A1
Vout VsA2A1
Cc
Vout
Rout
AA
-gm1Vd
R1 C1
V1
-gm2V1
R2
CL
Vout
Cc
Ic=(vout-vs)1/sCc
Figure 7: Small Signal Model for SMC
Figure 6: Two Stage Miller Compensation
Figure 8: Pole Splitting effect of SMC
Transfer Function
Pole/Zero LocationsBandwidth Reduction
RHP Zero
Miller CompensationCompensation capacitor is between the output of the two stage. This results in pole splitting between the dominant and non dominant poleA RHP zero exists at
Due to the feedforward component of the compensation current (Ic)
The second pole exists at
The unity gain frequency is at fun = gm1/2πCc
ISSUES WITH MILLER COMPENSATIONRHP zero reduces the phase margin of the amplifier and thus causes instability
Requires large Cc for stability Slow speed for a given load, CL Poor PSRR
Supply noise feeds through the compensation capacitor to the output
Requires large die area
Miller Compensation with Zero Nulling Resistor
A common method to cancel the RHP zero is by using a series resistor with compensation capacitorThe new location of the zero is
The resistor Rz can be implemented using a transistor in triode region
However introduces a third pole to the system
Need More Stable Op AmpsWe can increase Rz and create a LHP zero to improve phase margin
Becomes difficult to manage the location of the Rz over temperature and process variations
Stability of the op amp is a becoming a problem because of the non-dominant pole associated with the output (f2) is too lowIncrease f2 requires increase of gm of the output stage
Increase areaIncrease output stage current (Id2)
Need a more practical way to Compensate
Avoid using Miller CompensationAvoid connecting a compensation capacitor between two high impedance nodes !Literature has many examples illustrating how to avoid miller connections for high speed
This research develops Indirect Feedback Frequency CompensationA more practical way to compensateFeedback compensation current indirectly using
Common Gate AmplifierCascoded Structures
Improved PSRRSmaller Die Area (Compensation capacitor reduced 4~10 times)Much Faster ..!
VsA2A1 Buffer
Cc
Differential Amplifier Gain Stage Output Buffer
Vout
iccRi
A
Indirect Feedback - History• First proposed by B.K. Ahuja in “AN IMPROVED FREQUENCY COMPENSATION
TECHNIQUE FOR CMOS OPERATIONAL-AMPLIFIERS,” Ieee Journal of Solid-State Circuits, vol. 18, no. 6, pp. 629-633, 1983
• However it is still seldom used in practice ??– Looks very similar to Miller compensation– Prompts most designers to use design strategy for Miller-Rz compensation– However the Indirect Compensation Scheme has much different pole/zero
locations and conditions that need to be satisfied to tap the true potential of the compensation scheme
– Thus this work Provides analytical model/solution for the architectureProposes a design procedure based on the analytical resultsDesign Example using the proposed design procedureSimulation Results show the performance is orders of magnitude higher than miller compensation and far better than state of the art
Indirect Feedback Frequency Compensation
Improvements due to a simple changeThe compensation current is indirectly fedback from low impedance node VA to V1
The RHP pole zero can be eliminated as the feedforward current is blocked by the common gate amplifierNode V1 is now not loaded by the compensation capacitor (as previously) and thus results in a much faster second stage and increased unity gain frequency
AND MUCH MORE ………
M1 M2
M3 M4
M5
M6c
VDD
VSS
Cc
Vin- Vin+
M9
ic
VA
V1
Mb3M7
Mb1
Isupply
Mb2
Mb4
Mb5 Mb6
Vout
Vbb
Small Signal AnalysisCc
gm1Vd
R1 C1
V1 VA
gmcVA
roc
1/gmc RA CA gm5V1 R2CL
Vout
TAKING KCL AT EACHNODE
Simplified Transfer FunctionThe transfer function can be simplified and approximated as:-
The coefficients can be evaluated as
Evaluating the poles and zeros Assuming the pole |p1| >> |p2|, |p3|
The denominator can now be approximated
Real Poles Complex Poles
The third order transfer function as 3 poles and 1 zeroDominant Pole location
Non-dominant Real Poles location Condition For Real Poles
LHP Zero Location
bserving the Pole/Zero Locations
Remains at the same location
Large gmc ?
Improves Phase Margin
Analytical Results Summary
Pole / Zero Location
Real Poles Condition
Quick Facts
Pole p2 moved to much higher frequency
Can use much smaller gm5 Less Power
LHP zero improves the phase margin
Much faster op-amp with lower power and CC
Will EXPLORE more ….
Extended by a factor >1
M1 M2
M3 M4
M5
VDD
VSS
Cc
Vin- Vin+
M9
ic
V1
M7Mb1
Isupply
Mc1 Mc2
Vbb
A
if
Vout
Vcc
Alternative Implementations of Indirect Feedback
The common gate amplifier is embedded in the cascode actionSimilar to the common gate amplifier analyzed in the previous section, the LHP zero and the three poles are given by Equations provided previouslyReduction in Power at cost of Flexibility choosing the transconductance of gmc
M1 M2
M3 M4
M5
VDD
VSS
Cc
Vin- Vin+
M9
ic
V1
M7Mb1
Isupply
Mc1 Mc2
Vbb
A
Vout
Vcc
Similar to cascoded PMOS loads
However additional RHP zero located at:
RHP zeroHigh Frequency
Summarizing the Advantages of Indirect Feedback
Pole splitting can be achieved with a much smaller compensation capacitor (Cc)
Faster Op Amp Much Smaller Area
Lower Value of second stage transconductance (gm5) value required
Lower Power and Less Total Current Required
Improved PSRR
Analytically the reason the non-dominant pole shifted to a higher frequency is because the compensation capacitor now does not load the first stage output.
Pre - Design Procedure Guidelines
To quantify how good of a job our transistor does, we can therefore define the following “figure of merits (FOM)
Tranconductor Efficiency Transit Frequency
Good RegionFor AMI 0.5CNVEB ≈ 0.1-0.2 V
Indirect Feedback Design Procedure Summary
Noise Specification
Slew Rate Specification
Output Swing Specification
Gain-Bandwidth Requirement
Real Poles Requirement
Class A Output Stage DesignBad Output Stage Design
Not Controlling current in the output stage leads to:
Bad input-referred offsetPotential for large power dissipationNot controlling output stage gm (and thus stability)
Class A output stages also suffer from poor slew rate
M1 M2
M3 M4
M5
M6c
VDD
VSS
Cc
Vin- Vin+
M9
ic
VA
V1
Mb3M7
Mb1
Isupply
Mb2
Mb4
Mb5 Mb6
Vout
Vbb
M1 M2
M3 M4
M5
VDD
Cc
V1
Mc1 Mc2Vbb
Vout
SR = inf
CLM1 M2
M3 M4
M5
VDD
Cc
V1
Mc1 Mc2Vbb
Vout
Iss2CL
SR =
CL
Class AB Output Stage Design
Class AB Output StageThe Class AB output stage is realized by have a floating current source biased between the output stages transistors behaving like a push pull:
Slew Rate Improved during dischargingControlled output stage current and gmSlew rate limitation shifted to the compensation capacitor which is small in the proposed compensation scheme and thus achieves much higher slew rate
M1 M2
M3 M4
M5
VDD
Cc
V1
Mc1 Mc2Vbb
Vout
CL
Mpcasc
M6
Mncasc
Iss2
M1 M2
M3 M4
M5
VDD
Cc
V1
Mc1 Mc2Vbb
Vout
CL
Mpcasc
M6
Mncasc
Iss2
Figure of Merit (FOM)
To perform a comparison in terms of speed among the many compensation approaches independently of the particular amplifier topology, design choices, and technology, a figure of merit (FOM) that relates the load capacitance CL, the gain-bandwidth product ωGBW, and the total current consumption of the amplifier I Total has been proposed [ref].
Small Signal FOM
DC Transient FOM
Single Stage Comparison
Total TranscoductanceGm in multi-stage op amp
MHz pfmA
V s pfmA
Design Example – Op Amp Specifications
Op Amp Specification
Supply Voltages ± 1.25 V
Load Capacitance: CL 100 pF
Total Current (max) 30 μA
DC gain: Ao 70 dB
Unity-gain Frequency: fu 2 MHz
Phase Margin: φM 60°
Slew Rate: SR 1 V/μs
Input Common Mode Range: VCMR ± 1 V
Output Swing: Vout {max,min} ± 0.5 V
Input Referred Noise 15 nV/√Hz
Very Low PowerLarge Load
Good Stability
80
Design Example – Device SizingOp Amp Sizing
Transistor Multiplier Size (μm)
M1,22 4.05/0.9
M3,42 3.6/2.4
M56 10.05/1.5
M612 15/1.05
M76 1.65/1.05
M9,b1110 1.65/4.05
Mb11 1.65/4.05
Mb21 1.65/1.05
Mb312 1.65/1.05
Mb41 2.4/1.05
Mb51 12/1.05
Mb612 12/1.05
Mb72 3/1.2
Mb81 1.65/1.05
Mb9,1010 1.95/0.6
Cc- 5 pF
Isupply- 1.25uA
Summary of Simulated ResultsSimulated Results
Specification Specifications Simulation
DC gain: Ao 70 dB 72.45 dB
Unity-Gain Frequency: fu 2 MHz 2.01 MHz
Phase Margin: φM 60° 61.83°
Slew Rate: SR+/- ± 1 V/μs 1/-2.45 V/μs
Input Common Mode Range:
VCMR + / VCMR=
± 0.5 V 1.1/-0.75 V
Output Swing:
Vout MAX/Vout MIN
± 1 V 1.14/-1.1
ITotal 30 μA 30 μA
Power - 75 μW
High Speed
+
Low Power
AC Frequency Response (CL = 100pf)
Bandwidth Extension
Large Signal Transient Response (CL = 100pf)
Sine Wave Transient Response (CL = 100pf)
Robustness of Analytical Results
Small Error
Alternative Indirect Feedback Compensation Scheme Results
Comparison of Alternative Indirect Feedback Compensation
Specification Common Gate Cascode NMOS Cascode
PMOS
DC gain: Ao 72.45 dB 91.1 dB 86.1 dB
Unity-Gain
Frequency: fu
2.01 MHz 1.99 MHz 2.2 MHz
Phase Margin: φM 61.83˚ 61.29˚ 61.7˚
M1 M2
M3 M4
M5
VDD
VSS
Cc
Vin- Vin+
M9
ic
V1
M7Mb1
Isupply
Mc1 Mc2
Vbb
A
Vout
Vcc
M1 M2
M3 M4
M5
VDD
VSS
Cc
Vin- Vin+
M9
ic
V1
M7Mb1
Isupply
Mc1 Mc2
Vbb
A
if
Vout
Vcc
M1 M2
M3 M4
M5
M6c
VDD
VSS
Cc
Vin- Vin+
M9
ic
VA
V1
Mb3M7
Mb1
Isupply
Mb2
Mb4
Mb5 Mb6
Vout
Vbb
Common Gate Cascode PMOSCascode NMOS
Improved gain dueTo cascoding
Performance Comparison to Miller Compensation and Single Stage Amplifiers
M1 M2
M3 M4
M5
M6c
VDD
VSS
Cc
Vin- Vin+
M9
ic
VA
V1
Mb3M7
Mb1
Isupply
Mb2
Mb4
Mb5 Mb6
Vout
Vbb
Indirect Feedback
Comparison with Miller Compensation and Single Stage Amplifiers
Specification Single Stage Single Miler
Compensation
Indirect Feedback
Compensation
DC gain: Ao 36.93 dB 70.45 dB 72.45
Unity-Gain
Frequency: fu
1.098 MHz 293.1 KHz 2.01 MHz
Phase Margin: φM 90˚ 60.29˚ 61.7˚
Cc Required -NA- 35 pF 5 pF
Miller CompensationSingle Stage
Winner
Performance Comparison to Literature
Conference Author Total Id (mA) GBW (MHz) Slew Rate (V/μs) CL (pf) IFOMs (MHz•pf)/mA IFOML ((V/μs)•pf)/mA
ECCTD -2007 [25] Pennisi 1.950 700.00 2000.00 0.3 107.69 307.69
TCAS - 2005 [24] Mahattanakul 0.076 5.00 6.00 5 330.69 396.83
WESEAS -2006 [26] Franz 12.800 1060.00 863.00 4 331.25 269.69
JCSC 2008 [27] Hamed 7.667 300.00 -NA- 8.5 332.61 -NA-
JSSC - 1995 [28] Kovacs 0.110 4.50 -NA- 10 409.09 -NA-
AICSP - 2009 [29] Pugliese 0.318 27.10 25.00 10 851.71 785.71
TCAS - 1997 [6] Palumbo 0.158 28.00 6.59 5 886.08 208.54
E-Letter 2007 [30] Pugliese 0.032 6.70 1.00 10 2125.96 317.31
ECCTD - 2005 [31] Loikkanen 0.210 6.80 6.40 200 6476.19 6095.24
TCAS - 2008 [18] Palumbo 0.150 9.89 -NA- 100 6593.33 -NA-
This Work - Cascode NMOS Kumar 0.025 1.99 1.50 100 7960.00 6000.00
This Work - Common Gate Kumar 0.025 2.00 2.00 100 8000.00 8000.00This Work - Cascode PMOS Kumar 0.025 2.20 2.00 100 8800.00 8000.00
Floor Planning
Diff Input
TAIL CURRENT
PMOS OUT
CURRENT SOURCE CG
NMOS OUT
RESISTOR AVSS
AVDD
BIAS PMOS
BIAS NMOS
SIGNAL PATH
COMPENSATION CAPACITOR
PMOS LOAD
PMOS LOAD
CMFB PMOS CG LOAD
CG AMPLIFIER
SIGNAL PATH
SIGNAL PATHSIGNAL PATH
FLOOR PLANNING
INP
INNVOUT
Considerations Orientation of Transistors Power Distribution Routing Ease Current Mirror Matching
Final Layout
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