pipelines

ALU IM Reg DM Reg

IM

Graphical Pipeline Representation

Instr.

Order

Time (clock cycles)

Load

Add

Store

Sub

OrALU IM Reg DM Reg

ALU IM Reg DM Reg

ALUReg DM Reg

ALU IM Reg DM Reg

(right half highlighted means read, left half write)

Example: Single-cycle vs. Pipelined

ALU IM Reg DM Reg

ALU IM Reg DM Reg

ALU IM Reg DM RegALU IM Reg DM Reg

2 4 6 8 10 12 14 16 18 20

time

ALU IM Reg DM Reg

ALU IM Reg

1

2

3

1

2

3

Advanced Architectural Concepts

• Can we achieve CPI < 1? (i.e., can we have IPC > 1?) State-of-the-Art Microprocessor

• “Superscalar” execution or Instruction Level Parallelism (ILP)

“Deeper Pipeline => Dynamic Branch Prediction => Speculation => Recovery

• “Out-of-order” Execution => Instruction Window and Prefetch => Reorder Buffers

• “VLIW” Ex: Intel/HP Titanium

Instruction Level Parallelism (ILP) IPC > 1

IFtch Dcd Exec Mem WB

Mem

Dcd Exec Mem WB

IFtch Dcd Exec Mem WB

IFtch Dcd Exec Mem WB

IFtch Dcd Exec Mem WB

Program Flow ILP = 2

Time

IFtch Dcd Exec WB

IFetch

EX: Pentium, SPARC, MIPS 10000, IBM Power PC

Very Large Instruction Word (VLIW) IPC > 1

IFtch Dcd Exec Mem WBExec

IFtch Dcd Exec Mem WBExec

IFtch Dcd Exec Mem WB

Program Flow EX: Itanium

Time

Exec