principles of digital circuits jehan-françois pâris jparis@uh.edu

PRINCIPLES OF DIGITAL CIRCUITS

Jehan-François Pârisjparis@uh.edu

Chapter Organization

• Combinatorial circuits– Boolean algebra– Logical gates used to implement them

• Sequential circuits– Finite-state machines– Flip-flops and other memory technologies– Implementation

Importance

• Up to the 80’s, computers were built of discrete components– Computer architects were building their

computers using gates, flip-flops, …• Logical circuitry is now hidden inside

increasingly complex chips– Principles remain the same

COMBINATORIAL CIRCUITS

Outline

• Boolean Operators:– AND, OR, NOT, XOR, NAND, NOR

• Boolean Expressions– Identities– Simplification

• Algebraic methods• Karnaugh maps

Boolean quantities

• Can only have two values– TRUE or FALSE (logical expressions)– 0 or 1 (digital circuit design)

Boolean operations (I)• AND:

– True if both operands are true– Represented by a . sign (often omitted)

A B AB

0 0 0

0 1 0

1 0 0

1 1 1

This is called a truth table

Boolean operations (II)• OR:

– True unless both operands are false– Represented by a + sign

A B A+B

0 0 0

0 1 1

1 0 1

1 1 1

Boolean operations (III)• NOT:

– True if operand is false– Represented by a macron as in Ā or a prime

A A’

0 1

1 0

Boolean operations (IV)• Equality/Mutual Implication:

– True when both operands are equal– Represented by a sign

A B AB

0 0 1

0 1 0

1 0 0

1 1 1

Boolean operations (V)• Exclusive OR (XOR):

– True when operands are not equal– Represented by a sign

A B AB

0 0 0

0 1 1

1 0 1

1 1 0

Boolean operations (VI)• Not AND (NAND):

– True unless both operands are true

A B A NAND B0 0 1

0 1 1

1 0 1

1 1 0

Boolean operations (VII)• Not OR (NOR):

– True if both operands are false

A B A NOR B0 0 1

0 1 0

1 0 0

1 1 0

Notes

• XOR is used for – Generating parity bits– Hardware hashing

• NOR and NAND are used because they have very efficient hardware implementation

Useful identities (I)

• 1 + A = 1• 0 . A = 0• A + A’ = 1• A.A’ = 0• A(B + C) =AB + AC• (AB)’ = A’ + B’• (A+B)’ = (A’)(B’)

Useful identities (II)

– Let us show that (A+B)’ = A’B’

A B A’ B’ A’B’ A+B (A+B)’

0 0 1 1 1

0 1 1 0 0

1 0 0 1 0

1 1 0 0 0

Useful identities (II)

– Let us show that (A+B)’ = A’B’

A B A’ B’ A’B’ A+B (A+B)’

0 0 1 1 1 0 1

0 1 1 0 0 1 0

1 0 0 1 0 1 0

1 1 0 0 0 1 0

Universal set of operations (I)

• A set of operations is said to be universal iff any function can be described by using that set of operations alone

• Claim:AND, OR and NOT constitute a universal set

Universal set of operations (II)

• Proof:We will show that– A B = AB + A’B’– A B = A’B + AB’– A NAND B = (AB)’– A NOR B= (A + B)’– …

Universal set of operations (III)

– Let us show that A B = A’B + AB’

A B A’B AB’ A’B + AB’ AB

0 0

0 1

1 0

1 1

Universal set of operations (III)

– Let us show that A B = A’B + AB’

A B A’B AB’ A’B + AB’ AB

0 0 0

0 1 1

1 0 0

1 1 0

Universal set of operations (III)

– Let us show that A B = A’B + AB’

A B A’B AB’ A’B + AB’ AB

0 0 0 0

0 1 1 0

1 0 0 1

1 1 0 0

Universal set of operations (III)

– Let us show that A B = A’B + AB’

A B A’B AB’ A’B + AB’ AB

0 0 0 0

0 1 1 0

1 0 0 1

1 1 0 0

Universal set of operations (III)

– Let us show that A B = A’B + AB’

A B A’B AB’ A’B + AB’ AB

0 0 0 0 0

0 1 1 0 1

1 0 0 1 1

1 1 0 0 0

Universal set of operations (III)

– Let us show that A B = A’B + AB’

A B A’B AB’ A’B + AB’ AB

0 0 0 0 0 0

0 1 1 0 1 1

1 0 0 1 1 1

1 1 0 0 0 0

Universal set of operations (IV)

• Can simulate NOT with either NAND or NOR: • A NAND A = A NOR A = A’

Universal set of operations (V)

• Can simulate AND with either NAND or NOR:

• (A NAND B) NAND (A NAND B) =

((AB)’)’ = AB

• (A NOR A) NOR (B NOR B) =

( A’ + B’)’ = ((AB)’)’ = AB

Universal set of operations (VI)

• Can simulate OR with either NAND or NOR

• (A NAND A) NAND (B NAND B) =(A’B’)’ = ((A +B)’)’ = A + B

• (A NOR B) NOR (A NOR B) =((A +B)’)’ = A + B

• Both NOR alone and NAND alone form universal sets of operations

Exercise

• Construct an exclusive or usinga) only NAND operationsb) only NOR operations

Solution using NANDs

• Will start top down– AB = AB' + A'B

= (AB' NAND AB') NAND (AB' NAND AB')

where • AB' = (A NAND A) NAND B • A'B = A NAND (B NAND B)

Easier to draw it

and or not

nand nor xor

Easier to draw it (II)

(F NAND F) NAND (G NAND G) =F' NAND G' = F + G

GG'

F'(FG')' =F + GF

Easier to draw it (III)

(A NAND B) NAND (A NAND B) =(AB)' NAND (AB)' = AB

A

B

(AB)' (AB)'' = AB

Easier to draw it (IV)

(A NAND (BNAND B) NAND ( same) =(AB)' NAND (AB)' = AB

(AB')' = A'+B (A'+B)' = AB'A

BB'

(A'+B)' = AB'A

B

Easier to draw it (V)

(A NAND (BNAND B) NAND ( same) =(AB)' NAND (AB)' = AB

(A'B)' = A+B' (A+B')' = A'BA

B

A'

Putting it together

AB'

A

B A'+B

A

B

A+B' A'B AB'

A'B

Output is ((A'B) (B'A))' = AB'+A'B

Simplifying (I)

A

B A'+B

A

B

A+B'

Output is ((A'B) (B'A))' = AB'+A'B

X XX X

Simplifying (II)

A

B

A

B

(AB')'

(A'B)'

Output is ((A'B)' (B'A)')' = (AB')''+(A'B)'' = AB'+A'B

A'

B'

AB'+A'B

Expression simplification (I)

• My other class is full• I could make exceptions for

– All PhD students because the course is one of their core courses

– All MS students who graduate this semester because they might need the course

Expression simplification (II)

• I have two Boolean variables– D true if the student is a PhD student and

false otherwise– T if student completes his/her last semester

• We can assume that all non-PhD students are MS students– Course restricted to graduate students

Expression simplification (III)

• Rules can be expressed by Boolean expressionD +D’T

• Can I simplify this expression?– D + D’T = D (1 + T) + D’T

= D + DT + D’T = D + (D + D’)T = D + T

– One operation instead of three

Karnaugh maps (I)

• Graphical method to represent truth tables of Boolean expressions with up to four variables

• Our example becomes

T ' T

D’ 1

D 1 1

Karnaugh maps (II)

• Can identify rectangles corresponding to variables or AND “products”

• Form OR “sum” of these products

T ‘ T

D’ 1

D 1 1

Karnaugh maps (III)

• Want to simplify AB’C + ABC’ + A(BC)’= AB’C + ABC’ +A(B’ + C’)

B’C’ B’C BC BC’

A’ 0 0 0 0

A 1 1 0 1

Must use the sequence B’C’, B’C, BC, BC’

Karnaugh maps (III)

• Solution is AB’ + AC’ = A(B’ + C’)– Observe wrap-around for product AC’

B’C’ B’C BC BC’

A’ 0 0 0 0

A 1 1 0 1

Karnaugh maps (IV)

• Can have Karnaugh maps with four variables

C'D' C'D CD CD'

A’B’ 0 0 1 1

A’B 0 0 0 0

AB 0 0 0 0

AB’ 1 1 1 1

Karnaugh maps (V)

C’D’ C’D CD CD’

A’B’ 0 0 1 1

A’B 0 0 0 0

AB 0 0 0 0

AB’ 1 1 1 1

Karnaugh maps (VI)

• Solution is AB’ + B’C = B’(A +C)

C’D’ C’D CD CD’

A’B’ 0 0 1 1

A’B 0 0 0 0

AB 0 0 0 0

AB’ 1 1 1 1

Exercise (I)

• Simplify the expressionAC + (A’ + B) (C + D) + BD

Exercise (II)

Algebraic Solution:AC + (A’ + B) (C + D) + BD’ =AC + A’C + A’D + BC + BD + BD’ =C +A'D + BC + B =C + A’D + B

Exercise (III)

• Karnaugh Map:AC + (A’ + B) (C + D) + BD’ =C + A’D + B

C’D’ C’D CD CD’

A’B’ 0 1 1 1

A’B 1 1 1 1

AB 1 1 1 1

AB’ 0 0 1 1

Half adder (I)

• Implements Boolean addition without a carry from a lesser significant bit

• Binary addition table is very simple

+ 0 1

0 0 1

1 1 10

Half adder (II)

• Karnaugh map for sum bit

• Karnaugh map for carry bit

+ 0 1

0 0 1

1 1 0

+ 0 1

0 0 0

1 0 1

Half adder (IIII)

• Two outputs:– The sum S = x y– The carry C = xy

Half adder (IV)

• An implementation only using AND, OR and NOT gates– C = xy– S = x y

= x’y + xy’ + x’x + y’y = x’(x + y) + y’(x + y) = (x’ + y’)(x + y) = (xy)’(x + y)

Half adder

Carry =XY

Sum

X

XY

Y

XY

X'+Y'

Sum = (X'+Y')(X+ Y) = X'X + X'Y + Y'X + Y'Y

Full adder (I)

• We add the carry z from a less significant bit position

C'S' C'S CS'

+ 00 01 10 -

0 00 01 10 -

1 01 10 11 -

Outputs from half adder

Carry z

Full adder (II)• New sum:

C'S' C'S CS'

00 01 10 -

0 0 1 0 -

1 1 0 1 -

Outputs from half adder

Carry z

Full adder (II)• Checkerboard pattern indicates an XOR

C'S' C'S CS'

00 01 10 -

0 00 1 00 -

1 1 00 1 -

Outputs from half adder

Carry z

Full adder (III)• New carry:

C'S' C'S CS'

00 01 10 -

0 0 0 1 -

1 0 1 1 -

Outputs from half adder

Carry z

Full adder (IV)

• Define– SH = x y

– CH = xy

• With the carry z– New sum S = SH z

– New carry C = CH + SH z

for the half adder

Full adder (V)

• We can build a full adder using two half adders and an OR gate

Full adder (VI)

• A simpler diagram

Half adder Half adderxy

z

S

C

We treat the half adder as a black box.

Multiplexers (I)

• A multiplexer has– 2n input lines numbered 0 to 2n - 1– n select lines– one output

• Values of n select lines specify which input line is rolled to output

Four-input multiplexer (I)

Four-input multiplexer (II)

Decoders

• A decoder has– n input lines– 2n output lines numbered 0 to 2n – 1

• Values of n input line specify which output line is on

Two-input decoder

A generic decoder

Programmable Logic Arrays

• A PLA has– one selectable NOT gate for each input line– a set of programmable AND gate planes– a set of programmable OR gate planes

• Can represent any Boolean expression insum of product form:

ABC’ + AD + A’ED

Programmable Logic ArraysThe squiggly connectionscan be turnedon or off when the array isprogrammed

X states (I)• Sometimes we know that some input

combinations will never happen– Represented on a Karnaugh map by a X state

B’C’ B’C BC BC’

A’ X X 0 0

A 1 1 0 1

X states (II)• Can be assigned either 0 or 1• Expression simplifies in

B’+ AC’

B’C’ B’C BC BC’

A’ X=1 X=1 X=0 0

A 1 1 0 1

SEQUENTIAL CIRCUITS

Definition

• A sequential circuit is a circuit whose response depends on its past inputs– After n attempts to enter a password, the

systems stops asking the user for the correct password

– “Three strikes and you are out” laws• A sequential circuit has a state and requires

some memory capability to store that state

Overall organization

Input OutputSequential

Circuit

Feedback

Memory

Classes of sequential circuits

• Synchronous sequential circuits:– Can only modify their state when a clock pulse

is applied• Asynchronous sequential circuits:

– Can modify their state at any time– Feedback from memory can cause instabilities– Much less used

S-R Latch

• Two inputs– S for set (to one)– R for reset (to zero)

• Two complementary outputs Q and Q’.– Input S sets Q and resets Q’– Input R resets Q and sets Q’

S-R latch using NOR gates

Q’

QR

S

The lines that cross in the middle do not touch each other

How it works (I)

• When S = R = 0– If Q =1

• Q’ remains reset• Q remains set

– If Q =0• Q’ remains set• Q remains reset

How it works (II)

• When S = 1 and R = 0– If Q =1

• Q’ remains reset• Q remains set

– If Q =0• S=1 resets Q’• Q’ sets Q

How it works (III)

• When S = 0 and R = 1– If Q =1

• R = 1 resets Q• Q = 0 sets Q’

– If Q =0• Q remains reset• Q’ remains set

How it works (IV)

• When S = R = 1– Nothing works!– Cannot allow it to happen

S-R latch using NAND gates

Q

Q’R’

S’

Nothing happens as long as R = S = 1

Q and Q’have beenswitched

How it works

• When S’ = 0– Q NAND gate outputs 1– Both inputs of Q’ NAND gates are 1– Q’ NAND gate outputs 0

• When R’ = 0– Q’ NAND gate outputs 1– Both inputs of Q NAND gates are 1– Q NAND gate outputs 0

Clock controlled S-R latch (I)

• Will add additional clock input– Nothing can happen without a clock pulse

Clock-controlled S-R latch (II)

Q’

QR

S

Clock

Clock-controlled S-R latch (III)

Q

Q’R

S

Clock Q and Q’ have been switched

How it works• When S = 1 and Clock = 1

– S input NAND gate outputs 0– Q NAND gate outputs 1– Both inputs of Q’ NAND gates are 1– Q’ NAND gate outputs 0

• When R = 1 and Clock = 1– R input NAND gate outputs 0– Q’ NAND gate outputs 1– Both inputs of Q NAND gates are 1– Q NAND gate outputs 0

Clock-controlled D latch (I)

• Has one single input– S-R latch such that S = R’

• When clock pulse is on– D = 0 resets Q and sets Q’– D = 1 sets Q and resets Q’

• D stands for Delay

Clock-controlled D latch (II)

Q

Q’

D

Clock

D latch (III)

D

Clock

Q

Q’

Clock-controlled J-K latch (I)

• Avoid the problems of S-R latches• When clock pulse is on

– J = K = 0 does nothing– J = 1 and K = 0 sets Q and resets Q’– J = 0 and K = 1 resets Q and sets Q’– J = K = 1 toggles the latch

• Values of Q and Q’ change from 0 to 1 and from 1 to 0

Clock-controlled J-K latch (II)

Q’

QK

J

Clock

Clock-controlled J-K latch (III)

Q

Q’K

J

Clock

How it works (I)

• When J = 1, Q’ = 1 and Clock = 1– J NAND gate outputs 0– Q NAND gate outputs 1– Q’ NAND gate outputs 0

• When J = 1, Q’ = 0 and Clock = 1– J input has no effect

How it works (II)

• When K = 1, Q = 1 and Clock = 1– K NAND gate outputs 0– Q’ NAND gate outputs 1– Q NAND gate outputs 0

• When K = 1, Q = 0 and Clock = 1– J input has no effect

• When J = K = 1 and Clock = 1– Either Q = 0 disables the effect of having K = 1 or

Q’ = 0 disables the effect of having J = 1

Clock-controlled J-K latch (IV)

J

K

Clock

Q

Q’

Clock-controlled T latch (I)

• Has a single input– J-K latch such that J=K

• When clock pulse is on– T = 0 keeps current values of Q and Q’

unchanged– T = 1 toggles the latch

• Values of Q and Q’ change from 0 to 1 and from 1 to 0

Clock-controlled T latch (II)

T

Clock

Q

Q’

J-Klatch

Requires very short clock pulses!

Edge-triggered flipflops (I)

• If the clock pulse is not very short,J-K and T flipflops may change state twice during a clock pulse

Edge-triggered flipflops (II)

• Solution is to restrict change to either raising edge (a) or failing edge (b) of clock pulse– Use a short pulse generator

(a) (b)

Short-pulse generator (I)

• Generator takes advantage of switching delay of NOT gate– When input goes from 0 to 1,

output of NOT gate remains at 1 for a short while

Short-pulse generator (II)

Input

Output

J-K flip flop

J

K

Clock Q

Q’

Conventional representation

J

K

Q

Q’

Clock

Failing edge-triggered JK flipflop

J

K

Q

Q’

Clock

Notes

• There are many many different flipflops and latches

• Not all authors agree that – Latches are always level-triggered– Flipflops are always edge-triggered

Sequential circuit synthesis

• Multistep process:– Construct a conceptual representation of

circuit• Finite-state machine

– Assign flipflop values to states– Build Karnaugh maps– Select flipflop types

Example

• A very simple binary counter– Counts input pulses– Goes through cycle

• 00 01 10 11 00 …• Memory has four states

• Good prototype of bigger counters

Step 1: The finite-state machine

00

10

01

111/110/11

1/01

1/101/11

0/10

0/010/00

Note

• Each transition is labeled with a pair i/o where– i are the input value(s) triggering the transition– o are the output value(s) associated with the

transition• Our counter has no outputs other than the

values of its flipflops

Step 2: Karnaugh maps (I)

• Truth table for least significant bit Y

• Flips when A = 1

X’Y’ X’Y XY XY’

A’ 0 1 1 0

A 1 0 0 1

Step 2: Karnaugh maps (I)

• Truth table for least significant bit Y

• Flips when A = 1

X’Y’ X’Y XY XY’

A’ 0 1 1 0

A 1 0 0 1

Step 2: Karnaugh maps (II)

• Solution is

Y = A’Y + AY’

• Could use a D flipflop and an XOR• Better to use a T flipflop alone

Step 2: Karnaugh maps (III)

• Truth table for most significant bit X

• Flips when A = Y = 1

X’Y’ X’Y XY XY’

A’ 0 0 1 1

A 0 1 0 1

Step 2: Karnaugh maps (III)

• Truth table for most significant bit X

• Flips when A = Y = 1

X’Y’ X’Y XY XY’

A’ 0 0 1 1

A 0 1 0 1

Step 2: Karnaugh maps (IV)

• Solution is

X = A’Y + AX’Y + XY’

• Will use a T flipflop and an AND

Step 3: The circuit

T Q’

QX

Clock

TQ’

QY

Clock

Notes

• In general, the assignment of states to flipflops is not as trivial– Start the state-transition diagram of the finite

state machine with symbolic names for the states

– Can often reduce the number of states by merging equivalent states

Debouncing switches

• Opening or closing an electrical connection cause transient signals– Interpreted by gates as multiple pulses

• Must debounce each switch

REVIEW PROBLEMS

Combinatorial circuits

• Simplify the following expression

AB + BC + CA + A’C’

Solution

• AB + BC + CA + A’C’ =AC +B +A’C’

B’C’ B’C BC BC’

A’ 1 0 1 1

A 0 1 1 1

Combinatorial circuits

• Represent the expression

AB + AC’

only using NAND gates

Solution

• AB + AC’= ((AB)’ (AC’)’)’

• First NAND computes X = (AB)’• Second NAND computes Y = C’• Third NAND computes Z = (AY)’• Fourth NAND computes (XZ)’ = X’ + Z’

Combinatorial circuits

• Represent the expression

(A + B’)(A’ + C)

using a PLA

Solution

• Must convert (A + B’)(A’ + C)into a sum of products

(A + B’)(A’ + C) = AA’ + AC + B’A’ + B’C = AC + B’A’ + B’C

Sequential circuits

• Draw the state transition diagram for a sequential circuit outputting 1 if it has received an odd number of 1 inputs and 0 otherwise

Solution (I)

1/1

0 1

0/0 0/1

1/0

Solution (II)

• Implementing the circuit will only requirea T flipflop

Sequential circuits

• Build a T flipflop using – A D flipflops– Some gates

Solution

• P is previous state of flipflopA is current input

• Solution is A’P+ AP’ (one XOR)

P’ P

A’ 0 1

A 1 0