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SOFTWARE ENGINEER

Programmable Data Plane at Terabit Speeds

Milad Sharif

AUGUST 2018

PISA: Protocol Independent Switch Architecture

PISA − Block Diagram

3

Match+ActionStage

Memory ALU

ProgrammableParser ProgrammableMatch-ActionPipeline

PISA − Match-Action Unit

• Multiple simultaneous lookups and actions can be supported

Sequential Execution(Matchdependency)

Memory ALU Memory ALU

Memory ALU

Memory ALU

Staggered Execution(Actiondependency)

Memory ALU

Memory ALU

Parallel Execution(Nodependency)

Introducing Tofino

Four Match+Action Pipelines• Fully programmable PISA Embodiment • Single Shared Packet Buffer• 16nm technology

Port Configurations• 260 × 25 SerDes, support 1G, 10G, 25G, 40G, 50G, and 100G ports

CPU Interfaces• PCIe: Gen3 ×4/ ×2/ ×1• Dedicated 100GE port

6.5Tb/s TofinoTM− Overview

6

Match+ActionPipeline2

Match+ActionPipeline3

Match+ActionPipeline1

Match+ActionPipeline0

SharedPacketBuffer+TM

MAC+SerialI/O

Tofino − Simplified Block Diagram

7

pipe0

RxMACs10/25/40/50/100

IngressPipeline

Tx MAC10/25/40/50/100

Control&configuration

Reset/Clocks PCIe CPUMAC DMAengines

pipe1

RxMACs10/25/40/50/100

IngressPipeline

Tx MAC10/25/40/50/100

pipe2

RxMACs10/25/40/50/100

IngressPipeline

Tx MAC10/25/40/50/100

pipe3

RxMACs10/25/40/50/100

IngressPipeline

Tx MAC10/25/40/50/100

TrafficManager

EgressPipeline

EgressPipeline

EgressPipeline

EgressPipeline

Fully-Programmable Parser

8

Eth.

IPv4 IPv6

UDP TCP

Protocol==0x11 Protocol==0x06

FromMAC

TCAM SRAM

shiftcontrol

MatchFieldselection

NextstateNextstate

InputShiftRegister

MatchFieldExtract

Data

State

OutputField

Extractor

Action

PacketHeaderVector

• A set of uniform containers that carry the headers and metadata. along the pipeline

• Fields can be packed into any container or their combination.

• Packing is decided by PHV Allocation pass in the compiler.

Packet Header Vector (PHV)

9

8-bitwords

8

8

16-bitwords

16

16

32

32

32-bitwords

Match−Action Unit

MatchRAM/TCAM

Key

×Xbar

#

ActionRAM

ALUs:Meters,Statistisc,Stateful

Delay

Instr.RAM

InstructionAddress

OperandData

PHV

Match−Action Pipeline

MatchActionUnit

Parser

Fullpacket

MatchActionUnit

MatchActionUnit

MatchActionUnit

Deparser

Match−Action Pipeline

Parser

Fullpacket

uRPF

IPv4 IPv6

ACL

Deparser

ACL

IPv4

IPv6

• Multiple small tables per stage

• Large tables spread over multiple stages

Unified Match−Action Pipeline

MAU0PHV

MAUnPHV

CombinedIngress/EgressMatch-ActionPipeline

IngressParser

IngressPacketbody

QueuesAndPacketBuffers

IngressDeparser

IngressPacket

ConstructorIngress

Buffer

MAC

MAC

MAC

MAC

Unified Match−Action Pipeline

MAU0PHV

MAUnPHV MAC

MAC

MAC

MAC

CombinedIngress/EgressMatch-ActionPipeline

IngressPacketbody

EgressPacketbody

Egressheader

MAC

MAC

MAC

MAC

QueuesAndPacketBuffersIn

gress

Buffer

IngressDeparser

IngressPacket

Constructor

EgressDeparser

EgressPacket

Constructor

IngressParser

EgressDeparser

Unified Match−Action Pipeline

RecirculationBuffer(PacketReference,Metadata)

MAU0PHV

MAUnPHV MAC

MAC

MAC

MAC

CombinedIngress/EgressMatch-ActionPipeline

IngressPacketbody

EgressPacketbody

Egressheader

MAC

MAC

MAC

MAC

QueuesAndPacketBuffersIn

gress

Buffer

IngressDeparser

IngressPacket

Constructor

EgressDeparser

EgressPacket

Constructor

IngressParser

EgressDeparser

Programming Tofino

Tofino Architecture

• Data plane interfaces

• Intrinsic Metadata ingress_mac_tstamp − ingress timestamp assigned by MACucast_egress_port − output port

• Tofino-specific ExternRegisters, Counters, Meters, Filters, etc.

/// Registerextern Register<T, I> {/// Instantiate an array of <size> registers. /// The initial value is undefined.

Register(bit<32> size);

/// Initialize an array of <size> registers and set /// their value to initial_value.

Register(bit<32> size, T initial_value);

/// Return the value of register at specified index. T read(in I index);

/// Write value to register at specified index.void write(in I index, in T value);

}

Runtime Configuration

ExternLibraries

Arch.Definition

P416CoreLibrary

Target-SpecificConfiguration

BF-Runtimeinfo

Backend

Fronend

P4Compiler

Application

BF-RuntimeAPIs

V1Model

ProvidedbyBarefootNetworks

ASICdriverPSA

P4ArchitectureModel

UserDefined

PacketTestFramework

P4Visualization

P4Program

ASICModel/// Indexed counter with `size’ independent

/// counter values. extern Counter<W, I> { /// Constructor /// @type_param W : width of the counter value. /// @type_param I : width of the counter index. /// @param type : counter type. Packet an byte/// counters are supported.

Counter(bit<32> size, CounterType_t type);

/// Increment the counter value. /// @param index: index of the counter to be /// incremented.

void count(in I index); }

Multi−Pipeline configuration

ExternLibraries

Arch.Definition

P416CoreLibrary

App1.p4 P4Compiler

App2.p4 P4CompilerPipeline

Configuration

PipelineConfiguration

MSHARIF@BAREFOOTNETWORKS.COM

Thank You

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