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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 45, NO. 8, AUGUST 1998 849
Resonance and Damping in CMOS Circuitswith On-Chip Decoupling Capacitance
Patrik Larsson
AbstractDesign of on-chip decoupling capacitance and mod-eling of resonance effects in the power supply network of CMOSintegrated circuits is addressed. The modeling is based on math-ematical limits proving that damping will be low, resulting inresonance unless careful design is used. Design strategies thatreduce resonance are discussed. It is shown that an optimalparasitic resistor in series with the decoupling capacitor gives amaximum damping factor of 0.5 and practical values are withinthe range 0.30.4. Examples of digital circuits show that properdesign of on-chip decoupling capacitance may reduce the numberof bonding wires by an order of magnitude. The modeling anddesign suggestions are also applicable to mixed-mode circuits. Inparticular, sampled analog networks benefit with a potentially
higher sampling rate if enhanced damping is introduced duringdesign.
Index Terms Noise, resonance, circuits.
I. INTRODUCTION
SCALING of MOS technologies gives higher speed andreduced area. On the other hand, scaling imposes higherdemands on material, packaging, and interconnections. One
example is voltage fluctuations in the power distribution
network [1], [2], mainly caused by inductors associated with
the package. Assuming constant field scaling, the signal-to-
noise ratio (SNR) due to noise scales as when
scaling the process by Keeping the supply voltageconstant, the SNR scales as , indicating severe limitations
on the package [3]. In recent years, techniques to reduce noise
have gained interest. A discrete capacitor inside a package [4]
and on-chip decoupling capacitance [5], [6] have been proven
efficient to reduce noise.
Adding decoupling capacitance on a chip may give reso-
nance oscillations in the power distribution network [1]. This
may cause noise accumulation with unexpectedly large noise
amplitude. Resonance has been discussed in various contexts,
as, for example, capacitive decoupling [4], wafer-scale power
distribution [7], simultaneous switching of output buffers
[8][10], testing [11], [12], and board-level analysis [13]. In
[14] and [15] detailed simulation models of complex packagesand circuits were matched to measured data. Measurements
of specific packaged devices were presented, whereas this
paper is focused on predictive modeling of general circuits
and design suggestions to control resonance during design of
integrated CMOS circuits.
Manuscript received September 3, 1996; revised August 21, 1997. Thispaper was recommended by Associate Editor T. G. Noll.
The author is with Bell Laboratories, Lucent Technologies, Holmdel, NJ07733 USA (e-mail: pal@dnrc.bell-labs.com).
Publisher Item Identifier S 1057-7122(98)05539-1.
The paper is organized in three parts. The first part derives
a model predicting the resonance frequency and the damping
factor of a general CMOS circuit. This model is used in
the second part that proposes design techniques that increase
damping to avoid resonance. Design examples that show the
practical use of the modeling and proposed design suggestions
are given in the third part.
II. THE NEED FOR DAMPING
Fig. 1(a) shows a model of a digital CMOS circuit including
inductive power supply connections , on-chip decouplingcapacitance , and logic gates Later, it is shown
that the circuit in Fig. 1(a) can be approximated by the
circuit in Fig. 1(b), which acts as a resonance circuit since the
dc supply is ideally a short for ac signals [1]. The resonance
frequency and damping factor are expressed in Fig.
1(b). Modeling the dc source as an ideal short might seem
a crude model. However, often low-impedance decoupling
capacitors are connected close to the package [1], [2], which
are easily included in the model in Fig. 1(b) by replacing the
assumed short with their impedance [14]. The inductors in
Fig. 1 are simple models of bonding wires, package leads,
and other inductive elements. This model neglects the effects
of capacitive coupling between intermediate nodes in theserially connected bonding wire, package lead, and external
inductors. Furthermore, mutual coupling between neighboring
connections is assumed to be modeled as a reduced (or
increased) effective inductance for each individual connection.
It is mainly this crude modeling of inductance that will give
an upper frequency limit for which the models derived in the
following are valid.
When logic gates generate a current spike, the peak noise
in the node, illustrated near in Fig. 1(c), is given as
[6], [16]
(1)
where , and is the total capacitance that is
switched during a clock cycle. This is derived from charge
sharing between and , assuming that the total charge of
the current spike is supplied by the decoupling capacitance and
not by the bonding wires. A more accurate model was derived
in [17] including the bonding wires and the rise/fall time of
the switched node, but, for large values of , (1)
is a good approximation. In the second-order system in Fig.
10577122/98$10.00 1998 IEEE
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(a) (b)
(c)
Fig. 1. (a) Model of a CMOS circuit including bonding wire inductance. (b) Second-order model of the chip for which resonance frequency
and dampingfactor are defined. (c) Noise waveform of the internal node for an underdamped system when the internal circuits are switched.
1(b) with a damping factor , the peak-to-peak noise is
(2)
where is given by (1). A worst-case limits to
If the next clock edge occurs at in Fig. 1(c), the noise
peak will be larger than at , giving noise accumulation.
Adding on-chip decoupling capacitance increases in
Fig. 1(b) and allows larger inductance, yielding a lower
resonance frequency. Assuming a fixed clock period, there
will be fewer oscillation periods during which oscillation
energy must be dissipated before the next clock edge arrives.
Therefore, systems with on-chip decoupling capacitance needmore attention to damping during design to avoid risk of
noise accumulation. Although the peak noise [ in (1)] is
reduced by an increased , the peak value to which noise
accumulates may remain the same if is not selected carefully
and damping is not sufficient. The peak accumulated noise can
be estimated by setting the energy injected into the tank
by the switching circuit equal to the energy loss introduced by
resistive losses. This will not be treated further in this paper.
The derivations presented below will focus on digital cir-
cuits. Modifying the derivations to suit mixed-mode designs
show that damping is a critical design parameter for these
circuits as well. For sampled analog systems, noise oscillations
must be sufficiently damped before a sample is taken. Im-proved damping directly maps to better performance in terms
of a higher sampling frequency.
III. MODELINGCMOS CIRCUITS WITH NETWORKS
The model in Fig. 1(a) is approximated in two steps to get
the model in Fig. 1(b). First, each logic gate is modeled as a
resistor and two capacitors as in Fig. 2(a), which is reduced
to a single branch in Fig. 2(b). Secondly, the parallel
branches in Fig. 2(b) are merged into a single branch as in
Fig. 1(b).
(a)
(b)
Fig. 2. (a) Logic circuits in Fig. 1(a) have resistive path to either or and there is a parasitic resistance in the decoupling capacitance. (b)Network in (a) can be approximated with a simpler network.
A. Simplified Model of Each Logic Gate
The output of each logic gate in Fig. 1(a) has a resistive
path to either or , depending on its logic state.
When approximating the circuit in Fig. 2(a) with the model
in Fig. 2(b), the lower limits on both the capacitance and the
inductance are first determined. These give an upper limit onthe resonance frequency at which the relative impedance of
and in Fig. 2(a) are compared. The result is that
is shorting , i.e., Fig. 2(b) is a good approximation of Fig.
2(a).
Capacitance Estimation: The total capacitance in Fig. 1(a)
consists of and , where
(3)
A lower limit on is determined from the required noise
level in (1), where . is the activity ratio often
used in power consumption estimations and within the range
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LARSSON: RESONANCE AND DAMPING IN CMOS CIRCUITS 851
0.050.3 [18], [19]. In digital CMOS circuits it is customary
to keep the noise below , the threshold voltage of an
MOS transistor. Preparing for an underdamped system with
a required peak-to-peak noise less than , is set to
in (1), which gives a required decoupling capacitance of
(4)
Here, we assume in (1), where
the second term is the capacitance of inactive circuits. The
switched capacitance is excluded from operating as decoupling
capacitance, as explained in the Appendix. A standard CMOS
process with and gives
. was selected to ten in [6]. A lower limit on the
total capacitance in Fig. 1(b) is
(5)
The sign esteems from the fact that cannot be lower
than when and are connected in series in Fig. 1(a),
reducing the effective capacitance to only ,
assuming
Inductance Estimation: Decoupling capacitance is added
because the inductive noise is too large. Assume, e.g.,
and that the current charging/discharging the
switched capacitance is a triangle pulse with amplitude
and duration , the rise time of an internal node. This gives
(6)
If all of the capacitance was not switched simultaneously, the
lower limit on would be even larger.
Resonance Frequency and Relative Impedance: With
lower limits on both the inductance and capacitance, an upper
limit on the resonance frequency can be estimated as
(7)
Comparing the impedance of and in Fig. 2(a) at the
resonance frequency gives
(8)
where the last step is based on
and The impedance ratio for the circuit in
[14] can be estimated as 0.05, indicating that real circuits have
a ratio much smaller than the limit predicted by (8). Assuming
, a logic gate in Fig. 2(a) can be approximated
by in series with shown in Fig. 2(b). This gives
in Fig. 1(b) as
(9)
If the time constant of the decoupling capacitor is made similar
to that of standard logic, an upper limit on the damping factor
can be estimated as
(10)
indicating that resonance is likely.
B. Merging Several Branches
In the following the circuit in Fig. 2(b) is approximated
with the model in Fig. 1(b). If the capacitor and resistor of each
branch in Fig. 2(b) can be written and
for , all branches can be merged into a single
branch with
(11)
Another approximation is to first replace each branch of
series resistor and capacitor with an equivalent branch where
and are connected in parallel. At a single frequency, ,
the impedance of the circuit in Fig. 3(a), is equivalent to that
of the network in Fig. 3(b) if [20]
(12)
By choosing , given in Fig. 1(b) with determined
by (11), the circuit in Fig. 3(a) is equivalent to the model in
Fig. 3(b), which is transferred to Fig. 3(c). Equation (12) is
used to get the model in Fig. 3(d). The latter approach gives
better estimates than (11) when merging branches with large
differences in time constants, which violates the assumption
at (11). Both of these methods were compared in simulations
of large circuits in both the time and frequency domain,
showing good agreement [3].
The previous two methods of creating the second-ordermodel in Fig. 1(b) do not take the influence of the switching
circuits into account. As shown in Appendix, the switching
circuits will appear either as a damping resistor or as de-
coupling capacitance. However, the contribution to damping
and/or decoupling is small, so both of these positive effects
can be ignored.
Now we have a simple circuit model of a chip, which allows
us to estimate the resonance frequency and the damping
factor In the following, these estimates are used to provide
a circuit with proper on-chip decoupling capacitance, giving
reasonable damping.
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(a) (b)
(c) (d)
Fig. 3. (a) Series and (b) parallel connection of and gives equivalentimpedance at a single frequency. Several logic gates can be merged to a singleparallel branch as in (c), which can be translated to the equivalent serialcircuit in (d).
IV. INTRODUCING DAMPING
A resistor can increase damping in a resonance circuit.
Resistors exist at three places in Fig. 2(b): inherent resistance
of logic circuits, resistance in decoupling capacitance, and
resistance in the power supply paths (not shown). A resistancefrom to would also give damping with the drawback
of dc current.
A. Resistance of Logic Circuits
By intuitively selecting the resistance of the decoupling
capacitance to give a similar time constant in the capacitor
as in the logic circuits, the damping has an upper limit as
shown in (10). This damping is low, so one cannot rely on
this resistance to reduce resonance oscillations. A decoupling
capacitor with smaller time constant than the logic circuits
[5] will give an even lower damping factor. For mixed-mode
design, the acceptable noise level is often lower than used in(4). This gives a larger and an even lower limit on in (10).
B. Selecting Resistance in the Decoupling Capacitance
The resistance of the decoupling capacitance in Fig. 2
is a design parameter. To maximize the damping, it is derived
how the damping depends on First, (11) is used to merge
all branches representing the internal logic circuits. Then a
decoupling capacitance according to (4) is added, which gives
the model in Fig. 4(a), where as in
(9). Equation (12) is used to merge these branches, which
gives the intermediate circuits in Figs. 4(b) and 3(c). An
approximate solution to this optimization problem is obtained
when minimizing , the equivalent resistance of ,
and As cannot be changed, the possibility of
minimizing by selecting a proper is investigated, i.e.,
(13)
which gives and This leads to
(14)
(a)
(b)
Fig. 4. (a) Model used when choosing
to maximize damping. (b)Equivalent parallel circuit of model in (a).
where it is assumed from (9) and
Equations (12) and (13) also give
(15)
where the last step is based on part of (9), and
Equation (12) gives and
(16)
A typical circuit with and in (4) will
have By selecting so that the decoupling
capacitance has a similar time constant as the internal circuits
[5], will be much lower than 0.5.
A large may give large resistive voltage drop when
the peak current of switching circuits is injected into the
decoupling capacitor. However, for most circuits, the inactive
part of the circuit will act as decoupling capacitance and it
has sufficiently low resistance to take care of the peak current.
The added decoupling capacitance takes care of the main
portion of the charge that is switched during each clock cycle.
Furthermore, if the inherent parasitic channel resistance of an
MOS transistor [21] is used as , good damping can be
achieved since the resistance is large at low frequencies at
the same time as resistive noise is avoided due to the reducedresistance at high frequencies.
C. Double Decoupling Capacitors
If the circuit has high degree of activity [large in (4)]
or if there is a large peak current, the inactive circuits might
not have low enough resistance to avoid resistive drop. In
this case the use of two decoupling capacitors is suggested
[22]. One capacitor is used to assure low resistive drop
while the other capacitor optimizes the damping. The design
procedure for this strategy is as follows. First, a low-resistance
decoupling capacitor is selected according to (4). Then
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LARSSON: RESONANCE AND DAMPING IN CMOS CIRCUITS 853
another capacitor is added as
(17)
i.e., is the ratio between the well-damped capacitance and
the nearly undamped capacitance. A parasitic resistance
is then chosen to maximize the damping according to (13). The
same reasoning as deriving (14)(16) gives an equation similar
to (16) with replaced by This indicates that circuits
with high degree of pipelining require a larger decoupling
capacitance than predicted by (4). A similar technique for
reducing the -factor of circuits with on-chip decoupling was
presented in [23], where an additional inductor was connected
in series with
D. Resistance in Power Supply Paths,
The resistance in the power supply paths adds to the
equivalent series resistance in Fig. 1(b). is not only
the resistance of on-chip wiring, but also the series resistance
of external components [14].
A series resistance in the decoupling capacitance maypractically give a damping factor of about 0.30.4. This is
sufficient if the resonance frequency is a few times larger than
the clock frequency. For high-speed systems, this requires a
low power supply path inductance. In this case can be
used to increase the damping. It might be sufficient to model
or, if the power supply resistance is small, a resistor is
added [10], [13]. This coincides with the suggestion to add
a series resistance in an output buffer [8], [9] that not only
reduces levels but also improves damping. Difficulties
in modeling the parasitics can be avoided by minimizing the
parasitics and adding It may even be process compensated
as suggested in [10].
Due to resonance effects, the peak-to-peak noise can be
lower when including This indicates that a zero-resistance
power distribution network might not give the lowest noise,
contradicting the common rule of using minimum-resistance
power distribution. The contribution to damping is greater for a
resistor in series with the bonding wires than if the resistor is in
the power distribution system of the logic circuits. Therefore,
decoupling capacitance should electrically be connected as
close as possible to the logic circuits and not close to the
bonding wires (for example, in the pad frame). In this way,
resistive noise seen by the logic circuits will also be smaller
since the peak current through the bonding wires is smaller
than the peak current injected into the decoupling capacitance.
E. Adding a Parallel Resistor from to
As discussed in the Appendix, the switching circuits can
be modeled as a resistor from to with a current
equal to the average circuit current. This resistor will intro-
duce damping and, by adding another resistor in parallel, the
damping is further improved. However, the improvement in
damping introduced by the switching circuits is rather small.
To double this increase in damping would require an additional
dc power consumption equivalent to the power consumption
of the circuit itself, which is unrealistic.
Fig. 5. Noise accumulation in a system with gated clock and a too large time constant.
V. SELECTION OF POWER SUPPLY PATH INDUCTANCE
The basic rule of selecting the power supply path inductance
is to add a sufficient number of bonding wires not to violate
their current limitation. Traditionally, the number of wires is
selected to keep noise below noise specifications, but
that should be accomplished with the decoupling capacitance.
To not degrade the efficiency of the decoupling capacitor,
the charge redistribution from the switching circuits to the
decoupling capacitor must be achieved in less than half a
clock cycle, which gives , where is theclock period. For latch-based logic, we need
Assuming a total chip capacitance of determined by (9)
and choosing as (13), we get
(18)
The time constant must also be smaller than a clock
period. As illustrated in Fig. 5, where the bold line indicates
3/4 of a cycle at the resonance frequency, noise accumulation
might occur if This gives a rule that is
less strict than the rule of keeping much lower than
[1]. The rule in (18) is critical for systems with gated
clocks and shutdown techniques. Such systems may have large
changes in the average current demand, which may cause
noise accumulation during several clock cycles. However, for
a continuously clocked system with , it may be
assumed that there is no subharmonic of , or any other
signal, at the resonance frequency, so that resonance will not
occur. Furthermore, with a continuous clock, part of the current
demand of the circuit will appear as a dc current if the time
constant is larger than the resonance frequency. Therefore,
the decoupling capacitor need not take care of all charge
during a clock cycle and it is possible to violate (18). This
will be illustrated with the example circuits discussed later
and having is actually used in [6] as evident from
[14]. Note that the time constant restriction is not validfor the technique with double decoupling capacitors. in
series with is used to improve the damping, so the time
constant need not be less than a clock period.
VI. DESIGN SUGGESTIONS
Sections IV and V are summarized by the design checklist
below, describing the flowchart in Fig. 6.
1) Choose according to (5) and according to (13),
and select the number of bonding wires to not violate
their current limitation.
2) If causes too large resistive noise, reduce
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Fig. 6. Flowchart for selecting on-chip decoupling capacitance and power
supply path inductance.
3) If damping is satisfactorily, go to 7). This is not very
likely according to the discussion in Section IV-B. If
damping is too low, add
4) If the voltage drop over is acceptable, go to 7).
Otherwise, reduce , increase , and select a new
An increased improves damping according to (16).
5) If the size of is acceptable, go to 7). Otherwise, try to
add a damping capacitor with a parasitic resistor
according to Section IV-C and select new values
of , , and
6) If the resistive noise and the achieved damping are
satisfactorily, go to 7). Otherwise, reduce inductance by
adding more bonding wires and start from 2).
7) If the requirements discussed in conjunction with (18)
are fulfilled, the design is completed. Otherwise, reduce
and start from 2).
Note that this design scheme starts with the smallest possible
number of bonding wires and then adds as small decoupling
capacitance as possible to meet design requirements for the
noise level and damping. If the damping techniques are not
sufficient, additional capacitance is added. In the worst case,
inductance is reduced. It is always possible to find a solution to
the design problem, but this scheme will give the solution with
the smallest cost assuming that the cost of reducing inductanceis larger than the cost of increased decoupling capacitance.
VII. TWO EXAMPLE CIRCUITS
Two realistic circuits in a 1- m CMOS technology were
simulated to verify the previous estimates and design sugges-
tions. The circuits were a 12 16-b multiplier with five latch
stages and an 8 8-b multiplier where each fulladder has two
latch stages. The multipliers consisted of ten different cells,
including clock buffers. It is impractical to run analog simu-
lations of large-scale networks to find damping and resonance
frequency. Therefore, SPICE simulations of the simplified
TABLE ICHARACTERISTICS OF TWO EXAMPLE CIRCUITS
122 6 multiplier 82 8 multiplier
5 V 5 V
0.75 V 0.75 V
110 pF 100 pF
0.4 0.4
0.2 0.2
40 mA 90 mA
100 MHz 200 MHz
110 mW 195 mW
22 mA 39 mA
# transistors 7000 5400
network in Fig. 2(a) were compared with SPICE simulations
of the complete transistor networks including parasitics. The
circuit in Fig. 2(b) was simulated in the frequency domain
with MATLAB. The simplified models were obtained by first
extracting and for each of the ten logic gates and then
connecting all branches in parallel using a weighting
factor reflecting the multiplicity of each cell in the circuit [3].
A. Estimating and for the 12 16-b Multiplier
The circuit capacitance in (3) was extracted to
pF and the resistance was estimated to
using (10). From simulations of power consumption, the
average capacitance switched in each clock cycle was 43.7
pF including the clock buffer. This gives
, describing the average behavior of the
circuit. Since the circuit is based on latches, half of the
switched capacitance is charged/discharged at the positive and
the negative clock edge, respectively. Therefore,
should be used, and it implies that the charge redistribution
from the switching circuits to the decoupling capacitor mustbe achieved in less than half a clock cycle, giving a modified
restriction in (18).
B. Estimating and for the 8 8-b Multiplier
The 8 8-b multiplier had an extracted circuit capacitance
of pF and a resistance of A
capacitance of 39 pF was switched each clock cycle. This
gives and as defined
above. As will be shown, the decoupling capacitance design
procedure will be quite different for the two multipliers, which
is caused by a larger peak current of the 8 8-b multiplier as
shown in Table I summarizing the multiplier characteristics.
VIII. DECOUPLING THE EXAMPLE CIRCUITS
This section demonstrates the practical use of the flowchart
in Fig. 6. The goal of the simulations was to supply the two
multipliers with power using as few bonding wires as possible.
It was assumed that the current limit of a bonding wire is 200
mA and its inductance is 10 nH. A peak-to-peak power supply
noise limit was set to V. The subsections below are
labeled i, ii, , according to Fig. 6.
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assumed to be some mixture of the two extremes derived
here. Furthermore, both the improvement in damping and the
contribution to decoupling capacitance are small. Therefore,
the effects of the switching circuits can be neglected, as done
in various sections of this paper.
ACKNOWLEDGMENT
The author would like to thank Prof. C. Svensson, C.
Jansson, and the late Associate Prof. S. Eriksson at Linkoping
University for their helpful discussions.
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for reducing the effects of electrical interference in mixed-mode ICs,IEEE J. Solid-State Circuits, vol. 32, pp. 11361141, July 1997.
Patrik Larsson received the Ph.D. degree fromLinkoping University, Linkoping, Sweden, in 1995,where his research focused on the inherent analogproperties of digital signals and how they affectdigital circuits.
From 1993 to 1994 he was with a mixed-modedesign group at ERSO/ITRI, Taiwan. He is now withthe DSP and VLSI Systems Research Group, BellLaboratories, Lucent Technologies, Holmdel, NJ.His current interests are in low-power arithmetic andsignal processing, clock recovery and equalization
for cable modems, and various flavors of phase-locked loops (PLLs). He hascontributed to analysis, measurement, testing, and robust design. He has alsoworked on PLLs and high-speed CMOS frequency dividers and counters.
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