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Speaking at imec’s International Technology
Forum USA yesterday afternoon at the Marri-
ott Marquis, Luc Van den Hove, president and
CEO of imec, provided a glimpse of society’s
future and explained how semiconductor tech-
nology will play a key role. From the IoT to early
diagnosis of cancer through cell sorters, liquid
biopsies and high-performance sequencing,
technology will enable “endless complexity
increase,” he said.
Other developments, almost all of which are
being worked on at imec, include self-learning
neuromorphic chips, brain implants, artificial
intelligence, 5G, IoT and sensors, augmented
and virtual reality, high resolution (5000 ppi)
OLED displays, EOG based eye tracking and
haptic feedback
devices. He also
acknowledged
t h e c r i t i c a l
importance of
security issues,
but suggested
a solution. He
noted that each
chip has it s
own fingerprint
due to nanoscale variability. That’s been a
problem for the industry but we could “turn
this limitation into an advantage,” he said,
with an approach called PUFs — Physical
Unclonable Functions (Figure 1, page 3).
JULY 11, 2017
MOSCONE CENTER | SAN FRANCISCO, CALIFORNIA
TUESDAYSHOW DAILYSHOW DAILYSHOW DAILY9:05 am – 9:35 amKEYNOTE: The Semiconductor Industry: Changed and UnchangedTetsuro Higashi, TELYerba Buena Theater
9:35 am – 10:05 amKEYNOTE: Accelerating Innovation: Intelligent is the New SmartThomas Caulfield, GLOBALFOUNDRIES
10:30 am – 4:00 pmWorld of IoTUnderstanding Risks and OpportunitiesSan Francisco Marriott Marquis
10:30 am - 12:45 pm What’s next for MEMS & SensorsBig Growth of Disruptive ApplicationsMoscone North, TechXPOT North
2:00 pm – 5:00 pmChina Strategic Innovation & Investment ForumThe Rise of the China IC IndustryYerba Buena Theater
3:00 pm – 4:30 pmAdvanced PackagingMeet the Experts, Day 1Meet the Expert Theater, Moscone West
5:00 pm – 10:00 pmSummerfest at AT&T ParkHors d’oeuvres, beverages and MLB All-Star Game
5:00pm – 9:00pmLeti Workshop W Hotel - 181 3rd St., San Francisco
continued on p. 3
DON’T MISS
In the advanced CMOS technology programs
ongoing in the Belgium city of Leuven,
IMEC works to extend the building-
blocks of integrated circuits (IC). On the
day before the opening of SEMICON West
2017, the invitation-only IMEC Technology
Forum provided an update on the emerging
opportunities in semiconductor technology
and smart electronics systems. An Steegen,
Executive VP Semiconductor Technology &
Systems, provided the update on how small
we can scale CMOS devices over the next 5-10
years. Taller finFETs will likely be used along
with nano-wire FETs (NW-FET) by industry,
and researchers see ways to cost-effectively
combine both in future optimized System-
on-Chips (SoC).
“Existing finFET technology can scale
to the 5nm-node,” explained An Steegen at
ITF 2017 in Antwerp, Belgium. “However,
at the 3nm-node it looks like the nano-wire
is comparable in performance to the finFET,
but it has an additional advantage in that the
nanowire is a better electro-statically con-
continued on p 6
How Low Can We Go?
Luc Van den Hove, presi-dent and CEO of imec
BY ED KORCZYNSKI
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At the forum, imec also announced that its
researchers, in collaboration with scientists
from KU Leuven in Belgium and Pisa Univer-
sity in Italy, have performed the first material-
device-circuit level co-optimization of field-
effect transistors (FETs) based on 2D materials
for high-performance logic applications scaled
beyond the 10nm technology node. Imec also
presented novel designs that would allow using
mono-layer 2D materials to enable Moore’s law
even below 5nm gate length. Additionally, imec
announced that it demonstrated an electrically
functional 5nm solution for Back-End-of-Line
interconnects.
FETs based on 2D materials2D materials, a family of materials that form
two-dimensional crystals, may be used to cre-
ate the ultimate transistor with a channel thick-
ness down to the level of single atoms
and gate length of few nanometers.
A key driver that allowed the indus-
try to follow Moore’s Law and con-
tinue producing ever more powerful
chips was the continued scaling of the
gate length. To counter the resulting
negative short-channel effects, chip
manufacturers have already moved
from planar transistors to FinFETs. They are
now introducing other transistor architectures
such as nanowire FETs. The work reported
by imec looks further, replacing the transistor
channel material, with 2D materials as some
of the prime candidates.
In a paper published in Scientific Reports,
the imec scientists and their colleagues pre-
sented guidelines on how to choose materials,
design the devices and optimize performance to
arrive at circuits that meet the requirements for
sub-10nm high-performance logic chips. Their
findings demonstrate the need to use 2D mate-
rials with anisotropicity and a smaller effective
mass in the transport direction. Using one such
material, monolayer black-phosphorus, the re-
searchers presented novel device designs that
pave the way to even further extend Moore’s law
into the sub-5nm gate length. These designs re-
veal that for sub-5nm gate lengths, 2D electro-
statics arising from gate stack design become
more of a challenge than direct source-to-drain
tunneling. These results are very encourag-
ing, because in the case of 3D semiconductors,
such as Si, scaling gate length so aggressively
is practically impossible.
5nm solution for BEOLThe announced electrically functional solu-
tion for 5nm back-end-of-line (BEOL) is a full
dual-damascene module in combination with
multi-patterning and multi-blocking. Scaling
boosters and aggressive design rules pave the
way to even smaller dimensions.
As R&D progresses towards the 5nm tech-
nology node, the tiny Cu wiring schemes in
the chips’ BEOL are becoming more complex
and compact. Shrinking the dimensions also
reduces the wires cross-sectional area, driving
up the resistance-capacitance product (RC)
of the interconnect systems and thus increas-
ing signal delay. To overcome the RC delay
challenge and enable further improvements
in interconnect performance, imec explores
new materials, process modules and design
solutions for future chip generations.
One viable option is to extend the Cu-based
dual-damascene technology – the current
workhorse process flow for interconnects – into
the next technology nodes. Imec has demon-
strated that the 5nm BEOL can be realized
with a full dual-damascene module using multi-
patterning solutions. With this flow, trenches
are created with critical dimensions of 12nm at
16nm. Metal-cuts (or blocks) perpendicular to
the trenches are added in order to create elec-
trically functional lines and then the
trenches are filled with metal. Area
scaling is further pushed through the
introduction of fully self-aligned vias.
Moreover, aggressive design rules are
explored to better control the variabil-
ity of the metal tip-to-tips (T2Ts).
Beyond 5nm, imec is exploring al-
ternative metals that can potentially
replace Cu as a conductor. Among the can-
didates identified, low-resistive Ruthenium
(Ru) demonstrated great promise. The imec
team has realized Ru nanowires in scaled di-
mensions, with 58nm2 cross-sectional area,
exhibiting a low resistivity, robust wafer-level
reliability, and oxidation resistance – eliminat-
ing the need for a diffusion barrier.
Semiconductor Advances continued from p. 1
Figure 1. Nanoscale variability has been a problem for the industry but we could be turned into an advantage with PUFs — Physical Unclonable Functions.
Figure 2. 2D materials, with the atomically-precise dimension control they enable, promise to become key materials for future innovations.
Figure 3. Dense-pitch blocks enabled by a dual damascene flow and multi-patterning. The pattern is etched into the low-k and metallized.
Show Daily StaffPublished by Solid State Technology,
an Extension Media company.
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MOSCONE CENTER | SF, CA
4
Integrating data from various sensors in semi-
conductor fabs is a key focus in the industry
now, and the sub-fab is an increasingly impor-
tant part of the equation. As process steps be-
come ever more sophisticated and expensive,
keeping pumps and other sub-fab equipment
running optimally involves integrating mul-
tiple pieces of data into useful information.
Paul Rawlings, president of the SEMI Ser-
vice Division at Edwards, Ltd., said while the
semiconductor industry has a history of ana-
lyzing tool data and relating it to end processes,
more progress is needed in considering the
entire fab as an ecosystem.
“The sub-fab equipment also has a bear-
ing, not just in terms of how efficiently we
are using data to manage
the sub-fab efficiently,
but also in terms of im-
proving overall fab per-
formance and yields,”
Rawlings said.
Edwards is developing
“a structured approach to
the kinds of data that we
have, and how we use it,”
Rawlings said, includ-
ing a database of best
known methods (BKMs)
which includes the opti-
mum configurations for
pumps, abatements and
other systems.
Edwards currently
is launching EdCentra, a fault detection and
classification (FDC) software platform aimed
at the sub-fab. It provides a comprehensive
solution to vacuum security, to take one exam-
ple, by combining equipment monitoring, data
acquisition, and analysis of operational data.
Besides monitoring the performance of the
equipment, the EdCentra sub-fab information
management system has built-in predictive
capabilities. And it complements another Ed-
wards tools, which records service activities.
When a pump is taken back to an Edwards
service center, it is stripped down and serviced.
“Then we update all of that on to our central
database on the lifetime and the performance
of our equipment. We have an ecosystem
there,” he said.
The company’s overall goal, Rawlings said,
is to connect what have been “fairly separate
systems,” maximizing up-times in part by
comparing the performance of different tools
in the same area.
By extending the data analysis ecosystem,
Edwards can increase up-times and refine
service scheduling. “The data is there. When
we connect these systems, that’s where we get
all of the benefits from the data. It’s no longer
about taking data at individual points along the
life cycle. It’s about connecting the data across
the journey of the equipment and then looking
for optimization, adjustments, and maybe up-
grades on the equipment,” he said.
Engineers and data scientists throughout
the semiconductor industry are developing
more fab-level techniques, using multi-variate
analysis of data coming off the tools, as well as
other inputs.
For Edwards, that involves looking at data
coming from pressure gauges, temperature
sensors, the power spectrum, and, increas-
ingly, the very useful information derived from
vibration monitoring.
“What we are finding is that by looking at
the combinations of data, that’s when things
become really interesting. Rather than just
relying on one or two points of data on the
equipment, we’re starting to build up a library
of different parameters. Then we are looking
to see how we combine those to give us the
most accurate predictions of tool lifetime,”
he said.
Edwards is working closely with two fabs
to develop data-sharing protocols that allow
for optimum monitoring of the sub-fab equip-
ment. “We are looking at it both from their
point of view, and ours, discussing different
ways of processing the data and the analysis
of the performance of the equipment.”
Because of the huge amounts of data in-
volved, Rawlings said “we only transmit data,
if you like, that moves. It’s not worth sending
data at 10+ Hertz when that particular param-
eter is not moving. It’s only worth sending that
data when a change occurs.”
The work with customers is done within
strict limits to ensure data security. “Clearly,
you would never want to share any data that
could give any indication of what customers
do in their fabs and we go to great lengths to
safeguard this” he said.
One encouraging sign is that, industry
wide, cloud security is becoming more effec-
Edwards Sees Promise in Sub-Fab Data AnalysisBY DAVE LAMMERS
EdCentra, Edwards Sub-Fab FDC platform, provides process-critical vacuum and abatement equipment informa-tion, complementing Fab-based platforms and supporting industry efforts to create integrated Fab data-manage-ment systems.
continued on p 10
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MOSCONE CENTER | SF, CA
6
trolled device so it enables gate-
length scaling more than the fin-
FET. So the contacted gate pitch
(CGP) of a nano-wire can scale
further than a finFET, because
below ~40 nm CGP a finFET los-
es electro-static control which a
nano-wire does not.”
While it is given that a nanow-
ire has better electro-static con-
trol compared to a finFET, the
basic trade-off is that of reduced
drive current. The Figure shows
that IMEC sees the possibility of
System-Technology Co-Optimi-
zation (STCO) of future system-
on-chip (SoC) designs using
hybrid semiconductor technolo-
gies. IMEC’s basic process flow
for NW-FETs starts with form-
ing fins and so could be relatively
easily integrated with finFETs for
co-integrated
hybrid CMOS.
“Today, this
SoC is pro-
cessed in one
t e c h n o l o g y
which means
it’s sub-opti-
mal for certain
blocks on the
SoC,” explained
Steegen. “So
imagine a fu-
ture where you
can choose the
preferred tech-
nology for each
block. I would
choose finFETs for those blocks
that need drive current, while I
would choose nano-wire-FETs
for those blocks that need more
density and lower power. I would
for example choose a magnetic
RAM to replace my cache memo-
ry. I can optimize each sub-block
for a preferred technology. Now
I can do more, like sprinkle in
low-energy devices like
tunnel-FETs or spin-de-
vices or 2D-materials as
low-energy switches.”
Super-vias and RutherailsDesign-Technology Co-
Optimization (DTCO) is
IMEC’s term for new in-
terconnect technologies to
allow for simpler or more-
compact designs. IDTCO
process-scaling boosters
are needed to stay with the
pace of aggressive design
rule targets. “We’re work-
ing on super-vias that con-
nect more than one metal
to the other and can jump a
number of levels, and bur-
ied rails to support finFETs
in standard-cell libraries,”
explained Steegen during
ITF2017.
Super-vias could be
cobalt plugs that connect
more than two metal levels
within on-chip multi-level inter-
connects. The cobalt plugs would
be nominally 20nm diameter and
105nm deep, and connected to a
dual-damscene upper metal line.
Low-k dielectric of k=2.55 uses
thin silicon carbon nitride (SiCN)
for definition between the dama-
scene levels.
Ruthenium rails (Rutherails)
would be buried in a front-end di-
electric layer to provide electrical
contacts below finFETs for 42nm
CGP and 21nm MP needed for
IMEC 3nm-Node (I3N) devices.
Ruthenium rails 30nm deep and
10nm wide do not need complex
barrier layers and should provide
sufficient current flow for either
finFETs or NW-FETs.
IMEC is also working on ma-
terials R&D to extend the per-
formance of 3D-NAND. Steegen
said,
“At IMEC we are working on
improving the performance of
that Flash device by introducing
high-mobility channels, also by
engineering the dielectric trap-
ping layer with a barrier that can
help improve the erase window
and also the retention.”
System-Technology Co-Optimization (STCO) for future System-on-Chip (SoC) designs could integrate finFETs with Nano-Wire FETs (NW-FET) and Magnetic Random Access Memory (MRAM) for optimized performance. (Source: IMEC)
How Low continued from p. 1
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MOSCONE CENTER | SF, CA
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SEMI has enriched this year’s SEMICON West
by offering new, timely programs and forums
for attendees to engage with peers and present-
ers at the three-day industry event.
“As our industry changes, we’re changing
too,” said Dave Anderson, president, SEMI
Americas. “Our programs are now organized
around specific “Smart” applications, tech-
nologies, and adjacencies such as Smart Au-
tomotive, Advanced Packaging, 5G, and IoT,
making it easy for attendees to focus on their
specific needs,” he added. “We’ve reenergized
the entire exposition and conference to put a
laser focus on addressing challenges, finding
solutions, and giving attendees everything
they need to thrive in today’s disruptive busi-
ness environment.”
SEMICON West offers 115 hours of ad-
vanced programming and more than 600
exhibits. The industry’s flagship event, re-
imagined for 2017, will also feature inaugural
programs, including:
• China Strategic Innovation & Investment
Forum — China’s semiconductor indus
try is going through an explosive growth
phase. IC and investment executives will
share their views on the industry’s evolution
and offer insights on investment and M&A
trends in China.
• Meeting the Challenges of the 4th Indus-
trial Revolution along the Microelectron-
ics Supply Chain — The executive panel
will address the opportunities and chal-
lenges facing the industry as the era of Big
Data fuses the physical and digital worlds.
• Smart Automotive, 5G Communications,
MEMS & Sensors, MedTech and more
will be discussed in the expanded TechX-
POT sessions on the show floor.
• IEEE Embedded Systems Training
Workshops for IoT —Two exclusive IEEE
workshops will cover embedded system
software development, the key to optimiz-
ing performance and power in IoT devices
and applications.
• New Ways to Engage & Network — The
new SMART Journey on the exposition
floor will deliver stunning, hyper-visual in-
sights into the microelectronics innovations
that are revolutionizing the manufactur-
ing supply chain, automotive, and everyday
living. At the Journey’s Meet the Experts
Theater, attendees will hear how break-
throughs in processes, packaging, and AI
are changing the world.
• Career Development — Amid competi-
tion from trendy companies like Google and
Facebook, the semiconductor industry also
needs to attract the best and the brightest.
At the MicroE Career Development & Re-
cruitment Forum, job seekers will learn
about opportunities at some of the leading
names in electronics.
• On the fun front, the Summerfest at AT&T
Park, home of the San Francisco Giants,
will provide a bit of R&R as conference
attendees network and watch the All-Star
Game live on the stadium’s Big Screen.
In addition, SEMICON West features keynote
talks from industry luminaries including Tet-
suro Higashi of TEL, Tom Caulfield of GLO-
BALFOUNDRIES, Kathy Winters of Intel,
and special guest Jim Morgan of Applied Mate-
rials. The World of IoT: Understanding Risks
and Opportunities in Transformative
Technologies — focuses on key IoT
applications, big data and security,
including solutions for home auto-
mation, smart cities, industrial moni-
toring, medical and healthcare, envi-
ronmental monitoring, agriculture,
and more. All of this, along with tra-
ditional favorites such as the SEMI/
Gartner Bulls & Bears Industry
Outlook, will be held at SEMICON
West 2017.
To increase engagement with
speakers and colleagues and enhance
the overall Expo experience, attend-
ees are encouraged to download the
new SEMICON West Mobile App at
the App Store or Google Play.
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No recipes required. Just load and go. EagleView accepts four cassettes, with 100mm to 300mm wafers. And no recipes are needed. It’s totally plug-and-play. So you can eliminate all the time, hassle and special staff to generate and maintain recipes. With full automation, virtually anyone in your fab can use it anytime.
Catch more defects. And more root causes.Because it sees every wafer, EagleView can catch a lot more defects. And, it gives you smarter ways to track down the root causes. At the start of each run, the fab’s host automation system sends the lot’s tool history to EagleView, where that gets integrated with the wafer image data. So when you spot a defect you can readily drill down to deter-mine which particular process tool was the likely culprit.
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Wafer randomization for free.While EagleView is inspecting wafers it can also randomize or sort them. Automatically. While maintaining full speed. So, if you want to do slot position analysis you won’t need to buy extra sorters. And you won’t need special IT efforts to pull together usable databases. EagleView takes care of all of that automatically.
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MOSCONE CENTER | SF, CA
10
SEMI added a new high-profile program on
China to its 2017 conference lineup for SEMI-
CON West. Today at the Yerba Buena Theater,
the China Strategic Innovation & Investment
Forum will focus on the extensive business op-
portunities resulting from the semiconductor
industry’s largest regional growth spurt now
occurring in China.
While the global semiconductor in-
dustry continues to consolidate through
large-scale mergers and acquisitions,
China is embarking on a new round
of expansion with heavy investment
from public and private funding. Chi-
na’s semiconductor industry is growing at an
explosive rate, leading the rest of the world
with a projected increase of 68 percent in fab
equipment spending year-over-year (2017 to
2018), according to the May 2017 SEMI World
Fab Forecast. China will be equipping over 50
facilities through 2018, and is forecast to spend
more than US$11 billion.
The rise of the semiconductor industry in
China need not be viewed as a threat to other
global players, says SEMI, but rather as a sig-
nificant driver of growth and business oppor-
tunity for suppliers worldwide. With its low
indigenous market share for chips and nascent
technical breadth in IC design, manufacturing,
packaging, testing, equipment, and materials,
China has become an enormous market for
suppliers across the supply chain. In fact, ICs
still top the list of all Chinese bulk imports in
terms of U.S. dollar value.
At the China Strategic Innovation & Invest-
ment Forum, semiconductor and investment
executives, as well as key China government
and trade officials will share their views on
the industry’s evolution and offer insights on
growth, investment opportunities, M&A, and
the latest innovations emerging in China. At-
tendees will hear from C-Level executives from
Ali Cloud, AMEC, Applied Materi-
als Venture Capital Group, Gold-
man Sachs, Verisilicon, Walden
International, SEMI China, and
more. An hour-long panel discus-
sion, moderated by Lung Chu,
president of SEMI China, will fea-
ture speakers and a Q&A session. With access
to China experts presenting and multiple net-
working opportunities, the China forum will
offer a collaborative platform where markets,
technology, talent, and funding can meet up
for mutual benefit.
China Growth Surge Highlighted
China will be equipping over 50 facilities through 2018, and is forecast to spend more
than US$11 billion.
tive, reducing concerns about moving data to the cloud. “The
way that end-user data is segregated, the built-in security, is
resulting in a little bit more openness in terms of using this data,”
Rawlings said.
That said, it is still a difficult area to work with customers.
“I won’t mention names, but there are a few folks where we are
engaged, so we can move to the next level of validation. I think
it’s going to be an area of development over the next few years,
as we really focus on the right parameters to measure to predict
lifetimes.”
A lot of sub-fab equipment is affected by the processes, more
than the basic mechanics of the equipment. It is fairly rare to have
a bearing failure on a pump, for example. What is more likely is
that the pump will have some process-related issues, such as cor-
rosion or condensate build-up from materials in the fab.
“We spend a lot of time studying the process materials, tem-
perature settings, and those kinds of things to extend equipment
lifetimes, but there’s obviously always a limit to what can be
achieved. What we are now doing is looking at how the different
types of sensors that we have, both already on the equipment,
and other ones that we’re developing, can give us the best com-
bination, the best ways of predicting lifetimes. That’s an area
that we’ll be working hard on over the next few years for our
customers,” Rawlings said.
Edwards Sub Fab continued from p. 4
AdvancedProcessControlConferenceXXIX2017
Aus8n,TexasOctober9-12,2017
AirportHiltonHotel,Aus8n,Texas
CallforPapers:AbstractsdueJuly28,2017
Seewebsitefordetails
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12
Microtronic Inc.: EAGLEview 5 Mac-
ro Defect Management Platform
– EagleView 5 is the new, yield-enhancing,
breakthrough macro defect inspection plat-
form that was developed – and deployed in
production — through collaboration with
several leading device manufacturers who
wanted to standardize and unify wafer defect
management throughout their fab. Innovations
include: dramatically improved defect detec-
tion; level-specific sorting; and integration
with manual microscopes. (Process Control,
Metrology and Test Category; North Hall Booth
#5467)
SPTS Technologies Ltd: SentinelTM
End-Point Detection System for
Plasma Dicing after Grind – The Sen-
tinel™ End-Point Detection System improves
the control of plasma dicing processes and
protects taped wafers for improved yields. In
addition to signaling exposure of the tape, Sen-
tinel™ also detects loss of active cooling during
the process to enable intervention to prevent
yield loss. (Process Control, Metrology and Test
Category; West Hall Booth #7617)
TEL: Stratus P500 – The Stratus P500
system electroplates panel substrates with
wafer level processing precision. As redistri-
bution layers (RDL) reduce to widths below
10 µm line/space, and package sizes increase,
conventional plating systems are challenged to
meet system-on-package requirements. The
P500 makes panel scale fine line RDL and
feature filling applications possible. (Assem-
bly/Packaging Solutions Category; North Hall
Booth #6168)
SEMI and Solid State Technology Announce 2017 “Best of West” Award Finalists
Congratulations to each of the Finalists.
The Best of West Award winner will be announced during SEMICON West on Wednesday, July 12, 2017.
Each year at SEMICON West, the “Best of West” awards are presented by Solid State Technology and SEMI. More than 26,000 professionals from the electronics manufacturing supply chain attend SEMI-
CON West and the co-located Intersolar. The “Best of West” award was established to recognize new products moving the industry forward with techno-logical developments in the electronics supply chain.
Selected from over 600 exhibitors, the following Best of West 2017 Finalists will be displaying their products on the show floor
Mentor, a Siemens Business: Tessent® Cell-Aware Diagnosis – With FinFETs in
high volume, finding systematic yield issues at the transistor level is important. The Tessent Cell-
Aware Diagnosis technology significantly improves diagnosis of defects beyond the inter-connect
and inside the logic cells. (Process Control, Metrology and Test Category; North Hall Booth #6661)
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14
MEMS & Sensors Industry Group® (MSIG), the industry associa-
tion advancing MEMS and sensors across global markets, is host-
ing a TechXPOT program today, titled “What’s Next for MEMS &
Sensors: Big Growth of Disruptive Applications for Smart Sensing
Changes the Business.” Speakers from industry and academia will
explore the disruptive influence of MEMS and sensors on applica-
tions that span human-machine interfaces, disposable wireless
electronics, and wireless sensor nodes for smart cities. They will
also discuss advancements in piezoelectric materials for emerging
applications as well as MEMS foundry process technologies that
speed time to market.
“From smart autos and smart manufacturing to smart cities and
smart health monitoring, emerging markets for MEMS and sensors
are creating greater demand for integrated intelligence,” said Karen
Lightman, vice president, MEMS & Sensors Industry Group, SEMI.
“MSIG speakers at SEMICON West will help MEMS and sensors
suppliers to more ably respond to this demand, as they learn how
to add value through technological innovation and integration.”
Topics and presenters at the MEMS program at the TechXPOT
include:
• What’s Next for the MEMS Industry? — Jean-Christophe Eloy,
CEO and founder, Yole Développement
• New MEMS Opportunities from Piezoelectric Technology —
David Horsley, professor, Mechanical & Aerospace Engineering,
University of California Davis
• Smart IT Systems and Development Protocols Enable Faster
Time-to-Market in MEMS — Tomas Bauer, senior VP, sales/
business development, Silex Microsystems
• Waggle and the Future of Edge Computing and Smart Cities —
Pete Beckman, co-director, Northwestern-Argonne Institute
for Science and Engineering
• Roll-up Implementation of Gesture Sensing and Voice Isolation
Sensing Wall for Future Human-Machine Interface — James
Sturm, professor, Electrical Engineering, Princeton University
• Three Bit NFC Sensor Labels Based on a Flexible, Hybrid Printed
CMOS TFT Process — Arvind Kamath, VP of Engineering, Thin
Film Electronics
MSIG also invites members to attend the MEMS/NEMS Committee
Meeting, including a Task Force on microfluidics, from 3:30-5:30 pm
on July 13 at the San Francisco Marriott Marquis.
MOSCONE CENTER | SF, CA
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The Moscone Center will be undergoing major
construction during Semicon West week. The
major impact to attendees is that the South
Hall will be closed to allow for new construc-
tion, so Semicon will take place in the North
Hall and the first floor of the West Hall. The
crosswalks at the corner of 3rd and Howell will
also be closed. The Intersolar North America
show will occupy the West Hall Floor3 and
half of the West Hall Floor2. The International
Exhibition for Batteries and Energy Storage
Systems — ees North America — will occupy
the other half of Floor2. Expect heavy demoli-
tion operations to be underway nearby.
The Moscone Expansion Project plans to
meet that need by expanding contiguous exhi-
bition space as well as increasing the amount of
flexible meeting and ballroom spaces.
In addition to adding new rentable square
footage, the project architects – Skidmore,
Owings and Merrill – seek to create an iconic
sense of arrival that enhances Moscone’s civic
presence on Howard Street and reconnects
it to the surrounding neighborhood through
the creation of reintroduced
lost mid-block passageways. As
such, the project proposes two
new, enclosed pedestrian bridg-
es connecting the upper levels
of the new Moscone North and
Moscone South as well as an up-
grade to the existing pedestrian
bridge across Howard Street. This
would help to frame the main pub-
lic arrival space between the two
new buildings, provide enhanced
circulation for Moscone convention attend-
ees, and reduce on-street congestion all while
maintaining full-time elevated public access
across Howard Street from Yerba Buena Gar-
dens to the cultural facilities.
In related news, the San Francisco Travel
Association recently presented SEMI with the
2017 Crystal Bridge Award. Now in its eighth
year, award is given annually to honor major
convention customers that bring outstanding
events with significant impact to San Francis-
co. Past awards have been presented to Ameri-
can Bar Association, American Geophysical
Union, Oracle, Salesforce.com, the American
College of Surgeons and UBM. Semicon is one
of the only major shows that will take place
during Moscone’s construction phase.
Moscone Center Construction
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Highlighting the key drivers of industry growth
and innovation, SEMICON West 2017, is fo-
cusing on today’s smart technologies. Given
the explosive growth of electronics in automo-
biles — from infotainment to driver assistance
— SMART Automotive is in the spotlight. As
automobiles become mobile computing plat-
forms, they require more intelligence, speed,
and memory to meet ever-increasing require-
ments. The industry is responding with a new
generation of ICs, sensors, telematics, artificial
intelligence, embedded software, and machine
learning solutions designed to enable advanced
automotive systems, including powertrain
control, connectivity, infotainment, security
and safety mechanisms, and more.
In conjunction with SAE International
(Society of Automotive Engineers) and other
key players in the segment, SEMICON West
2017 will feature several informative sessions
covering the microelectronics innovations that
are revolutionizing the driving experience and
driving demand for chips. SEMICON West’s
new SMART Automotive sessions will provide
an insider’s view into this rapidly accelerating
market:
• From ADAS to Autonomous Vehicles — (R)
evolution Driven by New Technologies —
Luca De Ambroggi, IHS Markit
• New Generation of Automotive Semicon-
ductors Self-Test Solutions — Stephen Pa-
teras, Ph.D., Mentor Graphics
• Artificial Intelligence (AI) and Self-driving
Cars — Tim Wong, NVIDIA
• Accelerating the Future of the Connected
Car — Nakul Duggal, Qualcomm Tech-
nologies
• Range Extension through Energy-efficient
Connected Automated Driving — Brian
McKay, Continental Automotive Systems
• Accelerating Autonomous Technology for
Safety — David Agnew, Hyundai MOBIS
• IoT Cybersecurity - An End-to-End Busi-
ness — Simon Hartley, RunSafe Security
• Accelerating ADAS System-on-a-Chip
(SoC) Development with ASIL Certified
IP — Ron DiGiuseppe, Synopsys
The Smart Automotive sessions will provide
insights into the technologies, performance
upgrades, and market trends shaping the fu-
ture of the automotive industry and chang-
ing the world. The sessions are scheduled for
Tuesday, July 12 from 10:30am to 12:35pm and
2:00 to 4:00pm. In addition, SEMI is planning
to stage live demonstrations of some of the lat-
est innovations behind today’s autonomous
vehicle revolution.
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Last month, SEMI reported that worldwide
semiconductor manufacturing equipment bill-
ings reached US$13.1 billion for the first quar-
ter of 2017. The quarter ended very strong, with
March billings reaching
$5.6 billion, an all-time
monthly record.
Quarterly billings of
US$13.1 billion also rep-
resent the first time quar-
terly billings exceeded the
record quarterly high set
in the third quarter of
2000 ($13.0 billion). Bill-
ings for the most recent
quarter are 14 percent
higher than the fourth
quarter of 2016 and 58
percent higher than the
same quarter a year ago.
The data is gathered joint-
ly with the Semiconductor Equipment Asso-
ciation of Japan (SEAJ) from over 95 global
equipment companies that provide data on a
monthly basis.
The quarterly billings data by region in
billions of U.S. dollars, quarter-over-quarter
growth and year-over-year rates by region are
as follows:
Q1 Billings of $13.1 Billion New Record
1Q2017 4Q2017 1Q2016 1Q2017/4Q2016(Qtr-over-Qtr)
1Q2017/4Q2016(Year-over-Year)
Korea 3.53 2.39 1.68 48% 110%
Taiwan 3.48 4.15 1.89 -16% 84%
China 2.01 1.15 1.60 74% 25%
North America 1.27 1.24 1.01 3% 26%
Japan 1.25 1.05 1.24 19% 1%
Europe 0.92 0.93 0.35 -1% 160%
Rest of World 0.63 0.60 0.51 4% 23%
TOTAL 13.08 11.52 8.28 14% 58%
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18
The Linde Group is expanding production of the
rare gases used by the semiconductor industry,
including xenon, which is in increasing demand
for etching 3D semiconductor structures.
This quarter, Linde expects to complete a
xenon expansion project at its Alpha, N.J. plant,
part of a xenon supply network that spans three
continents. Of the three rare gases – neon,
krypton, and xenon – xenon is the rarest. Be-
sides extracting xenon from the atmosphere,
Linde provides numerous services to conserve
and optimize their process use of xenon, said
Matt Adams, head of sales and marketing, elec-
tronic gases & specialty products. “We have
been developing specialized solutions around
xenon for 30 years. Recycling xenon can actu-
ally make some applications viable that may
not have been previously, because there’s not
enough product in the world,” he said.
Lithography Gas Expansions With increasing demand for neon from DUV
(deep UV) multi-patterning lithography and
other excimer laser applications, Linde is ex-
panding neon capacity at a newly installed
neon production facility in La Porte, Texas.
Linde works with its customers to supply
mixtures of neon, fluorine, and other gases
for excimer laser patterning applications At
SEMICON West, Linde (Bridgewater, N.J.)
is discussing its expansion of lithography gas
processing capacity at its Medford, Ore. facility.
“By investing in Medford for lithography
gas production, it gives us another site and in-
creases our business continuity plan. We work
with the OEMs to make sure that we are chang-
ing as needed, to make sure that the tools and
the fabs are working optimally,” Adams said.
Besides adding purifica-
tion capacity, Adams said its
continuity planning includes
strengthening Linde’s supply
chain in Europe and manag-
ing a portfolio of third-party
sources.
With more than 60,000
employees worldwide and
around $20 billion in annual
revenues, Linde leads the in-
dustry in rare gases. “We con-
tinue to invest globally in our
own sources, and at the same
time develop additional sup-
ply capacity with our partners,” said Andreas
Weisheit, head of Linde Elec-
tronics. For example, Linde
has more than 35 captive
air separation units (ASUs)
for rare gas production, and
manages a network of external
suppliers.
The major lithography
equipment and chip manu-
facturers work with Linde en-
gineers to develop new tech-
nologies at Linde’s Centers of
Excellence, including a center
for laser gases in Alpha, N.J.
Linde spans the gamut of
rare gas capabilities, includ-
ing the design and manufac-
ture of air separation units
(ASUs) and rare gas extraction equipment,
cryogenic engineering, purification capabili-
ties for neon, krypton and xenon, and high-
volume mixing and blending capabilities.
Rare gas production is a multi-stage pro-
cess, Adams said. For example, a steel com-
pany that needs oxygen will have a Linde air
separation unit onsite to extract the rare gases.
This crude mixture, sometimes referred to as a
soup of materials, is further refined — and in
some cases undergoes cryogenic distillation º
to extract the xenon, krypton and neon.
Because neon is the highest-volume rare
gas, Linde has multiplesneon purifiers strate-
gically located around the world. “That speaks
to our business continuity planning, that we
have these at separate locations. We’re able
to process this crude neon into semiconductor
grade neon. Of course, it’s similar with xenon
and krypton,” he said.
Adams said the neon shortage has been ad-
dressed and supply and demand has come back
into balance. “That can change with new and
different applications. We are starting to see
some tightening in the xenon market, due to
some applications that are coming online that
have a high xenon demand. Which is one of the
reasons why we’re making the investment in
Alpha, New Jersey,” he said.
Linde Electronics will be exhibiting at
SEMICON West, booth number 5952 in the
North hall in the Moscone Center. Its focus
will be on the leadership that Linde Electronics
brings to the semiconductor industry through
such offerings as electronic specialty gases, on-
site solutions, materials recycling and recovery
and SPECTRA® nitrogen plants.
For more information, see The Linde Group
online at www.linde.com/electronics.
Xenon cylinders inside the Linde plant in Alpha, NJ.
Rare gas production is a multi-stage process
Linde Group Announces Rare Gas Capacity Expansions
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