sram a-factors for simple 6t sram cell using microprocessor logic cmos process technology

SRAM A-Factors for Simple 6T SRAM Cell using Microprocessor Logic CMOS Process Technology

020406080

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0.13micron (Intel, IEDM

2000.p.567))

0.13micron (M

otorola, IEDM2000,p.571))

0.18micron (Intel, IEDM

1998,p.197)

0.25micron (Intel, IEDM

1996,p.847)

0.35micron (Intel, IEDM

1994)

0.3micron (M

otorola, IEDM1994)

A-F

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)Average A-Factor = 161.67

DRAM half-pitch (F) A-Factor (A*F2)0.13micron (Intel, IEDM2000.p.567)) 143.70.13micron (Motorola, IEDM2000,p.571)) 146.740.18micron (Intel, IEDM1998,p.197) 172.530.25micron (Intel, IEDM1996,p.847) 164.160.35micron (Intel, IEDM1994) 167.30.3micron (Motorola, IEDM1994) 175.6

0.15, TSMC, VLSI00 152

0.13, Toshiba, VLSI00 148

0.18 (0.13 poly), Motorola, VLSI00, embedded!

85 (or 162 using 0.13)

0.13, IBM, SOI, VLSI00 128

0.13, IBM, bulk, VLSI00 147

0.18, TSMC, VLSI99 136

0.18, IBM, VLSI99 119

0.18, IBM, ISSCC00 131

0.25, UMC, IEDM97 101

0.25, Samsung, VLSI98 102

0.13, Fujitsu, VLSI98

0.25, Motorola, VLSI98

147

150

F, Company, Reference A factor

Virtual Silicon libraries based on United Microelectronics (UMC) processes

A-factors:

0.25 m, high-performance (10 tracks):2-in NAND/NOR: 371INV: 248MUX2: 867DFF: 2106

0.18 m, high-performance (11 tracks), quoted max density = 93.5K gates/mm2, translating to 10.7 m2/gate or 330F2 :

2-in NAND/NOR: 377INV: 251MUX2: 878DFF: 2133

0.15 m, high-density (8 tracks), about 20% smaller than high-performance, quoted max density = 173K gates/mm2, translating to 5.8 m2/gate or 258F2.

2-in NAND/NOR: 307INV: 205MUX2: 717DFF: 1638

If we assume contacted metal pitch = 2.5*F (e.g. MP = 0.625 m for 0.25 m), this gives ~60 MP2 for 2-in NAND/NOR, which is inline with BACPAC calcs

Current recommendations:

SRAM cell size = 150-160F2

Std. Cell size = 375F2??

SRAM overhead: use factor of 1.6 (60% overhead penalty)

These areas don’t include any white-space consideration so the actual packing density should be lower