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ASIC Test
Outline
1 Introduction
2 Fault models
3 Test Generation Flow
4 Design-for-Testability
5 Problems of Testing
6 Conclusions
Introduction
1
Introduction
Goals and Problems of Testing
Types of Tests
Some Definitions of Testing
Verification vs. Testing
Model
Netlist
Chip Implementation/
Synthesis Production
Simulation/Verification Testing
Bug Defect
Verification vs. Testing
Model
Netlist
Chip Implementation/
Synthesis Production
Simulation/Verification Testing
Bug Defect
Goal & Problems of Testing
• Goal
• The goal of testing is to apply a minimum set of
input vectors to each device to determine if it contains
a defect.
• Problem
• ⇒ Apply a set of test vectors to a device and compare
its outputs to the known good response.
• ⇒ The optimum test set will detect the greatest
number of defects that can be present in a device
with the least number of test vectors
Types of Tests
• Exhaustive – apply every possible input vector
• Functional – test every function of the device
• Fault Model Derived – find a test for every modelled fault
Which test type is closest to optimum?
ALU
Consider a 16-bit ALU
• 8 operations
4 arithmetical operations (add, sub, mul, div)
4 logical operations (and, or, xor, inv)
• 2 16-bit operands
a b
c
16 16
16
3 op
Which test type is closest to optimum?
Exhaustive testing
• Will detect 100 % of detectable faults
• Can done automatically
• Requires 235 = 17.179.869.184 test vectors
• Test at 10 MHz would take 57 min 16 s
Which test type is closest to optimum?
Functional testing
• Will detect 100 % of detectable faults
• No algorithmic way to verify that all functional modes have
been tested (designer expertise required)
• Total functional test will take 4(log_ops) × 4(vecs) + 4(arith_ops)× ≈ 20(vecs) ≥ 96 vectors
• Test at 10 MHz would take 9.6 µs
Which test type is closest to optimum?
Modelled Fault Testing
• Will detect 100 % of detectable faults
• Vectors can be generated and analyzed in terms of fault
coverage
• Number of detected defects depends on the quality of the fault
model
• Requires ≈ 40 vectors (for a single-stuck-at-faults)
• Test at 10 MHz would take ≈ 4 µs
Which test type is closest to optimum?
Exhaustive testing
• Requires 235 = 17.179.869.184 test vectors
• Test at 10 MHz would take 57 min 16 s
Functional testing
• Total functional test will take 96 vectors
• Test at 10 MHz would take 9.6 µs
Modelled Fault Testing
• Requires ≈ 40 vectors (for a single-stuck-at-faults)
• Test at 10 MHz would take ≈ 4 µs
Definitions
Fault coverage
Percentage of total faults referring to a fault model for which test
patterns have been generated
Fault coverage = 100 × Number of faults detected by patterns
Total number of faults of the given FM
Definitions cont.
Testability
. . . is determined by controllability and observability.
Definitions cont.
Testability
. . . is determined by controllability and observability.
Controllability
. . . is the capability of controlling the state of a unit.
⇒ Application of patterns
Definitions cont.
Testability
. . . is determined by controllability and observability.
Controllability
. . . is the capability of controlling the state of a unit.
⇒ Application of patterns
Observability
. . . is the capability of observing the state of a unit.
⇒ Reception of test responses
Testability
Tes
t inputs
Tes
t res
ponse
UUT-Environment (Rest of Device)
Unit-Under-
UUT inputs UUT outputs
Test
Tester
Testability
Controllability Observability
Definitions cont.
Sensitization
Process of driving the circuit to a state where the fault causes an
actual erroneous value at the point of the fault
Propagation
Process of driving the circuit to a state where the error becomes
observable at the primary outputs
Justification
Process of determining the input combination necessary to drive
an internal circuit node to a specific value
Fault models
2 Fault models
Types of Faults
Stuck-at Fault Model
Stuck-open Fault Model
Bridging Faults
Delay Fault Model
IDDQ Model
Types of Faults
Functional faults (bugs)
. . . are defined in conjunction with a functional model.
⇒ Introduced in design process
⇒ Shall be detected during simulation/verification
⇒ Require a feasible test bench
⇒ No automated test generation
Types of Faults
Structural faults (defects)
. . . are defined in conjunction with a structural model of the system
and a logical fault model.
⇒ Introduced during fabrication
⇒ Not detectable during simulation, detected via testing
⇒ Automated test generation is possible, since the function of the
system in case of a fault of the given fault model can be
determined.
Goals of Fault Modelling
• Fault model
• Abstract model of a defect, i.e. something that can go
wrong during the fabrication of a system.
• Goal of fault models
• Model defects at the highest level of abstraction
possible
• Model as high a percentage as possible of the actual
physical defects that can occur
Stuck-at Fault Model
Stuck-at Fault Model
• Stuck-at-0: A net is permanently connected to GND
s-a-0
GND
• Stuck-at-1: A net is permanently connected to VDD
VDD
s-a-1
Stuck-at Fault Model Cont.
x s-a-0 (1)
x2
• Output stuck-at fault model:
x = s − a − 0 /1 ⇒ x = x1 = x2 = s − a − 0 /1
s-a-0 (1) x1 x
x2
• Input stuck-at fault model:
x1 = s − a − 0 /1 ≠> x2 = s − a − 0 /1
x1
Single vs. Multiple Stuck-at Fault Model
Single stuck fault model
• Assumes that only one wire is permanently stuck
Reasonable number of faults 2n (n number of circuit nodes)
Efficient algorithms for ATPG and fault simulation are well
developed
Covers about 90% of possible manufacturing defects in CMOS
circuits
Other fault models can be mapped into stuck-at faults
Does not cover all defects
Does not consider that faults can mask each other
Single vs. Multiple Stuck-at Fault Model
Multiple stuck fault model
• Assumes that 2 or more wires are permanently stuck
Fault coverage higher than for single stuck-at fault model
Does not cover a significantly larger number of defects than
single stuck-at
Large number of faults 3n − 1 (n number of circuit nodes)
Algorithms for ATPG and fault simulation are much more
complex
Stuck-open Fault Model
Stuck-open Fault Model
• A physical line is broken (high
impedance)
• Such breaks result in memory effects for
some undetermined discharge time
Covers physical defects not covered by
stuck-at fault models
Large number of tests
Algorithms for ATPG and fault simulation
are much more complex
Requires a low level circuit description for
faults within logic elements
A
B
VDD
GND
F Line
break
Bridging Faults
Bridging Faults
• Two nodes of a circuit are shortened together
• Usually assumed to be a low resistance path
• Three classes
Bridging within a logic element
Bridging between logic nodes without feedback
Bridging between logic nodes with feedback VDD
GND
A
B
Bridging
F
Bridging Faults
• Two nodes of a circuit are shortened together
• Usually assumed to be a low resistance path
• Three classes
Bridging within a logic element
Bridging between logic nodes without feedback
Bridging between logic nodes with feedback
Bridging
Bridging Faults
• Two nodes of a circuit are shortened together
• Usually assumed to be a low resistance path
• Three classes
Bridging within a logic element
Bridging between logic nodes without feedback
Bridging between logic nodes with feedback
Bridging
Bridging Faults
• Two nodes of a circuit are shortened together
• Usually assumed to be a low resistance path
• Three classes
Bridging within a logic element Bridging between logic nodes without feedback
Bridging between logic nodes with feedback
Covers a large number of physical defects – 30 % of all defects
are bridging faults
ATPG algorithms are very complex
Requires a low level circuit description for bridging faults
within logic elements
Delay Fault Model
Delay fault model
• The logic function of the UUT is error free
• Some physical defect (e.g. process variation) makes some
delays greater than some defined bounds
• Two delay fault models:
Gate delay, or transitional fault model
Path delay fault model
Transitional delay fault model
• A logical model for a defect that delays either a rising or
falling transition
Slow-to-rise
Slow-to-fall
011
000
001
011
Slow-to-rise
Fault free
• Tests are similar to stuck-at fault tests
Initialize a line to 0 and test for a s-a-0 fault to detect
slow-to-rise transition fault
• Two patterns are required: initialization/launch and transition
detection/capture
Reasonable number of faults 2n (n number of nodes)
Faulty delays of gates can be compensated by other gates
Path delay fault model
Delay = 2
Delay = 2
Delay = 6
Delay = 2
B
A
C
E
Z
Delay = 2 D
Delay = 2
• The total delays of a path from its inputs to its outputs exceed
some maximum value
Detects more faults than transition delay fault model
Can be used with more aggressive statistical design
philosophy
Large number of possible paths in the circuit
Algorithms for ATPG are complex
IDDQ Model
IDDQ Model
defect
no defect
I
O I
VDD
GND
O
defect
• Many defects in CMOS circuits can be detected by current
measuring techniques
• A fully static CMOS gate consumes significant current only
when switching
• Most physical defects will raise the quiescent current for MOS
devices (IDDQ) by several orders of magnitude
IDDQ Model and Testing
Test generation is easier since faults must be activated, but
not propagated to a primary output
IDDQ testing detects defects not modelled by stuck-at fault
models
Normal IDDQ is very low ⇒ precise measurement required
Measurement takes a significant amount of time
Problematical in combination with small cell geometries
Test Generation Flow
a-s-a-0
a-s-a-1
b-s-a-0
b-s-a-1
c-s-a-0
c-s-a-1
d-s-a-0
d-s-a-1
...
Generate
list of
undetected
faults
Select
undetected
fault for test
generation
Generate a test
vector for that
fault
Generate list of
other faults
detected by
that vector
a-s-a-0
c-s-a-1
d-s-a-1
h-s-a-0
l-s-a-1
m-s-a-1
s-s-a-0
...
Select a fault
for test
generation
101110...
X a-s-a-0
a-s-a-1
b-s-a-0
b-s-a-1
c-s-a-0
X c-s-a-1
d-s-a-0
X d-s-a-1
...
Circuit-Under-
Test
a-s-0
Yes Exit All faults detected or
proven untestable?
Test Generation Flow
a-s-a-0
a-s-a-1
b-s-a-0
b-s-a-1
c-s-a-0
c-s-a-1
d-s-a-0
d-s-a-1
...
Generate
list of
undetected
faults
Select
undetected
fault for test
generation
Generate a test
vector for that
fault
Generate list of
other faults
detected by
that vector
a-s-a-0
c-s-a-1
d-s-a-1
h-s-a-0
l-s-a-1
m-s-a-1
s-s-a-0
...
Select a fault
for test
generation
101110...
X a-s-a-0
a-s-a-1
b-s-a-0
b-s-a-1
c-s-a-0
X c-s-a-1
d-s-a-0
X d-s-a-1
...
Circuit-Under-
Test
a-s-0
Ye
s All faults detected or
proven untestable?
Exit
Adequate
fault coverage?
Ye
s
Redesign/DfT-
insertion
Test Generation Flow
• Test vectors developed by the design team often must be
significantly modified by the test team since the vectors are
incompatible with Automatic Test Equipment (ATE)
Overflow of scan-data, format-data, or timing-data
memory
Vectors set is not compact enough to fit in pattern
memory
Vectors include comparison with tristate values
Design-for-Testability
4 Design-for-Testability
Definition of Design-for-Testability
Structured DfT – Scan Design
Built-In Self-Test (BIST)
On-line Testing
Design-for-Testability
The goal of Design-for-Testability
. . . is to increase the ease with which a device can be tested.
⇒ Increase the controllability and observability of internal points.
Categories of Techniques
• Ad-Hoc
Partitioning
Test points
• Structured Techniques
Scan Design
Boundary Scan
Ad-Hoc DfT
Device-Under-Test
Ad-Hoc DfT
Module
1
Module
3
Module
2
• Decompose the system into subcomponents
Ad-Hoc DfT
Module
1
Module 2
TDI1
TEN
TDI2
Module
3
TDO1
TDO2
• Decompose the system into subcomponents
• Add control and observation points
Structured DfT – Scan Design
Scan test
• Make a FSM testable by making the internal state
variables controllable and
observable
• Replacing latches and flip-flops by their scannable
counterparts
• Connect latches and
flip-flops to shift-registers
• Provide a tester interface
(SEN, SDI, SDO)
• Test: Shift vectors in, apply 1 functional clock cycle,
shift response out
SI
SO
MU
X
SE SET
RS
D
SI
Q
Q=SO
CK
Q D
Q RST
SET
Scan test
• Make a FSM testable by making the internal state
variables controllable and
observable
• Replacing latches and flip-flops by their scannable
counterparts
• Connect latches and
flip-flops to shift-registers
• Provide a tester interface
(SEN, SDI, SDO)
• Test: Shift vectors in, apply 1 functional clock cycle,
shift response out
SI1
SO1
SI2
SO2
SI3
SO3
Level Sensitive Scan Design (LSSD)
• Used to realize scannable latches
• Introduces a second latch used to avoid transparency
• Requires 2 additional non-overlapping shift clocks
L2 L1 TCK1
SI
D
C
Q
TCK2
SO
Level Sensitive Scan Design (LSSD)
• Used to realize scannable latches
• Introduces a second latch used to avoid transparency
• Requires 2 additional non-overlapping shift clocks M
UX
SI
D CK
TCK2
Q
SO
SE
RS
SET
D Q
G RST
SET
SET
D Q
G RST
MU
X
TCK1
L2
L2
L2
Q1
Q0
Q2
SO
SI
C
D1
D2
D0
TCK1
TCK2
S I
TC K 1
L1 D
C
S I
TC K 1
L1
D
C
S I
TC K 1
L1
D
C
TC K 2
TC K 2
TC K 2
LSSD – Design Rules
1. All internal storage is implemented in hazard-free polarity-hold
latches
2. The latches are controlled by two or more non-overlapping
clocks such that latches that feed one another can not have
the same clock
3. It must be possible to identify a set of clock primary inputs
from which the clock inputs to to shift-register latches (SRLs)
are controlled either through simple powering trees or through
logic that is gated by SRLs and/or non-clock primary inputs
4. Clock primary inputs my not feed the data inputs to latches
either directly or through combinational logic, but may only
feed the clock input to the latches or the primary outputs
Boundary Scan
Source: Application-Specific Integrated Circuits - Michael J. S. Smith
Boundary Scan Cell
Source: Application-Specific Integrated Circuits - Michael J. S. Smith
TAP Controller
Source: Application-Specific Integrated Circuits - Michael J. S. Smith
Boundary Scan – Modes
• Normal mode Mode=0: Data
passes from IN to OUT
• Scan mode Shi f t=1 ,
Clock=scan clock: Serial
data is shifted in from SIN
and to SOUT
• Capture mode Shi f t=0 , Clock=std clock: Data on
the IN line is clocked into QA
• Update mode with QA
loaded, Mode=1: Data in QA
is applied to OUT
TDI
MU
X
Application Logic
Optional:
BIST registers
Scan registers
T
A
P Bypass Regs.
Instr. Regs.
Op. Regs.
SI
SO
TMS
TCK
TDO
Boundary-scan cell I/O Pad
Boundary-scan path
MU
X
IN
SIN
D Q
QA
D Q
QB
MU
X
OUT
SO
Shift Clock Update
Advantages of scan technique
Transforms the testing problem from one of sequential circuit
testing to one of combinational testing
Can be used to test for a variety of fault models (stuck-at,
bridging, delay faults, IDDQ tests)
Eases functional testing due to additional controllability and
observability
Good diagnosis capabilities
Area and speed overhead due to scan cells
Limited at-speed testing
Clock generation and distribution for LSSD
Built-In Self-Test (BIST)
Built-In Self-Test
• Perform at-speed tests of internal IPs
• Collecting each output response and off-loading it for
comparison is too inefficient to be practical
⇒ Compress the entire output stream into a single
signature value
⇒ Evaluate and analyze signature at the end of the test
Built-In Self-Test
output input Tout Ten
TPG
TRA
UUT
MU
X
• Test-Pattern-Generator (TPG) generates patterns for the
unit-under-test (UUT)
• Test-Response-Analyser (TRA) receives the output of the UUT
and generates a signature
Built-In Self-Test – TPG
D Q
R
D Q
S
D Q
S
rst
clk
• Implemented using a simple Linear-Feedback-Shift-Register
(LFSR)
• Generates all possible values except →0
• Often made scannable for setting an initial seed
BIST – Canonial Form of LFSRs and MISRs
+
c1
+
c2 cn-1
+
D Q
Q1 Q2 Q3 Qn
D Q D Q D Q
cn
(a) LFSR Type 1
cn-1 cn-2 cn c1
+ D Q +
Q1 Q3 Qn
D Q +
Q2
D Q D Q
(b) LFSR Type 2
P (x) = 1 + c1x + c2x2 + . . . + cnxn
Built-In Self-Test – TRA
D Q
R
D Q
S
D Q
S
Tout
Input data
rst
clk
ienable
• Implemented using a Multi Input Signature Register (MISR)
• Input enable signal for excluding undesirable response
vectors (e.g. that includes X values)
• Made scannable for evaluation of the stored pattern
Signature Analysis
• Based on the concept of cyclic redundancy checking (CRC)
• Choose ci, such that the possibility of masking faults is
minimized
+
cn-1
+
cn-2 cn c1
+ D Q
Q1 Q2 Q3 Qn
D Q D Q D Q +
D1 D2 D3 Dn
(c) MISR
Signature Analysis
• Based on the concept of cyclic redundancy checking (CRC)
• Choose ci, such that the possibility of masking faults is
minimized
D Q
Q
D Q
Q
D Q
Q
D Q
Q
MU
X
Q1 Q2 Q3
Q4=SO
D1 D2 D3 D4 B1
B2
SI
(d) BILBO
BIST with LUTs
• Use look-up tables in case
predefined patterns are required
• Can be combined with LFSRs to
keep the overhead low, e.g.
Generate frame via LUT
Generate payload via LFSR
Pattern
Response
MISR Signature
Pattern-LUT
Test enable
Counter
Pattern address
MUX
MISR
UUT
Datain
Dataout
BIST with LUTs
• Use look-up tables in case
predefined patterns are required
• Can be combined with LFSRs to
keep the overhead low, e.g.
Generate frame via LUT
Generate payload via LFSR
Pattern
Response
Test enable
MUX
UUT
Datain
Dataout
Address
Pattern-LUT
Counter
Response
LUT
Comparator
Fault
Hierarchical BIST
TEn
Din Dout
TEn TEn TEn
IP
IP
Tester Interface
BIST Controller
IP IP
MU
X
MU
X
MU
X
TPG
TPG
TPG
TPG
TPG
TPG
TPG TPG
IP
• Divide and conquer
• Insert global test as well as local test capabilities
Advantages of BIST
Can be used in case of synchronization problems with tester,
e.g. for heterogeneous systems (GALS, asynch. circuits)
Can be used to perform at-speed tests
Detects transient and intermittent faults
Limited diagnosis capabilities
Faults within check circuitry may reduce yield
On-line Testing
On-line Testing
• Introduce redundant logic to perform on-chip tests during
normal operation
• Predictor-Circuits: Usage of error-detecting (EDC) (or even
-correcting (ECC)) codes
• Watchdog circuits: Often used in case the UUT has an
invariant property
Unit-Under-Test
Generator
Predictor Com
para
tor
input output
fault
(e) Predictor-Circuits
Unit-
Under-
Test
fault
WatchDog
(f) Watchdog
On-line Testing – An example
• Arithmetic operations (addition, subtraction, multiplication)
can be checked through residue class arithmetic modulo p by
using the following equations:
On-line Testing – An example
On-line Testing – An example
c = a b
n n
k
r2 = < e >p
m
f = (r1 == r2)?
2
f
a b
c
< a >p < b >p
m m
Predictor
r1 = << a >p < b >p>p
m
Generator
Comparator
Comparators
• Use self-checking comparators for test response generation
a
f
a’
b
b’
f'
Advantages of On-line testing
Allows at-speed tests
Detection of intermittent and transient faults
Allows graceful degradation techniques
Additional hardware overhead for check components
Faults within check circuitry may reduce yield
Redundant logic and undetectable faults
• Redundant logic introduces undetectable faults
• Additional DfT (control and observation points) may help
FF
FF
FF
Voter
x
Clk
s-a-x
Conclusions
Summary of DfT-Techniques
Scan Test BIST On-line Test Observability & controllability
Fault coverage
Influences in area
Influences in
Performance
At-speed testing
Diagnose
Capabilities
Test time
Conclusions
• Integrate DfT-Techniques into design specification
• Divide and Conquer
• Make use of hierarchical DfT techniques
• Functional tests are not sufficient!
• Insert scan as a prerequisite for performing structural tests!
• Be aware of test problems with redundant logic! (Requires
additional DfT)
Thank you for your attention!
References
• RASSP Educational & Facilitation Program, Test Technology
Overview, h t t p : / /www.cedcc .psu.edu/ee497i / rassp_43 /s ld001.htm ,
1998
• M. Abramovici, M.A. Breuer and A.D. Friedman: Digital
Systems Testing and Testable Design, 1990
• Michael Gössel and Steffen Graf: Error Detection Circuits,
1993
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