An Efficient Baugh-Wooley Architecture forSigned & Unsigned Fast Multiplication

Pramodini MohantyDepartment of Electrical & Electronics Engineering,

Noida Institute of Engineering & Technology (NIET), Greater Noida (UP)Email-id: pramodini swain@yahoo.co.in, pamina2009@gmail.com

Abstract- This paper presents an efficientimplementation of a high speed multiplier using the shift andadds method of Baugh-Wooley Multiplier. This parallelmultiplier uses lesser adders and lesser iterative steps. As aresult of which they occupy lesser space as compared to theserial multiplier. This is very important criteria because inthe fabrication of chips and high performance systemrequires components which are as small as possible.Experimental results demonstrate that the proposed circuitnot only improves the accurate performance but alsoreduces the hardware complexity and also less powerconsumption that is dynamic power of 15.3mW andmaximum clock period of 3.912ns is required which is veryefficient as compared to the reference paper.

Keywords- Baugh-Wooley Multiplier, Pipeline resister,Power Efficient, Carry Save Adder.

I. INTRODUCTIO

Multiplication involves two basic operations- thegeneration of the partial product and their accumulation[5]. Therefore, there are possible ways to speed up themultiplication that reduces the complexity, and as a resultreduces the time needed to accumulate the partialproducts. Both solutions can be applied simultaneously.

Baugh-Wooley Two's Complement SignedMultiplier: Two's Compliments is the most popularmethod in representing signed integers in ComputerSciences. It is also an operation of negation (Convertingpositive to negative numbers or vice -versa) in computerswhich represent negative numbers using two'scomplements. Its use is so wide today because it does notrequire the addition and subtraction circuitry to examinethe signs of the operands to determine whether to add orsubtract. Two's complement and one's complement

-~ Positive -~ Nezatrve IntesersIntegers Sign & zs is

MO!!llimck Complement Comnlcmcnt-{) 0000 -0 1000 ---- 1111-1 0001 -1 1001 III 1 1110-) 0010 -2 1010 Ilia 1101-3 0011 -3 1011 1101 1100-~ 0100 -.l 1100 1100 lOll-; 0\01 -5 1101 1011 1010-6 OllO -6 1110 1010 1001-, Olll -; n n 1001 1000-8 ---- -S ---- 1000 ----FIG I(a): Two's complement & one's complement representation

representations are commonly used since arithmetic unitsare simpler to design. Fig.I shows Two's & One'scomplement representation.

Baugh-Wooley Two's complement Signednumbers: Baugh-Wooley Two's complement Signedmultipliers is the best known algorithm for signedmultiplication because it maximizes the regularity of themultiplier and allow all the partial products to havepositive sign bits [3]. Baugh-Wooley technique wasdeveloped to design direct multipliers for Two'scomplement numbers [9]. When multiplying Two'scomplement numbers directly, each of the partial productsto be added is a signed number. Thus each partial producthas to be sign extended to the width of the final product inorder to form a correct sum by the Carry Save Adder

a, a3 a1 al ao

A, A3 A1 XI AO

a,xo a3Ai! a1AO alxo aoxo

a,xI a3xI ~XI alxl aoxi

a,x, a3x, a,x1 alx1 aOx1

a,x3 a3x3 a1x3 alA3 aOA3

a,x, a3x, alA, alA, aox,

P9 Ps P7 P6 PI p, P3 p, PI Po

FIG I (b): 5*5 unsigned multiplications

a, al a, al aox, X3 X, XI Xo

-a.xo alAo a,xo ClIXO GOAO

-04Xl a3xI alAI alAI aoxi-0 •.\, a3x, alA, alA, aOAl

-a.x3 a3x3 alA) alA) aOA)a4;:(, -a3A. -alA, -alA. -aox.

P9 Ps p, P6 PI p, P3 p, PI Po

FIG I (c): 5*5 signed multiplications

(CSA) tree. According to Baugh-Wooley approach, anefficient method of adding extra entries to the bit matrixsuggested to avoid having deal with the negativelyweighted bits in the partial product matrix. In fig I (a) & (b)partial product arrays of 5*5 bits Unsigned and Signed bitsare shown.

Figure I (c) shows how this algorithm works in thecase of a 5x5 multiplication. The first three rows are

18 NIET Journal of Engineering & Technology, Vol. 1, Issue 2, 2013

referred to as PM (partial products with magnitude part)and generated by one NAND and three AND operations.The fourth row is called as PS (partial products with signbit) and generated by one AND and three NANDoperations with a sign (with magnitude part) andgenerated by one NAND and three AND operations.Consider the partial products of PM. Suppose b2= bOinfigure1 (c). Then the third row can be obtained by shiftingthe first row by 2 bits. Likewise, shift operation can beused to obtain a partial product of different bit level as insign magnitude multiplication.

Baugh- Wooley schemes become an area consumingwhen operands are greater than or equal to 32 bits. The restof the paper is organised as follows. The Baugh-Wooleyarchitecture is explained in section 2. Implementationresults in terms of power, area, and speed 4 bit multipliersand comparison are presented.

II. BAUGH-WOOLEY ARCHITECTURE

Hardware architecture for Baugh-Wooley multiplier isshown in fig 2. It follows left shift algorithm. ThroughMUX (multiplexer) we can select which bit will multiply.

Suppose we are adding +5 and -5 in decimal we get '0'.Now, represent these numbers in 2 's complement form,and then we get +5 as 0101 and -5 as 1011. On addingthese two numbers we get 10000. Discard carry, then thenumber is represented as '0' .

G. a3 G1 at aox. X3 x., Xl Xo

G.Xo a3xo a,Xa alAo aoxoa.xl a3xI a, Xl alxl aOxl

G.X1 a3x., G1X., alA., GOXl

G.X3 a3x3 G:l:X3 GtX3 aOx3a.x. a3x, a2x, alx, aox,

P9 Ps p, P6 Ps P. P3 P, PI Po

FIG! (d): 5*5 Multiplication Example of Baugh-Wooley Architecture

[ Multiplicand

----.;.--;7 Enable :.- _.. - _. - .-_. - - _ .. - - - - - ..- - _ ..- _ •.-- - -~

Mux ~···-S·eiecr-··.... ·__·············_-1

c_ ~de, c. !o. ex';ept in

last cycleL- --' k + 1

Fig 2(a): Signed 2's-Complement Baugh-Wooley Hardware Multiplier

Baugh-Wooley Multiplier (5):

Baugh- Wooley Multiplier is used for both unsignedand signed number multiplication. Signed Numberoperands which are represented in 2's complementedform. Partial Products are adjusted such that negative signmove to last step, which in turn maximize the regularity ofthe multiplication array. Baugh- Wooley Multiplieroperates on signed operands with 2's complementrepresentation to make sure that the signs of all partialproducts are positive.

Here are using fewer steps and also lesser adders. HereaO, a l, a2, a3& bO, b1, b2, b3 are the inputs. I am gettingthe outputs that are pO, pL. p7. As I am using pipe liningresister in this architecture, so it will take less time tomultiply large number of 2 's complement but less than32 bit. Above 32 bit Modified Baugh-Wooley Multiplieris used.

Fig 2(b): Block diagram ofa 4*4 Baugh-Wooley multiplier

III. IMPLEMENTATION RESULTS AND COMPARISONS

In this paper, I use 4-bit pipelined multipliers and areimplemented in VHDL and logic simulation is done byusing ModelSim Designer and the synthesis is done usingXilinx ISE 8.2i of Device 4VFX20FF672-12. Thesynthesis result of 4-bit pipelined Baugh-Wooleyarchitecture is shown in table above of the reference paperand my paper.

In my paper, I am using Brent-Kung adder (BKadder), an advanced design prefix adder, which is a verygood balance between area and power cost and also it willpresent better performance. This adder has a complexcarry and inverse carry tree. A tree can be divided into 2

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types that is a tree and an inverse tree. The upper tree basedon periodic power of 2. The inverse tree is offset 1,beginning from the bottom of the matrix and expandingoutwards at power of2.

The results show that the Baugh-Wooley multiplierhas increased speed since clock period is only15.861ns.Pipeline stages further improve the Baugh - Wooleyarchitecture speed. Number of LUTs represents the arearequired for implementation.

The number of LUTs required in Baugh-Wooleyarchitecture is 30 compared to 32. The fan-out of themultiplier architecture is also given which directly givesthe possibility ofthe multiplier to form large circuits. Thiscan be extended to the pipelined multiplier architecturealso to verify the parameters. Latency and speed are theimportant factors with pipe lining under consideration.The synthesis results of 4-bit pipelined multipliers areshown in Table 2. Power consumption in Baugh-Wooleymultipliers is minimum compared to other conventionalmultiplier units. So it clears that the signed binarymultiplication through Baugh-Wooley multiplication issuited for large multiplier implementation. Theimprovements in constraint can be used to make Baugh-Wooley multiplier more efficient. The fan-out of themultiplier architectures are also given which directlygives the possibility of the multiplier to form largecircuits. This can be extended to the pipelined multiplierarchitecture also to verify the parameters. Latency andspeed are the important factors with pipelining underconsideration. The synthesis results of 4-bit pipelinedmultipliers are shown in Table 2. The pipeline constraint

Fig 3: Synthesis Report of Baugh- Wooley Architecture

Output: Simulation Result for Baugh- Wooley Architecture:

Fig 4: Simulation Result for Both Unsigned Numbers Multiplication

TABLE 1SYNTHESIS RESULTS OF DIFFERENT 4-BIT PIPEUNED

MULTIPLIER ARCHITECTURES

Multiplier Numberof Fanout Clock- PowerArchitecture LUTS Period Dissipation

(ns) (mW)

Add-and- 74 18 8.939 68.89Shift

Baugh- 32 104 15.029 67.84Wooley

TABLE 2MY SYNTHESIS RESULTS OF DIFFERENT 4-BIT

PIPELINED MULTIPLIER ARCHITECTURES

Multiplier Numberof Fanout Clock- PowerArchitecture LUTS Period Dissipation

(ns) (mW)

Add-and- 74 18 8.939 68.89Shift

Baugh- 30 46 3.921 15.3Wooley

increases the speed of the multiplier considerably with aincrease in power consumption. For the Baugh-Wooleymultipliers, the clock period reduces to 3.321 ns as a resultof pipeline registers implemented. This improves thespeed which may reduce due to the BK adder which I usedin my architecture. The maximum delay for thisarchitecture is 2.143ns. I am using 65 Flip Flops out of17088 and maximum frequency is 527.037MHz, which isa good sign. The incorporation of the pipeline multipliersthus can be effectively done to make the chip efficiently

20 NIET Journal of Engineering & Technology, Vol. 1, Issue 2, 2013

Fig. 5 Simulation Result For both Signed Number Multiplication

reconfigurable among the two reconfiguration modes andthis work is in progress. The possibility of otherreconfiguration constraints is under work and theimplementation of the reconfiguration modes accordingto these constraints are the future work.

IV. CONCLUSIONS

An efficient multiplier to deal with the latencyproblem is proposed. This paper presents a comparisonbetween various multiplier architectures with area, speedand power as the main constraints. It is observed that theBaugh-Wooley architecture gives optimized values forvarious constraints and hence suited for long bitmultiplication up to less than 32 bit. The pipe liningresister techniques are used to improve the multipliercharacteristics.

REFERENCES

[1 J Power Reduction Techniques for Ultra-Low-Power Solutions. byVirage Logic Corporation.

[2J R.M.Badghare, S.K.Mangal, R.B.Deshmuk:h, R. M. Patrikar(2009), "Design of Low Power Parallel Multiplier", Journal ofLow Power Electronics, vol. 5, no. I,ApriI2009,pp. 31-39.

[3J A. Dandapat, S. Ghosal, P. Sarkar, D. Mukhopadhyay (2009), "A1.2- ns l ox 16-Bit Binary Multiplier Using High SpeedCompressors", International Journal of Electrical, Computer,and Systems Engineering, 2009, pp. 234-239.

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[5J Jin-Hao Tu and Lan-Da Van, "Power-Efficient PipelinedReconfigurable Fixed-Width Baugh-Wooley Multipliers," IEEETransactions on computers, vol. 58, Nno. 10, October 2009.

[6J C. R. Baugh and B. A. Wooley, "A Two's Complement ParallelArray Multiplication Algorithm," IEEE Transactions onComputers, vol. 22,pp.1045~1047, December 1973.

[7J H. Eriksson, P. Larsson-Edefors, M.Sheeran, M. Sjalander, D.Johansson, and M.Sch6lin, "Multiplier Reduction Tree withLogarithmic Logic Depth and Regular Connectivity," in IEEEInternational Symposium on Circuits and Systems, May 2006.

[8J E.E.Swartzlander, Jr., "Truncated multiplication withapproximate rounding," in Proc. 33rd Asilomar Conference onSignals, Systems, and Computers, 1999, vol. 2, pp. 1480-1483.

[9J J. Di and J. S. Yuan, "Run-time reconfigurable power-awarepipelined signed array multiplier design," in Proc. IEEEInternational Symposium on Signals Circuits, and Systems, July2003, vol. 2, pp. 405-406.

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Pramodini Mohanty received theB.Tech. degree in electrical engineeringfrom Utkal University, Orissa, in 2004.She is currently working towards herM.Tech. degree in VLSI Design atN.I.E.T, Greater-Noida. Her researchinterests include fast multiplication

named Baugh-Wooley Architecture and other electroniccircuits. Presently she is working as a faculty member inN.I.E.T, Greater-Noida.

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