an efficient methodology for achieving optimal power and speed in asic
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ASIC is a Unique Product. An ASIC (“a-sick”) is an application- specific
integrated circuit
ASICs are the standard parts, used to design microelectronic systems
ASIC is an integrated circuit customized for particular use, rather than intended for general purpose use.
s-o-c System on chip
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Customer Specification
Semi -Custom ASIC
Gate Array ASIC
FPGA ASIC
Fab-Less Design House
Full Custom
ASIC
Logic Design/Front End
Physical Design/Back End
Gate Level Net List
Physical layout/Masks
Foundry/Processing
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PHYSICAL DESIGNTransformation of a circuit design into
physical representation for manufacturing
The circuit design is described through a netlist.
The end product from a physical design is a layout which is design rule, connectivity and timing correct.
The layout data is sent to mask shop to generate masks for fabrication
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PHYSICAL DESIGN METHODOLOGY
Read in Netlist(Verilog or Edit)
Floorplan (Macro Placement,
IO Placement,P/G routing
Flatten the Netlit
Insert Clock Trees(if necessary)
Place & Route DRC/LVS
Static Timing Verification
Back- AnnotationSPEF/SDF
Modify Netlistif Timing Doesn’t
meet
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• IMPLEMENTATION
1. SOC Encounter :Floor planning, placement and routing.
2. Nano router : Optimize routing for timing, area, power and manufacturability.
• ANALYSIS1. Common timing
engine(CTE): Static timing analysis.
2. Voltage Storm: Power analysis.
3. Celtic: Crosstalk analysis.
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Today some of the most powerful microprocessor chips can dissipate 100-150Watts,for an average power density of 50-75 Watts per square centimeter.
This Power density not only presents packaging and the cooling challenges; it also can pose problems for reliability, since the mean time to failure decreases exponentially with temperature.
In addition, timing degrades with temperature & leakage increases with temperature.
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From The International Technology Roadmap for Semiconductors (ITRS) makes the following predictions:
Today, the power consumption of ICs is considered one of the most important problems for high-performance chips, as well as for portable devices. For the latter, the problem is due to the limited cell battery lifetime, while it is the chip cooling for the first case.
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For battery operated devices the distinction between power & energy is critical.
Power is the instantaneous power in the device. Energy is the integral of power over time.
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Power DissipationKinds of power dissipation:
Sources of dynamic power consumption:
Switching Power: The charging and discharging of external capacitive load on output of a cell.
Internal Power: Short circuit (crowbar) current that flows through Pmos - Nmos stack during a transition
Dynamic power is the power consumed when the device is active – that is, when signals are changing values.
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Switching Power
clockddefdyn fVCP 2
Crowbar Current
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Static power is the power consumed when the device is powered up but no signals are changing value. In CMOS devices, static power consumption is due to leakage.
Power Dissipation Contd.
Estimating leakage/static power : Leakage power is emerging as a key design
challenge in current and future CMOS designs. Since leakage is critically dependent on operating temperature and power supply, we present a full chip leakage estimation technique which accurately accounts for power supply and temperature variations
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There are four main types of leakage currents in a CMOS gate
Power Dissipation Contd.
Sub – threshold Leakage (ISUB): The current which flows from drain to the source current of a transistor operating in weak inversion region.Sub – threshold leakage occurs when the CMOS gate is not turned completely OFF. For a good approximation its value is given by,
th
TGS
nV
VV
thoxSUB eL
WVCI
2
where, W & L >> dimensions of the transistor Vth >> threshold voltage kT/q (25.9 mV
at room temperature) n >> function of the device fabric process
& ranges from 1.0 to 2.5
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Power Dissipation Contd.
Gate Leakage (IGATE): The current which flows directly from the gate through the oxide to substrate due to gate oxide tunneling and hot carrier injection. Gate leakage occurs as a result of tunneling current through the gate oxide. At future nodes, high-k dielectric materials will be required to keep gate leakage in check. This appears to be the only effective way of reducing gate leakage.
Gate Induced Drain Leakage (IGIDL): The current which flows from the drain to substrate induced by a high field effect in the MOSFET drain
caused by high VDG.
Reverse Bias Junction Leakage (IREV): Caused by minority carrier drift and generation of electron or hole pairs in the depletion regions.
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Clock Gating
Gate Level Power Optimization
Multi-VDD
Multi-Vt
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As geometries have shrunk to 130nm to 90nm and below, using libraries with multi-vt has become a common way of reducing leakage voltage.
Scale down the threshold voltage for low voltage low power circuits to increase performance VT ↓ = Delay ↓ + Ileakage ↑ Low -VT : Provides high performance VT ↑ = Delay ↑ + Ileakage ↓ High -VT : Reduces subthreshold leakage
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Low threshold voltage cell technique( Lvt)
High threshold voltage cell technique( Hvt)
Standard/Normal threshold voltage cell technique( Rvt)
Mixed flow design
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Use mix of different Vt cells in a single design
Design Libraries – Multiple libraries at different Vt options Optimization Tools – Optimization tools employ different Vt cells • For timing critical paths, use low Vt cells
(LVT) • For non timing critical paths, use high Vt
cells (RVT)– Meets performance target, while minimizing
leakage power…
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What is the best way to optimize the design withmultiple libraries to meet timing, area and powerdesign goals?
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Baseline – Only RVT library (Optimized for timing and area,
but not leakage power) – Only LVT library (Optimized for timing and area,
but not leakage power) One pass synthesis – Both RVT and LVT library in a single run (MVT
synthesis) – Multiple Vt optimization effort level – low, medium,
high Two pass synthesis – Initial synthesis with RVT followed by both RVT and
LVT libraries for timing closure (RVT/LVT synthesis) – Initial synthesis with LVT followed by both RVT and
LVT libraries for power recovery (LVT/RVT synthesis)
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Power is the next frontier for VLSI designs – Leakage power is exponentially increasing! Use of multiple libraries with different Vt is
inevitable to meet the performance and area goals, while minimizing leakage power.
– Multiple Vt libraries are solution for minimizing leakage power
– Number of different Vt libraries are increasing to meet the demand