an example mpc8540-based compactpci reference design · 2016-11-23 · mba1 ras* mcontrol0 mdm8...
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© Freescale Semiconductor, Inc., 2004. All rights reserved.
Freescale SemiconductorWhite Paper
CompactPCI™ is a very high performance industrial bus based on the standard PCI electrical specification in a rugged 3U or 6U Eurocard packaging.Compared to standard desktop PCI, CompactPCI supports twice as many PCI slots (8 versus 4) and offers a packaging scheme that is much better suited for use in industrial applications.Due to its extremely high bandwidth, the CompactPCI bus is particularly well suited for many high speed data communication applications such as servers, routers, converters and switches. Full CompactPCI specifications are available from the PCI Industrial Computer Manufacturers Group at www.picmg.org.
This White Paper describes an example design of a compact PCI reference system based on the latest MPC8540 integrated PowerPC™ processor.
1 IntroductionThe MPC8540 is a member of the latest PowerPC processor based family of integrated devices. It is based on a 32-bit implementation of the “new” Book E Embedded PowerPC processor core. This core is known as the e500 core and supports the features detailed in the PowerPC Book E architecture definition.
This core has several features that differ from other PowerPC cores which are known as “Classic PowerPC.” Details of the differences are described in a separate Application Note.
MPC8540cPCIWPRev. 1, 11/2004
Contents1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12. Example Reference CompactPCI Design . . . . . . . . . . 33. Block Diagram of Example Reference Design . . . . . . 44. Example Interface Schematics . . . . . . . . . . . . . . . . . . 65. Document Revision History . . . . . . . . . . . . . . . . . . . 28
An Example MPC8540-BasedCompactPCI Reference Designby NCSD Applications
Freescale Semiconductor, Inc. East Kilbride, Scotland
CompactPCI Reference Design, Rev. 1
2 Freescale Semiconductor
Introduction
The key features of the MPC8540 are described in the MPC8540 User’s Manual and therefore will not be repeated here.
The device consists of the following components in a 783-ball FC-PBGA package• Embedded e500 Book E-compatible core• 256 Kbytes of on-chip memory• DDR memory controller• Local Bus Controller• 2 x Three-speed (10/100/1000) Ethernet controllers (TSEC)• RapidIO interface unit• PCI/PCI-X functional unit• Integrated DMA controller• Programmable Interrupt Controller (PIC)• DUART• I2C Controller• Boot sequencer• Address translation and mapping unit (ATMU)• System performance monitor• System access port• Power management• IEEE 1149.1-compliant, JTAG boundary scan
A block diagram of the main functional units within the MPC8540 is shown in Figure 1.
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Example Reference CompactPCI Design
Figure 1. MPC8540 Functional Block Diagram
2 Example Reference CompactPCI DesignThis example reference design utilises the on chip PCI Controller in the MPC8540 to interface to the CompactPCI bus. It contains a block of DDR SDRAM memory which is controlled directly by the device and a small amount of Flash memory used to hold power on reset boot code.
One of the TSEC ethernet interfaces is brought out to a standard RJ-45 socket via a Gb Ethernet PHY device and associated interface logic. Separate debug interface ports are provided via the on-chip DUART interface.
The RapidIO Trade Association have defined a standard interface connector for a parallel RapidIO interface. This forms part of the specification for a Hardware Implementation Platform (HIP) which allows standard PCI to RapidIO inter operability. This HIP platform is not defined for CompactPCI systems. For reference purposes the schematics for this example design show this standard RapidIO connector as an optional extra connector.
Full details are available at www.rapidio.org.
CompactPCI Reference Design, Rev. 1
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Block Diagram of Example Reference Design
3 Block Diagram of Example Reference DesignA block diagram of the example system is shown in Figure 2.
Figure 2. Block Diagram of Reference Design
3.1 MPC8540The MPC8540 is the processing element of this design. It contains a 32-bit embedded PowerPC processor core and interfaces to each of the other blocks of this example reference design.
3.2 DDR SDRAMThe main memory array is built from 5 x MT46V16M16 DDR SDRAM devices. These are configured to provide 128MBytes of 64-bit wide memory along with one parity bit for each memory byte. The control of the DDR memory system is handled by the DDR memory controller implemented within the MPC8540 device.
3.3 Boot FlashThe boot Flash is implemented by a single 8MByte AMD29L_V641D device configured to be 16-bits wide. Since the local bus of the MPC8540 is a multiplexed address and data bus, an external latch using 74LVT16373 devices is implemented and controlled by the Local Address Latch Enable (LALE) signal from the MPC8540.
DDR SDRAM128MBytes
Boot FLASH8MBytes
CompactPCIConnector
GbEthernetPHY etc
DUARTRS232 Interface
Optional RapidIOConnector
Clocking,Configurationand Reset Logic
Power Supply
MPC8540
DDR SDRAM128MBytes
Boot FLASH8MBytes
CompactPCIConnector
GbEthernetPHY etc
DUARTRS232 Interface
Optional RapidIOConnector
Clocking,Configurationand Reset Logic
Power Supply
MPC8540
CompactPCI Reference Design, Rev. 1
Freescale Semiconductor 5
Block Diagram of Example Reference Design
3.4 Compact PCI ConnectorsThe MPC8540 device contains an on-chip PCI/PCI-X interface which handles all the defined protocol for these buses. The PCI bus is brought out to two separate edge connectors on the board which conform to the Compact PCI interface specification. These are the connectors defined as J1 and J2 in the CompactPCI specification. Note the MPC8540 only supports 3.3V I/O. If a 5V interface is to be supported then level shifting logic will be required between the MPC8540 and the connectors.
3.5 Gb Ethernet PHYThe MPC8540 contains a two separate triple speed ethernet controllers which support speeds of 10Mbps, 100Mbps and 1Gbps. One of these controllers is brought out to an RJ45 edge connector via a Marvell 88E1011Gb Ethernet physical transceiver device
3.6 DUARTThe MPC8540 also contains a dual UART interface that supports simple serial interfaces. These channels are brought out to 9-way D type RS232 connectors. These ports would be typically be used for debug and maintenance work
3.7 Clocking, Configuration and Reset LogicThe MPC8540 uses the input 66MHz PCI clock as a reference and makes use of on-chip PLLs to multiply this clock frequency to drive the memory interface bus and processor core. A diagram of the clock structure is shown in Figure 3.
Figure 3. Clock sub-system Block Diagram
Many of the features of the MPC8540 are configured by sampling a series of pins during reset. In this reference design the configuration pins are all implemented as a series of small DIP switches that are configured by hand before the device is reset. For a design where the final configuration is known at the design stage then these DIP
CompactPCI Reference Design, Rev. 1
6 Freescale Semiconductor
Example Interface Schematics
switches can be omitted and replaced by pull-up or pull-down resistors to achieve the desired value on the configuration pins.
3.8 Power SupplyAssuming this board will be supplied with +5V and +3.3V from the CompactPCI backplane then all the other voltages required on the board are generated by the various power convertor circuits on the card. This includes 2.5V for the DDR memory and Ethernet PHY. The 1.2V cpu core voltage and the 1.5V for the Ethernet PHY. The 1.25V reference voltage for the DDR memory is produced by the LP2995 DDR voltage regulator device.
4 Example Interface SchematicsA full set of interface schematics are shown below. These were created using OrCad version 9.2 available from Cadence Design Systems™. The schematics are laid out in a hierarchical sequence of sheets.
The following pages give a full set of example schematics for an MPC8540 Compact PCI Reference design. They also include an optional RapidIO connector.
The schematics are laid out in a hierarchical fashion as follows:
Table 1. Top Level System Interconnection
Figure 4 Top Level System Interconnection
Figure 5 Top Level view of MPC8540 and memory systems
Figure 6 DDR SDRAM Memory Array
Figure 7 MPC8540 Top Level
Figure 8 Boot FLASH Memory
Figure 9 MPC8540 CPU and Local Bus Interface
Figure 10 MPC8540 DDR SDRAM Interface
Figure 11 DDR SDRAM Termination
Figure 12 MPC8540 Gb Ethernet Interface
Figure 13 MPC8540 RapidIO Interface
Figure 14 MPC8540 Power on Configuration Logic
Figure 15 MPC8540 PCI/PCI-X Interface
Figure 16 MPC8540 Parallel I/O and DUART Interface
Figure 17 MPC8540 Power Connections
Figure 18 Compact PCI J1 and J2 Connectors
Figure 19 Clock and Reset Logic
Figure 20 Local Power Supply Logic
Figure 21 Gb Ethernet Transceiver
Figure 22 RS232 Interface Logic
Figure 23 Optional RapidIO Connector
Figure 24 MPC8540 COP Debug Connector
CompactPCI Reference Design, Rev. 1
Freescale Semiconductor 7
Example Interface Schematics
Figure 4. Top Level System Interconnection
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CompactPCI Reference Design, Rev. 1
8 Freescale Semiconductor
Example Interface Schematics
Figure 5. Top Level view of MPC8540 and memory systems
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CompactPCI Reference Design, Rev. 1
Freescale Semiconductor 9
Example Interface Schematics
Figure 6. DDR SDRAM Memory Array
DDR Memory Termination Regulator
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M
WE
CA
SR
AS
CS
A1
A2
A3
A4
A5
A6
A7
A8
A9
DQ
13D
Q14
DQ
15
VS
SV
SS
UD
QS
LDQ
S
VS
SQ
VS
SQ
NC
NC
DN
U
NC
DN
U
NC
NC
VR
EF
CLK
VS
SQ
VS
SQ
VS
SQ
VS
S
VD
DV
DD
VD
DV
DD
QV
DD
QV
DD
QV
DD
QV
DD
Q
C12
0.1u
F
MD
Q[0
:63]
MD
M[0
:8]
MD
QS
[0:8
]
RA
S*
CA
S*
MW
E*
MB
A[0
:1]
MC
KE
MC
K
MC
K*
MA
[0:1
2]
ME
CC
[0:7
]M
CS
0*
CompactPCI Reference Design, Rev. 1
10 Freescale Semiconductor
Example Interface Schematics
Figure 7. MPC8540 Top Level
MP
C85
60_C
PM
_Int
erfa
ce
P13
_MP
C85
40_C
PM
_Int
erfa
ce
SIN
0
SIN
1
SO
UT
0
SO
UT
1
MP
C85
40_C
ON
FIG
P11
_MP
C85
40_C
onfig
urat
ion_
logi
c
CF
G[1
:32]
HR
ES
ET
MP
C85
40 _
Mem
ory
Inte
rfac
e
P07
/08_
MP
C85
40_D
DR
_Mem
_I/F
ME
CC
[0:7
]
CA
S*
RA
S*
MW
E*
MD
Q[0
:63]
MD
QS
[0:8
]
MD
M[0
:8]
MA
[0:1
2]
MB
A[0
:1]
MC
S0*
MC
K
MC
K*
MC
KE
MP
C85
40_P
CI/P
CIX
_Int
erfa
ce
P12
_MP
C85
40_P
CI_
Inte
rfac
e
PC
I[0:8
6]
SY
SC
LK
CF
G[1
:32]
MP
C85
40_C
PU
P06
_MP
C85
40_C
PU
SY
SC
LK
HR
ES
ET
*
SR
ES
ET
*LA
D[0
:31]
LCS
0*
LALE
LWR
*
LBO
E*
SD
A
SC
L
MD
IO
MD
C
TC
KT
DI
TM
ST
RS
T
TD
O
CF
G[1
:32]
CK
ST
P_I
N*
CK
ST
P_O
UT
*
MP
C85
40_R
apid
IO_I
nter
face
P10
_ M
PC
8540
_Rap
idIO
_Int
erfa
ce
RIO
[0:3
9]
MP
C85
40_P
ower
P14
_MP
C85
40_P
ower
MP
C85
40_C
omm
s_In
terf
ace
P09
_MP
C85
40_C
omm
s_In
terf
ace
ET
HE
RA
[0:2
4]
GT
X_C
LK12
5
CF
G[1
:32]
CF
G[1
:32]
TR
ST
LALE
RA
S*
MC
K
MB
A[0
:1]
PC
I[0:8
6]H
RE
SE
T*
TD
O
LWR
*
MW
E*
MD
Q[0
:63]
LBO
E*
ET
HE
RA
[0:2
4]
MC
S0*
TC
K
MC
K*
SD
A
LCS
0*
MC
KE
MD
M[0
:8]
GT
X_C
LK12
5
SC
L
TD
I
RIO
[0:3
9]
MD
QS
[0:8
]
SY
SC
LK
LAD
[0:3
1]
MD
C
SR
ES
ET
*
ME
CC
[0:7
]
TM
S
MA
[0:1
2]
CA
S*
MD
IO
SIN
0
SIN
1
SO
UT
0
SO
UT
1
CK
ST
P_I
N*
CK
ST
P_O
UT
*
CompactPCI Reference Design, Rev. 1
Freescale Semiconductor 11
Example Interface Schematics
Figure 8. Boot FLASH Memory
LA22
LA18
LA9
LA24
LA15
LA18
LA27
LA12
LA28
LA21
LA11
LA10
LA23
LA28
LA17
LA14
LA27
LA29
LA29
LA11
LA19
LA24
LA30
LA13
LA23
LA15
LA12
LA9
LA20
LA19
LA25
LA14
LA13
LA26
LA16
LA25
LA21
LA30
LA20
LA[9
:30]
LA16
LA22
LA17
LA26
LA10
LAD
3
LAD
15
LAD
12
LAD
30
LAD
7
LAD
11
LAD
19
LAD
1
LAD
27
LAD
31
LAD
21
LAD
13
LAD
9
LAD
4
LAD
15
LAD
28
LAD
14
LAD
20
LAD
5
LAD
10
LAD
24
LAD
17
LAD
29
LAD
4
LAD
0
LAD
2
LAD
2
LAD
6
LAD
23
LAD
1
LAD
3
LAD
0
LAD
13
LAD
8LA
D9
LAD
12
LAD
14
LAD
7LA
D6
LAD
18
LAD
22
LAD
26
LAD
10
LAD
16
LAD
25
LAD
5
LAD
11
LAD
8
+3.
3V
+3.
3V
+3.
3V +3.
3V
+3.
3V
+3.
3V
+3.
3V
R4
4K7
R1
10K
R5
4K7
U10
74LV
T16
373/
SO
2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23
47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 2548 241
4 10 15 21 28 34 39 45
7 18 31 42
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2LE
1LE
2OE
1OE
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
VC
CV
CC
VC
CV
CC
C19
0.1u
F
R3
4K7
U8
74LV
T16
373/
SO
2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23
47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 2548 241
4 10 15 21 28 34 39 45
7 18 31 42
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2LE
1LE
2OE
1OE
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
VC
CV
CC
VC
CV
CC
4M x 16 FLASH
U9
AM
29LV
641D
25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 1626 11
15
29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45
47
28 12910
13 14
27 4637
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
CE
WE
A19
DQ
0D
Q1
DQ
2D
Q3
DQ
4D
Q5
DQ
6D
Q7
DQ
8D
Q9
DQ
10D
Q11
DQ
12D
Q13
DQ
14D
Q15
VIO
OE
RE
SE
TA
21A
20
AC
CW
P
VS
SV
SS
VC
C
U7
EE
PR
OM
48
12375 6
GN
D
VC
C
A0
A1
A2
WP
SD
AS
CL
R7
10K
R6
10K
R2
10K
LAD
[0:3
1]
LCS
0*
LALE
LWR
*
LBO
E*
HR
ES
ET
*
SD
AS
CL
CompactPCI Reference Design, Rev. 1
12 Freescale Semiconductor
Example Interface Schematics
Figure 9. MPC8540 CPU and Local Bus Interface
Sys_PLL Ratio bit 0
Sys_PLL Ratio bit 1
Sys_PLL Ratio bit 2
Sys_PLL Ratio bit 3
Core_PLL Ratio bit 0
Core_PLL Ratio bit 1
Host/Agent Select bit 0
Host/Agent Select bit 1
CPU Boot Configuration
CPU Boot Sequence bit 0
CPU Boot Sequence bit 1
TSEC Width
RIO Tx CLK Source bit 0
RIO Tx CLK Source bit 1
Memory Debug Config
DDR Debug Config
PCI/PCI-X Output Hold bit 0
PCI/PCI-X Output Hold bit 1
Reset Configuration
LAD
27
LAD
5
LAD
3LA
D2
LAD
21
LAD
26
LAD
7
LAD
13
LAD
10LA
D9
LAD
14
LAD
23
LAD
28
LAD
22
LAD
0LA
D1
LAD
4
LAD
6
LAD
8
LAD
11LA
D12
LAD
15LA
D16
LAD
17LA
D18
LAD
19LA
D20
LAD
24LA
D25
LAD
29LA
D30
LAD
31
CF
G1
CF
G2
CF
G4
CF
G6
CF
G7
CF
G8
CF
G3
CF
G5
CF
G12
CF
G1
CF
G2
CF
G3
CF
G4
CF
G12
CF
G13
CF
G14
CF
G15
CF
G18
CF
G19
CF
G27
CF
G28
CF
G29
CF
G30
CF
G5
CF
G6
CF
G7
CF
G8
CF
G13
CF
G14
CF
G15
CF
G18
CF
G19
CF
G27
CF
G28
CF
G29
CF
G30
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V
+3.
3V+
3.3V
R29 10
K
R8
10K
R33
160R
R10
10K
R25
10K
R21
10K
R17
10K
R28
10K
R36
160R
R13
10K
R37
10K
R24
10K
R34
10K
R30
10K
R20
10K
R16
10K
LO
CA
L B
US
U11
F
MP
C85
40
AD
26A
D27
AD
28A
C26
AC
27A
C28
AA
22A
A23
AA
26Y
21Y
22Y
26W
20W
22W
26V
19T
22R
24R
23R
22R
21R
18P
26P
25P
20P
19P
18N
22N
23N
24N
25N
26
AA
27A
A28
T26
P21
V21
V20
U19
U22
V28
V27
V23
V22
AB
28A
B27
T23
P24
U18
T18
T19
T20
T21
Y27
Y28
W27
W28
R27
R28
P27
P28
U27
U28
V18
U23
T27
T28
LAD
0LA
D1
LAD
2LA
D3
LAD
4LA
D5
LAD
6LA
D7
LAD
8LA
D9
LAD
10LA
D11
LAD
12LA
D13
LAD
14LA
D15
LAD
16LA
D17
LAD
18LA
D19
LAD
20LA
D21
LAD
22LA
D23
LAD
24LA
D25
LAD
26LA
D27
LAD
28LA
D29
LAD
30LA
D31
LDP
0LD
P1
LDP
2LD
P3
LALE
LBC
TL
LGP
L0/L
SD
A10
LGP
L1/L
SD
WE
LGP
L2/L
OE
/LS
DR
AS
LGP
L3/L
SD
CA
SLG
PL4
/LG
TA
/LU
PW
AIT
/LP
BS
ELG
PL5
LWE
0/LB
S0
LWE
1/LB
S1
LWE
2/LB
S2
LWE
3/LB
S3
LA27
LA28
LA29
LA30
LA31
LCS
0LC
S1
LCS
2LC
S3
LCS
4LC
S5/
DM
A_D
RE
Q2
LCS
6/D
MA
_DA
CK
2LC
S7/
DM
A_D
DO
NE
2
LCLK
0LC
LK1
LCLK
2
LCK
E
LSY
NC
_IN
LSY
NC
_OU
T
R12
10K
R27
10K
D2 RE
D
R32
10K
R23
10K
R19
10K
R15
10K
R35
10K
R26
10K
R11
10K
R9
10K
D1 RE
D
R22
10K
AU
XIL
IAR
Y F
UN
CT
ION
PIC
DMA
Eth.MI
AN
AL
OG
JTA
G
DEBUG
SPA
RE
S
CL
OC
KIN
G
DF
T
I2C
SY
S. C
NT
RL
PW
R M
ng.
U11
D
MP
C85
40
AG
17A
G16
AA
18Y
18A
B18
AG
24A
A21
Y19
AA
19A
G25
AB
20Y
20A
F26
AH
24A
B21
H5
G4
H6
G5
H7
G6
F1
E1
AB
22
AF
22
AG
2A
H3
AG
22
AF
19
AF
23A
G21
AF
21
AG
23
N12 G2 J9 G3
F3
F5
F2
F4
T11
U11
AF
1C
1
AB
23A
H21
AG
19A
H20
AG
18
AH
23A
H22
M11 G1
AF
20A
G20
AH
16
AH
1A
G1
AH
2B
1B
2A
2A
3A
H25
AH
26A
H27
AH
28A
G28
AF
28A
E28
MC
PU
DE
IRQ
0IR
Q1
IRQ
2IR
Q3
IRQ
4IR
Q5
IRQ
6IR
Q7
IRQ
8IR
Q9/
DM
A_D
RE
Q3
IRQ
10/D
MA
_DA
CK
3IR
Q11
/DM
A_D
DO
NE
3IR
Q_O
UT
DM
A_D
RE
Q0
DM
A_D
RE
Q1
DM
A_D
AC
K0
DM
A_D
AC
K1
DM
A_D
DO
NE
0D
MA
_DD
ON
E1
EC
_MD
CE
C_M
DIO
L1_T
ST
CLK
CLK
_OU
TC
LKO
UT
_DIF
FC
LKO
UT
_DIF
FT
HE
RM
0T
HE
RM
1
L2_T
ST
CLK
TD
O
TM
ST
DI
TC
K
TR
ST
TR
IG_I
NT
RIG
_OU
T/R
EA
DY
/QU
IES
CE
MS
RC
ID0
MS
RC
ID1
MS
RC
ID2
MS
RC
ID3
MS
RC
ID4
MD
VA
L
SP
AR
E1
SP
AR
E2
SP
AR
E3
SP
AR
E4
RT
CS
YS
CLK
LSS
D_M
OD
ET
ES
T_S
EL(
Dra
co/D
raco
m)
AS
LEE
P
IIC_S
CL
IIC_S
DA
CK
ST
P_I
NC
KS
TP
_OU
TS
RE
SE
TH
RE
SE
T_R
EQ
HR
ES
ET
NC
1N
C2
NC
3N
C4
NC
5N
C6
NC
7N
C8
NC
9N
C10
NC
11N
C12
NC
13N
C14
NC
15
R18
10K
R31
10K
R14
10K
LWR
*
SR
ES
ET
*
LCS
0*
LAD
[0:3
1]
LBO
E*
LALE
SY
SC
LK
HR
ES
ET
*
MD
IOM
DC
SD
AS
CL
TD
I
TR
ST
TD
O
TC
K
TM
S
CF
G[1
:32]
CK
ST
P_I
N*
CK
ST
P_O
UT
*
CompactPCI Reference Design, Rev. 1
Freescale Semiconductor 13
Example Interface Schematics
Figure 10. MPC8540 DDR SDRAM Interface
PM
A1
RA
S*
PM
BA
1
MC
KE
MC
K
CA
S*
PM
A12
PM
A5
PM
A10
PM
A3
MC
K*
PM
A9
PM
A4
MC
S0*
PM
A2
PM
A8
MW
E*
PM
DQ
54
PM
DQ
34
PM
DQ
60
PM
DQ
48
PM
DQ
45
PM
DQ
63
PM
DQ
49
PM
DQ
59P
MD
Q58
PM
DQ
52P
MD
Q51
PM
DQ
33
PM
DQ
43
PM
DQ
46
PM
DQ
56
PM
DQ
41
PM
DQ
37
PM
DQ
47
PM
DQ
35
PM
DQ
0P
MD
Q1
PM
DQ
2P
MD
Q3
PM
DQ
4P
MD
Q5
PM
DQ
6P
MD
Q7
PM
DQ
8P
MD
Q9
PM
DQ
10P
MD
Q11
PM
DQ
12P
MD
Q13
PM
DQ
14P
MD
Q15
PM
DQ
16P
MD
Q17
PM
DQ
18P
MD
Q19
PM
DQ
20P
MD
Q21
PM
DQ
22P
MD
Q23
PM
DQ
24P
MD
Q25
PM
DQ
26P
MD
Q27
PM
DQ
28P
MD
Q29
PM
DQ
30P
MD
Q31
PM
DQ
32
PM
DQ
36
PM
DQ
38P
MD
Q39
PM
DQ
40
PM
DQ
42
PM
DQ
44
PM
DQ
50
PM
DQ
53
PM
DQ
55
PM
DQ
57
PM
DQ
61P
MD
Q62
PM
EC
C0
PM
EC
C1
PM
EC
C2
PM
EC
C3
PM
EC
C4
PM
EC
C5
PM
EC
C6
PM
EC
C7
PM
DM
0P
MD
M1
PM
DM
2P
MD
M3
PM
DM
4P
MD
M5
PM
DM
6P
MD
M7
PM
DM
8P
MD
QS
0P
MD
QS
1P
MD
QS
2P
MD
QS
3P
MD
QS
4P
MD
QS
5P
MD
QS
6P
MD
QS
7P
MD
QS
8P
MA
0
PM
A6
PM
A7
PM
A11
PM
BA
0
PC
AS
*
PM
BA
[0:1
]
PM
DQ
[0:6
3]
PM
WE
*
PM
DQ
S[0
:8]
PR
AS
*
PM
A[0
:12]
PM
EC
C[0
:7]
PM
DM
[0:8
]
+2.
5V
VR
EF
_+1.
25V
+2.
5V
R40
10K
C22
0.1u
F
C31
10uF
C25
0.1u
F
R39
10K
C20
0.1u
FC
240.
1uF
C32
10uF
C29
0.1u
FC
260.
1uF
DD
R S
DR
AM
U11
B
MP
C85
40
N20
M20 L19
E19
C21
A21
G19
A19 L24
H28
F24 L21
E18
E16
G14
B13
M19 L26
J25
D25
A22
H18
F16
F14
C13
C20
N19
B21
F21
K21
M21
C23
A23
B24
H23
G24
K19
B25
D27 J14
J13
M26
L27
L22
K24
M24
M23
K27
K26
K22
J28
F26
E27
J26
J23
H26
G26
C26
E25
C24
E23
D26
C25
A24
D23
B23
F22
J21
G21
G22
D22
H21
E21
N18
J18
D18
L17
M18
L18
C18
A18
K17
K16
C16
B16
G17
L16
A16
L15
G15
E15
C14
K13
C15
D15
E14
D14
D13
E13
D12
A11
F13
H13
A13
B12
B18
B19
D17
F17 J16
H16
G16 J15
H15
E26
E28 J20
F20
H25
A15
D20
F28
K14
G27
B15
E20
F27 L14
N28
M28
J12
F12
C12
L13
G13
A14
K15
F15
D16
J17
E17
B17
G18
H19
F19
D19
K20
G20
A20
N21
D21
J22
E22
B22
L23
G23
H24
D24
M25
K25
F25
A25
A26
J27
A27
L28
G28
D28
C28
B28
A28
N27
ME
CC
0M
EC
C1
ME
CC
2M
EC
C3
ME
CC
4M
EC
C5
ME
CC
6M
EC
C7
MD
M0
MD
M1
MD
M2
MD
M3
MD
M4
MD
M5
MD
M6
MD
M7
MD
M8
MD
QS
0M
DQ
S1
MD
QS
2M
DQ
S3
MD
QS
4M
DQ
S5
MD
QS
6M
DQ
S7
MD
QS
8M
A0
MA
1M
A2
MA
3M
A4
MA
5M
A6
MA
7M
A8
MA
9M
A10
MA
11M
A12
MA
13M
A14
MD
Q0
MD
Q1
MD
Q2
MD
Q3
MD
Q4
MD
Q5
MD
Q6
MD
Q7
MD
Q8
MD
Q9
MD
Q10
MD
Q11
MD
Q12
MD
Q13
MD
Q14
MD
Q15
MD
Q16
MD
Q17
MD
Q18
MD
Q19
MD
Q20
MD
Q21
MD
Q22
MD
Q23
MD
Q24
MD
Q25
MD
Q26
MD
Q27
MD
Q28
MD
Q29
MD
Q30
MD
Q31
MD
Q32
MD
Q33
MD
Q34
MD
Q35
MD
Q36
MD
Q37
MD
Q38
MD
Q39
MD
Q40
MD
Q41
MD
Q42
MD
Q43
MD
Q44
MD
Q45
MD
Q46
MD
Q47
MD
Q48
MD
Q49
MD
Q50
MD
Q51
MD
Q52
MD
Q53
MD
Q54
MD
Q55
MD
Q56
MD
Q57
MD
Q58
MD
Q59
MD
Q60
MD
Q61
MD
Q62
MD
Q63
MB
A0
MB
A1
MW
E-
MR
AS
-M
CA
S-
MC
S0-
MC
S1-
MC
S2-
MC
S3-
MC
KE
0M
CK
E1
MC
K0
MC
K0-
MC
K1
MC
K2
MC
K3
MC
K4
MC
K5
MC
K1-
MC
K2-
MC
K3-
MC
K4-
MC
K5-
MS
YN
C_O
UT
MS
YN
C_I
NG
Vdd
1G
Vdd
2G
Vdd
3G
Vdd
4G
Vdd
5G
Vdd
6G
Vdd
7G
Vdd
8G
Vdd
9G
Vdd
10G
Vdd
11G
Vdd
12G
Vdd
13G
Vdd
14G
Vdd
15G
Vdd
16G
Vdd
17G
Vdd
18G
Vdd
19G
Vdd
20G
Vdd
21G
Vdd
22G
Vdd
23G
Vdd
24G
Vdd
25G
Vdd
26G
Vdd
27G
Vdd
28G
Vdd
29G
Vdd
30G
Vdd
31G
Vdd
32G
Vdd
33G
Vdd
34G
Vdd
35G
Vdd
36G
Vdd
37G
Vdd
38G
Vdd
39G
Vdd
40G
Vdd
41
MV
RE
F(G
Vdd
/2)
C27
0.1u
F
R38
10K
C21
0.1u
FC
230.
1uF
C30
10uF
C28
0.1u
F
MC
KE
MC
K*
MC
K
MC
S0*
CompactPCI Reference Design, Rev. 1
14 Freescale Semiconductor
Example Interface Schematics
Figure 11. DDR SDRAM Termination
MD
Q53
PM
DQ
26
MD
Q20
MD
Q31
MD
Q38
ME
CC
0
MD
Q30
MD
Q40
PM
DQ
27
MD
Q15
PM
DQ
S5
MD
Q3
PM
EC
C7
MD
Q26
MD
QS
0
MD
Q12
MA
1
MD
Q21
MD
M2
MD
Q45
PM
DQ
23
MD
QS
7
MD
Q9
PM
DQ
62
MA
4
MD
Q38
MD
Q51
MD
M3
PM
A2
PM
DQ
12
PM
DQ
21M
EC
C7
MD
Q25
PM
DQ
49
MD
M2
MD
M8
MD
Q61
PM
DQ
11
MD
Q2
PM
DM
5
MD
Q29
MD
M6
PM
DQ
51
PM
DQ
22
MD
Q8
MD
Q52
MD
Q19
PM
DQ
25
MD
Q1
MD
Q55
MD
Q53
MD
Q11
MD
Q27
MD
Q6
PM
A12
MD
Q17
MD
Q4
MD
Q7
MD
Q44
MD
Q13
PM
A9
MD
Q7
MD
Q9
MD
Q58
PM
DQ
54
PM
DQ
52
MD
Q48
PM
DQ
S8
MD
Q63
PM
DQ
56
MD
Q11
PM
DQ
35
MD
QS
8
MD
Q52
MB
A0
MA
2P
MD
Q61
MD
Q33
PM
DM
7
MD
QS
1
PM
A10
PM
A11
MA
3P
MD
Q60
ME
CC
6
MD
QS
7
MD
Q50
MD
M4
MD
Q36
MA
3
PM
DQ
46
PM
DQ
42
PM
DQ
38
ME
CC
0
PM
DQ
S6
MD
Q14
MA
5
MA
7
MA
5
MD
Q43
PM
DQ
S1
PM
DQ
41
ME
CC
6P
MD
Q19
PM
DQ
32
MD
M1
PM
DQ
37
MD
Q44
MB
A1
PM
DQ
48
PM
DQ
29
PM
A3
MD
Q16
MA
12
ME
CC
2
PM
DQ
14
MD
Q39
MD
Q42
MD
M6
MD
Q30
MD
Q31
MD
Q41
MA
8
PM
DQ
3
MD
Q45
MD
M5
PM
DQ
7
MD
QS
6
MD
Q6
MD
Q24
ME
CC
1
MD
Q39
MD
Q18
PM
DQ
8
PM
DQ
13
MA
9
MD
QS
5
ME
CC
1
PM
EC
C3
MD
Q3
PM
DM
1
PM
EC
C6
MD
QS
1
MA
11
MD
Q0
MD
Q51
PM
DQ
S0
PM
DQ
S4
MD
Q10
MD
QS
4
MD
Q0
MA
2
MA
0
PM
DQ
59
MD
Q60
PM
DQ
15
MA
10
MD
Q22
MD
M0
PM
DQ
17
PM
DQ
53
MD
M7
MD
Q55
MD
Q15
MD
Q46
PM
DQ
57
PM
DQ
S7
MD
Q18
MD
Q1
MA
1
MA
9
MD
Q8
MD
QS
8
MD
Q54
MD
Q25
ME
CC
2
MB
A0
PM
A4
PM
DM
0
MD
Q20
MD
Q12
MD
Q17
MD
Q22
MD
Q34
PM
DQ
18
ME
CC
3
MD
Q26
MD
Q14
PM
DQ
40
PM
EC
C1
PM
DQ
34
MD
Q58
MD
QS
5
PM
BA
0
MD
QS
6
MD
M3
MD
Q40
MD
Q24
MD
Q47
PM
DQ
39
MD
Q59
PM
DQ
43
ME
CC
4
PM
DQ
47
MD
Q5
MA
6
PM
DQ
1
PM
A7
PM
DM
3
PM
DQ
28
PM
DQ
24
MA
6M
DQ
57
MD
Q2
PM
A8
PM
EC
C0
PM
EC
C2
PM
DM
4
ME
CC
5
MD
Q47
MA
12
MD
M4
MD
M1
PM
A6
PM
DQ
S3
MD
Q60
PM
BA
1
MD
Q23
PM
DQ
9
ME
CC
4
MD
Q63
MD
Q4
MD
QS
3
MD
QS
2
MD
Q48
MD
Q19
MD
Q49
MD
Q61
PM
EC
C5
ME
CC
3
MA
7M
DM
7
PM
DQ
4
MD
Q23
MD
Q36
PM
DQ
5
MA
11
MD
QS
0
PM
DQ
50
MD
Q49
MD
Q54
PM
DM
6
PM
DQ
63
PM
DQ
20
MD
Q5
MD
Q28
MD
M8
PM
DQ
44
MD
M5
MA
8
MD
Q28
PM
DQ
10
MD
Q57
MD
M0
MD
Q27
PM
DQ
0
ME
CC
7
PM
DQ
30
PM
DQ
36
MD
Q34
MD
Q35
PM
DQ
2
PM
A0
ME
CC
5
PM
DQ
16
MD
Q41
MD
Q29
MD
Q35
PM
DM
8
MA
0
PM
DQ
S2
PM
A5
PM
DQ
6
MD
Q46
MD
Q62
MD
Q21
MD
Q13
MD
Q56
MD
Q32
PM
A1
MD
Q62
MD
Q37
PM
DQ
58
PM
DQ
33M
DQ
33
MA
10
MD
Q56
MD
Q42
MD
Q10
PM
DM
2
MD
Q16
MD
QS
2
MD
Q43
PM
EC
C4
MD
Q59
MD
Q32
MB
A1
PM
DQ
45
MA
4
MD
Q50
MD
QS
3M
DQ
37
PM
DQ
31
PM
DQ
55
MD
QS
4
PM
DQ
[0:6
3]P
MA
[0:1
2]
PM
EC
C[0
:7]
PC
AS
*
PM
BA
[0:1
]
PM
DM
[0:8
]
PR
AS
*
PM
DQ
S[0
:8]
PM
WE
*
VT
T_+
1.25
V
VT
T_+
1.25
V
VT
T_+
1.25
V
VT
T_+
1.25
V
VT
T_+
1.25
V
VT
T_+
1.25
V
VT
T_+
1.25
V
VT
T_+
1.25
V
VT
T_+
1.25
VV
TT
_+1.
25V
R24
522
R
R21
922
R
R11
522
R
R16
122
R
R17
625
RR
180
25R
R41
22R
R86
25R
R70
25R
R52
25R
R18
425
R
R18
122
R
R23
322
R
R21
722
R
R24
322
R
R62
25R
R46
25R
R16
522
R
R79
22R
R23
922
R
R10
122
R
R68
25R
R87
22R
R84
25R
R14
425
R
R73
22R
R10
522
R
R19
625
R
R44
25R
R60
25R
R20
825
R
R16
322
R
R21
025
R
R25
322
R
R99
22R
R13
225
R
R22
722
R
R69
22R
R13
722
R
R15
722
R
R94
25R
R19
425
R
R74
25R
R20
625
R
R18
322
R
R67
22R
R14
825
R
R23
825
R
R15
625
R
R92
25R
R50
25R
R12
322
R
R23
122
R
R42
25R
R17
722
R
R15
322
R
R14
225
R
R23
625
RR
242
25R
R17
522
R
R18
625
R
R22
025
R
R20
322
R
R12
122
R
R22
922
R
R21
425
R
R45
22R
R13
522
R
R15
825
R
R12
425
R
R11
425
R
R81
22R
R13
122
R
R21
825
R
R16
825
R
R43
22R
R95
22R
R78
25R
R21
225
R
R13
322
R
R17
025
R
R12
225
R
R49
22R
R15
025
R
R11
025
R
R24
025
R
R19
722
R
R19
122
R
R15
225
R
R11
322
R
R17
425
R
R14
122
R
R11
825
R
R20
425
R
R25
625
R
R76
25R
R82
25R
R14
522
R
R20
922
R
R10
825
R
R12
922
R
R11
122
R
R77
22R
R17
225
R
R20
122
R
R22
225
R
R19
522
R
R11
625
R
R58
25R
R10
425
R
R20
722
R
R85
22R
R18
722
R
R17
922
R
R16
922
R
R63
22R
R12
722
R
R19
825
R
R75
22R
R19
922
R
R21
522
R
R83
22R
R20
522
R
R55
22R
R12
025
R
R22
625
R
R89
22R
R18
225
R
R14
322
R
R56
25R
R13
025
R
R25
225
R
R57
22R
R10
625
R
R22
425
RR
221
22R
R12
522
R
R88
25R
R72
25R
R14
625
R
R12
825
R
R21
625
R
R25
122
R
R90
25R
R25
025
R
R17
322
R
R25
425
R
R19
322
R
R48
25R
R64
25R
R19
225
R
R16
722
R
R10
322
R
R19
025
R
R15
122
R
R66
25R
R15
922
R
R14
025
R
R24
722
RR
249
22R
R17
122
R
R23
722
R
R16
625
R
R22
825
R
R93
22R
R23
225
R
R13
625
R
R20
225
R
R25
522
R
R71
22R
R18
922
R
R96
25R
R23
522
R
R16
425
R
R17
825
R
R97
22R
R91
22R
R23
025
R
R14
922
R
R20
025
R
R13
425
R
R10
922
R
R18
825
R
R24
625
R
R13
825
R
R65
22R
R10
225
R
R13
922
R
R61
22R
R16
025
R
R21
322
R
R11
922
R
R10
722
R
R16
225
R
R24
425
R
R12
625
R
R24
122
R
R22
522
R
R10
025
R
R47
22R
R18
522
R
R59
22R
R21
122
R
R53
22R
R24
825
R
R11
722
R
R15
425
R
R98
25R
R15
522
R
R22
322
R
R14
722
R
R54
25R
R80
25R
R51
22R
R11
225
R
R23
425
R
MW
E*
MD
M[0
:8]
MD
Q[0
:63]
ME
CC
[0:7
]
RA
S*
MA
[0:1
2]
MD
QS
[0:8
]
MB
A[0
:1]
CA
S*
CompactPCI Reference Design, Rev. 1
Freescale Semiconductor 15
Example Interface Schematics
Figure 12. MPC8540 Gb Ethernet Interface
Boot ROM Location bit 0
Boot ROM Location bit 1
Boot ROM Location bit 2
TSEC1 Protocol
TSEC2 Protocol
RIO Device ID bit 6
RIO Device ID bit 7
Local Bus Output Hold bit 0
Local Bus Output Hold bit 1
Reset Configuration
RX
_DV
0E
TH
ER
A22
ET
HE
RA
7C
FG
16
RX
D06
ET
HE
RA
20
TX
_EN
0E
TH
ER
A8
CF
G17
TX
D02
ET
HE
RA
2
RX
D04
ET
HE
RA
18
RX
D07
ET
HE
RA
21
ET
HE
RA
11G
TX
_CLK
0
TX
D01
ET
HE
RA
1
ET
HE
RA
6C
FG
9
RX
D03
ET
HE
RA
17
RX
D00
ET
HE
RA
14
CF
G32
TX
D07
ET
HE
RA
7
CF
G22
TX
D05
ET
HE
RA
5
CF
G16
RX
D02
ET
HE
RA
16
RX
_ER
0E
TH
ER
A23
TX
_ER
0E
TH
ER
A9
CR
S0
ET
HE
RA
12
TX
D03
ET
HE
RA
3T
XD
04E
TH
ER
A4
ET
HE
RA
5C
FG
10C
FG
9
RX
D01
ET
HE
RA
15
CF
G11
TX
_CLK
0E
TH
ER
A10
TX
D06
ET
HE
RA
6
RX
_CLK
0E
TH
ER
A24
CF
G21
RX
D05
ET
HE
RA
19
TX
D00
ET
HE
RA
0
CF
G10
CF
G31
CO
L0E
TH
ER
A13
ET
HE
RA
4C
FG
11
TX
D15
CF
G32
TX
D16
CF
G31
TX
D17
CF
G17
TX
D13
CF
G22
TX
D12
CF
G21
+3.
3V
TSE
C1
TSE
C2
Gb
E C
lock
ing
U11
G
MP
C85
40
E8
G8
A7
B7
C7
D7
F7
A6
C8
B8
C6
B6
E6
F6
A5
B5
D5
D3
B4
D4
D2
E5
D6
C3
G7
E11
G11
H11
J11
K11
J10
A10
B10
B11
D11
D10
C10
F10
G10
H9
A9
B9
C9
E9
F9
H8
A8
E10
D9
F8
E2
A4
C5
E7
H10
TS
EC
1_T
XD
0T
SE
C1_
TX
D1
TS
EC
1_T
XD
2T
SE
C1_
TX
D3
TS
EC
1_T
XD
4T
SE
C1_
TX
D5
TS
EC
1_T
XD
6T
SE
C1_
TX
D7
TS
EC
1_T
X_E
NT
SE
C1_
TX
_ER
TS
EC
1_T
X_C
LKT
SE
C1_
GT
X_C
LK
TS
EC
1_R
XD
0T
SE
C1_
RX
D1
TS
EC
1_R
XD
2T
SE
C1_
RX
D3
TS
EC
1_R
XD
4T
SE
C1_
RX
D5
TS
EC
1_R
XD
6T
SE
C1_
RX
D7
TS
EC
1_R
X_D
VT
SE
C1_
RX
_ER
TS
EC
1_R
X_C
LK
TS
EC
1_C
RS
TS
EC
1_C
OL
TS
EC
2_T
XD
0T
SE
C2_
TX
D1
TS
EC
2_T
XD
2T
SE
C2_
TX
D3
TS
EC
2_T
XD
4T
SE
C2_
TX
D5
TS
EC
2_T
XD
6T
SE
C2_
TX
D7
TS
EC
2_T
X_E
NT
SE
C2_
TX
_ER
TS
EC
2_T
X_C
LKT
SE
C2_
GT
X_C
LK
TS
EC
2_R
XD
0T
SE
C2_
RX
D1
TS
EC
2_R
XD
2T
SE
C2_
RX
D3
TS
EC
2_R
XD
4T
SE
C2_
RX
D5
TS
EC
2_R
XD
6T
SE
C2_
RX
D7
TS
EC
2_R
X_D
VT
SE
C2_
RX
_ER
TS
EC
2_R
X_C
LK
TS
EC
2_C
RS
TS
EC
2_C
OL
EC
_GT
X_C
LK12
5
LVdd
1LV
dd2
LVdd
3LV
dd4
ET
HE
RA
[0:2
4]
GT
X_C
LK12
5
CF
G[1
:32]
CompactPCI Reference Design, Rev. 1
16 Freescale Semiconductor
Example Interface Schematics
Figure 13. MPC8540 RapidIO Interface
RIO
0R
IO_T
CLK
RIO
1R
IO_T
CLK
*R
IO2
RIO
_TF
RA
ME
RIO
3R
IO_T
FR
AM
E*
RIO
4R
IO_T
D0
RIO
5R
IO_T
D0*
RIO
6R
IO_T
D1
RIO
7R
IO_T
D1*
RIO
8R
IO_T
D2
RIO
9R
IO_T
D2*
RIO
10R
IO_T
D3
RIO
11R
IO_T
D3*
RIO
12R
IO_T
D4
RIO
13R
IO_T
D4*
RIO
14R
IO_T
D5
RIO
15R
IO_T
D5*
RIO
16R
IO_T
D6
RIO
17R
IO_T
D6*
RIO
18R
IO_T
D7
RIO
19R
IO_T
D7*
RIO
20R
IO_R
CLK
RIO
21R
IO_R
CLK
*
RIO
22R
IO_R
FR
AM
E
RIO
23R
IO_R
FR
AM
E*
RIO
24R
IO_R
D0
RIO
25R
IO_R
D0*
RIO
26R
IO_R
D1
RIO
27R
IO_R
D1*
RIO
28R
IO_R
D2
RIO
29R
IO_R
D2*
RIO
30R
IO_R
D3
RIO
31R
IO_R
D3*
RIO
32R
IO_R
D4
RIO
33R
IO_R
D4*
RIO
34R
IO_R
D5
RIO
35R
IO_R
D5*
RIO
36R
IO_R
D6
RIO
37R
IO_R
D6*
RIO
38R
IO_R
D7
RIO
39R
IO_R
D7*
U11
C
MP
C85
40
AC
20A
E21
AE
25A
E24
AE
18
AC
18
AD
19
AE
20
AD
21
AE
22
AC
22
AD
23
AD
18
AE
19
AC
19
AD
20
AC
21
AD
22
AE
23
AC
23
Y25
Y24
AE
27
AE
26
T25
U25
T24
V25
W25
AA
25
AB
25
AC
25
AD
25
U24
V24
W24
AA
24
AB
24
AC
24
AD
24
AF
24
AF
25
RIO
_TC
LKR
IO_T
CLK
-
RIO
_TF
RA
ME
-R
IO_T
FR
AM
E
RIO
_TD
0
RIO
_TD
1
RIO
_TD
2
RIO
_TD
3
RIO
_TD
4
RIO
_TD
5
RIO
_TD
6
RIO
_TD
7
RIO
_TD
0-
RIO
_TD
1-
RIO
_TD
2-
RIO
_TD
3-
RIO
_TD
4-
RIO
_TD
5-
RIO
_TD
6-
RIO
_TD
7-
RIO
_RC
LK
RIO
_RC
LK-
RIO
_RF
RA
ME
RIO
_RF
RA
ME
-
RIO
_RD
0
RIO
_RD
1
RIO
_RD
0-
RIO
_RD
2
RIO
_RD
3
RIO
_RD
4
RIO
_RD
5
RIO
_RD
6
RIO
_RD
7
RIO
_RD
1-
RIO
_RD
2-
RIO
_RD
3-
RIO
_RD
4-
RIO
_RD
5-
RIO
_RD
6-
RIO
_RD
7-
RIO
_TX
CLK
_IN
RIO
_TX
CLK
_IN
-
RIO
[0:3
9]
CompactPCI Reference Design, Rev. 1
Freescale Semiconductor 17
Example Interface Schematics
Figure 14. MPC8540 Power on Configuration Logic
Sys_PLL Ratio bit 3
Host/Agent Select bit 1
Sys_PLL Ratio bit 1
CPU Boot Sequence bit 0
CPU Boot Sequence bit 1
Boot ROM location bit 0
Core_PLL Ratio bit 0
Boot ROM location bit 2
Host/Agent Select bit 0
Reset Configuration
Boot ROM location bit 1
RIO Tx CLK Source bit 1
TSEC Width
Sys_PLL Ratio bit 2
CPU Boot Configuration
Core_PLL Ratio bit 1
Sys_PLL Ratio bit 0
RIO Tx CLK Source bit 0
TSEC1 Protocol
TSEC2 Protocol
PCI Width (32/64)
Local Bus Output Hold bit 1
Local Bus Output Hold bit 0
PCI/PCI-X Output Hold bit 1
PCI/PCI-X Output Hold bit 0
Memory Debug Config
PCI Mode Config
PCI Debug
PCI Arbiter
PCI I/O Impedance
RIO Device ID bit 7
RIO Device ID bit 6
Reset Configuration
DDR Debug Config
CF
G1
CF
G2
CF
G3
CF
G4
CF
G5
CF
G6
CF
G7
CF
G8
CF
G9
CF
G10
CF
G11
CF
G12
CF
G13
CF
G14
CF
G15
CF
G16
CF
G29
CF
G27
CF
G20
CF
G25
CF
G31
CF
G30
CF
G17
CF
G28
CF
G18
CF
G24
CF
G21
CF
G19
CF
G26
CF
G23
CF
G32
CF
G22
+3.
3V
+3.
3V
+3.
3V+
3.3V
+3.
3V
+3.
3V
+3.
3V
R25
710
K
S4
SW
DIP
-8
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
U12
IDT
54F
CT
1622
44/F
P
2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23
43444647 37384041 32333536 26272930 1 242548
7183142
410152128343945
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4
1A4
1A3
1A2
1A1
2A4
2A3
2A2
2A1
3A4
3A3
3A2
3A1
4A4
4A3
4A2
4A1
1OE
4OE
3OE
2OE
VCCVCCVCCVCC
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
RN
3
10K
,5%
10
12346789
5
RN
4
10K
,5%
10
12346789
5
S2
SW
DIP
-8
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
S3
SW
DIP
-8
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
U13
IDT
54F
CT
1622
44/F
P
2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23
43444647 37384041 32333536 26272930 1 242548
7183142
410152128343945
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4
1A4
1A3
1A2
1A1
2A4
2A3
2A2
2A1
3A4
3A3
3A2
3A1
4A4
4A3
4A2
4A1
1OE
4OE
3OE
2OE
VCCVCCVCCVCC
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
S1
SW
DIP
-8
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
RN
2
10K
,5%
10
12346789
5
RN
1
10K
,5%
10
12346789
5
U14
74LV
175
19
2 7 10 15 3 6 11 14
4 5 12 13
MR
ST
CLK
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
D0
D1
D2
D3
CF
G[1
:32]
HR
ES
ET
SY
SC
LK
CompactPCI Reference Design, Rev. 1
18 Freescale Semiconductor
Example Interface Schematics
Figure 15. MPC8540 PCI/PCI-X Interface
PCI I/O Impedance
PCI Arbiter
PCI Debug
PCI Mode Config
PCI Width (32/64)
Reset Configuration
PC
I14
AD
14
PC
I22
AD
22
PC
I16
AD
16
PC
I82
PE
RR
*
PC
I10
AD
10
PC
I86
PC
ICLK
AD
51P
CI5
1
PC
I12
AD
12
PC
I43
AD
43P
CI4
4A
D44
PC
I8A
D8
PC
I6A
D6
PC
I3A
D3
PC
I42
AD
42
PC
I17
AD
17
PC
I31
AD
31
PC
I24
AD
24
PC
I13
AD
13
PC
I41
AD
41
PC
I5A
D5
AD
57P
CI5
7
AD
55P
CI5
5
PC
I7A
D7
PC
I9A
D9
PC
I20
AD
20
PC
I4A
D4
PC
I40
AD
40
PC
I27
AD
27
PC
I35
AD
35
PC
I25
AD
25
PC
I2A
D2
PC
I26
AD
26
PC
I32
AD
32
PC
I74
FR
AM
E*
PC
I19
AD
19
PC
I34
AD
34
PC
I18
AD
18
PC
I0A
D0
PC
I15
AD
15
PC
I30
AD
30
AD
62P
CI6
2
PC
I33
AD
33
PC
I23
AD
23
AD
60P
CI6
0
PC
I11
AD
11
PC
I29
AD
29
PC
I85
GN
T0
AD
54P
CI5
4
PC
I72
PA
R
PC
I47
AD
47
PC
I76
IRD
Y*
AD
63P
CI6
3
PC
I39
AD
39
PC
I46
AD
46
PC
I37
AD
37P
CI3
6A
D36
PC
I28
AD
28
PC
I38
AD
38
PC
I45
AD
45
PC
I1A
D1
PC
I64
C_B
E0
AD
48P
CI4
8
PC
I21
AD
21
PC
I75
TR
DY
*
AD
56P
CI5
6
AD
59P
CI5
9
AD
53P
CI5
3
AD
50P
CI5
0
AD
52P
CI5
2
AD
49P
CI4
9
AD
61P
CI6
1
AD
58P
CI5
8
PC
I65
C_B
E1
PC
I66
C_B
E2
PC
I67
C_B
E3
PC
I68
C_B
E4
PC
I69
C_B
E5
PC
I70
C_B
E6
PC
I71
C_B
E7
PC
I73
PA
R64
PC
I77
ST
OP
*P
CI7
8D
EV
SE
L*P
CI7
9ID
SE
L*P
CI8
0R
EQ
64*
PC
I81
AC
K64
*
PC
I83
SE
RR
*R
EQ
0P
CI8
4
CF
G23
PC
I_G
NT
1
CF
G24
PC
I_G
NT
2
CF
G25
PC
I_G
NT
3
CF
G26
PC
I_G
NT
4
CF
G20
PC
I_R
EQ
64
PC
I_G
NT
1P
CI_
GN
T2
PC
I_G
NT
3P
CI_
GN
T4
PC
I_R
EQ
64P
CI8
0
PC
IX/P
CI
U11
A
MP
C85
40
AC
12A
D11
AB
10A
H8
W14
V14
AH
13A
G13
AC
13A
B13
Y13
V13
AH
12A
G12
AE
12A
D12
AB
12Y
12W
12V
12A
H11
AG
11A
F11
AE
11A
A10
Y10
W10
AH
9A
G9
AF
9A
E9
AD
9A
G8
AF
8A
C8
AB
8A
H7
AE
7A
D7
AH
6A
F18
AF
17A
E17
AB
17A
A17
Y17
W17
V17
AF
16A
E16
AD
16A
C16
AB
16W
16V
16A
H15
AG
15A
D15
AC
15A
B15
AA
15Y
15W
15V
15A
H14
AG
14A
F14
AE
14A
D14
AC
14A
B14
AA
14
AA
11Y
14A
C10
AG
10A
D10
V11
AH
10A
A9
AE
13A
D13
W11
Y11
AF
5A
F3
AE
4A
G4
AE
5A
E6
AG
5A
H5
AF
6A
G6
PC
I_C
_BE
0P
CI_
C_B
E1
PC
I_C
_BE
2P
CI_
C_B
E3
PC
I_C
_BE
4P
CI_
C_B
E5
PC
I_C
_BE
6P
CI_
C_B
E7
PC
I_A
D0
PC
I_A
D1
PC
I_A
D2
PC
I_A
D3
PC
I_A
D4
PC
I_A
D5
PC
I_A
D6
PC
I_A
D7
PC
I_A
D8
PC
I_A
D9
PC
I_A
D10
PC
I_A
D11
PC
I_A
D12
PC
I_A
D13
PC
I_A
D14
PC
I_A
D15
PC
I_A
D16
PC
I_A
D17
PC
I_A
D18
PC
I_A
D19
PC
I_A
D20
PC
I_A
D21
PC
I_A
D22
PC
I_A
D23
PC
I_A
D24
PC
I_A
D25
PC
I_A
D26
PC
I_A
D27
PC
I_A
D28
PC
I_A
D29
PC
I_A
D30
PC
I_A
D31
PC
I_A
D32
PC
I_A
D33
PC
I_A
D34
PC
I_A
D35
PC
I_A
D36
PC
I_A
D37
PC
I_A
D38
PC
I_A
D39
PC
I_A
D40
PC
I_A
D41
PC
I_A
D42
PC
I_A
D43
PC
I_A
D44
PC
I_A
D45
PC
I_A
D46
PC
I_A
D47
PC
I_A
D48
PC
I_A
D49
PC
I_A
D50
PC
I_A
D51
PC
I_A
D52
PC
I_A
D53
PC
I_A
D54
PC
I_A
D55
PC
I_A
D56
PC
I_A
D57
PC
I_A
D58
PC
I_A
D59
PC
I_A
D60
PC
I_A
D61
PC
I_A
D62
PC
I_A
D63
PC
I_P
AR
PC
I_P
AR
64P
CI_
FR
AM
EP
CI_
TR
DY
PC
I_IR
DY
PC
I_S
TO
PP
CI_
DE
VS
EL
PC
I_ID
SE
LP
CI_
RE
Q64
PC
I_A
CK
64P
CI_
PE
RR
PC
I_S
ER
RP
CI_
RE
Q0
PC
I_R
EQ
1P
CI_
RE
Q2
PC
I_R
EQ
3P
CI_
RE
Q4
PC
I_G
NT
0P
CI_
GN
T1
PC
I_G
NT
2P
CI_
GN
T3
PC
I_G
NT
4
PC
I[0:8
6]S
YS
CLK
CF
G[1
:32]
CompactPCI Reference Design, Rev. 1
Freescale Semiconductor 19
Example Interface Schematics
Figure 16. MPC8540 Parallel I/O and DUART Interface
CP
M
Alt. DUARTAlt. DUART
Alt. 10/100 Eth.
Alt. 10/100 Eth.
U11
H
MP
C85
40
H1
H2 J1 J2 J3 J4 J5 J6 J7 J8 K8
K7
K6
K3
K2
K1 L1 L2 L3 L4 L5 L8 L9 L10
L11
M10 M9
M8
M7
M6
M3
M2
M1
N1
N4
N5
N6
N7
N8
N9
N10
N11
P11
P10 P9
P8
P7
P6
P5
P4
P3
P2
P1
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
T9
T6
T5
T4
T1
U1
U2
U3
U4
U7
U8
U9
U10
V9
V6
V5
V4
V3
V2
V1
W1
W2
W3
W6
W7
W8
W9
Y9
Y1
Y2
Y3
Y4
Y5
Y6
AA
8A
A7
AA
4A
A3
AA
2A
A1
AB
1A
B2
AB
3A
B5
AB
6A
C7
AC
4A
C3
AC
2A
C1
AD
1A
D2
AD
5A
D6
AE
3A
E2
PA
0P
A1
PA
2P
A3
PA
4P
A5
PA
6P
A7
PA
8P
A9
PA
10P
A11
PA
12P
A13
PA
14P
A15
PA
16P
A17
PA
18P
A19
PA
20P
A21
PA
22P
A23
PA
24P
A25
PA
26P
A27
PA
28P
A29
PA
30P
A31
PB
4/F
EC
_TX
D3
PB
5/F
EC
_TX
D2
PB
6/F
EC
_TX
D1
PB
7/F
EC
_TX
D0
PB
8/F
EC
_RX
D0
PB
9/F
EC
_RX
D1
PB
10/F
EC
_RX
D2
PB
11/F
EC
_RX
D3
PB
12/F
EC
_CR
SP
B13
/FE
C_C
OL
PB
14/F
EC
_TX
_EN
PB
15/F
EC
_TX
_ER
PB
16/F
EC
_RX
_ER
PB
17/F
EC
_RX
_DV
PB
18P
B19
PB
20P
B21
PB
22P
B23
PB
24P
B25
PB
26P
B27
PB
28P
B29
PB
30P
B31
PC
0P
C1
PC
2P
C3
PC
4P
C5
PC
6P
C7
PC
8P
C9
PC
10P
C11
PC
12P
C13
/UA
RT
_CT
S1
PC
14P
C15
/UA
RT
_CT
S0
PC
16P
C17
/FE
C_R
X_C
LKP
C18
/FE
C_T
X_C
LKP
C19
PC
20P
C21
PC
22P
C23
PC
24P
C25
PC
26P
C27
PC
28P
C29
PC
30P
C31
PD
4P
D5
PD
6P
D7
PD
8P
D9
PD
10P
D11
PD
12P
D13
PD
14P
D15
PD
16P
D17
PD
18P
D19
PD
20P
D21
PD
22P
D23
PD
24P
D25
PD
26/U
AR
T_R
TS
1P
D27
/UA
RT
_SO
UT
1P
D28
/UA
RT
_SIN
1P
D29
/UA
RT
_RT
S0
PD
30/U
AR
T_S
OU
T0
PD
31/U
AR
T_S
IN0
SO
UT
1
SO
UT
0
SIN
1
SIN
0
CompactPCI Reference Design, Rev. 1
20 Freescale Semiconductor
Example Interface Schematics
Figure 17. MPC8540 Power Connections
+3.
3V
+1.
2V
C71
10uF
C49 0.
1uF
C33 0.
1uF
C60
0.1u
F
C46 0.
1uF
PO
WE
R
U11
I
MP
C85
40
AE
1D
1T
2N
3H
3A
H4
AD
4W
4K
4E
4A
C5
AA
5U
5M
5A
F7
AB
7Y
7T
7 L7A
E8
V8
AB
9A
E10
K10
AC
11A
F12
AA
12W
13A
E15
AA
16A
C17
W19
R19
AA
20U
20W
21P
22Y
23R
25A
B26
U26
AG
27
AF
2N
2C
2A
G3
AD
3T
3E
3B
3A
F4
AB
4M
4H
4C
4W
5K
5A
C6
AA
6U
6 L6A
G7
V7
AD
8Y
8T
8D
8A
C9
K9
G9
AF
10V
10T
10A
B11
F11
C11
T12
P12
M12
H12
G12
E12
A12
AF
13A
A13
U13
R13
N13
T14
P14
M14
H14
B14
AF
15U
15R
15N
15Y
16U
16T
16P
16M
16A
D17
U17
R17
N17
H17
C17
A17
W18
K18
F18
AB
19J1
9C
19R
20L2
0H
20B
20U
21M
22H
22C
22W
23P
23K
23F
23J2
4E
24L2
5G
25A
G26
V26
R26
B26
AF
27M
27H
27C
27B
27K
28
OV
dd1
OV
dd2
OV
dd3
OV
dd4
OV
dd5
OV
dd6
OV
dd7
OV
dd8
OV
dd9
OV
dd10
OV
dd11
OV
dd12
OV
dd13
OV
dd14
OV
dd15
OV
dd16
OV
dd17
OV
dd18
OV
dd19
OV
dd20
OV
dd21
OV
dd22
OV
dd23
OV
dd24
OV
dd25
OV
dd26
OV
dd27
OV
dd28
OV
dd29
OV
dd30
OV
dd31
OV
dd32
OV
dd33
OV
dd34
OV
dd35
OV
dd36
OV
dd37
OV
dd38
OV
dd39
OV
dd40
OV
dd41
OV
dd42
GN
D1
GN
D2
GN
D3
GN
D4
GN
D5
GN
D6
GN
D7
GN
D8
GN
D9
GN
D10
GN
D11
GN
D12
GN
D13
GN
D14
GN
D15
GN
D16
GN
D17
GN
D18
GN
D19
GN
D20
GN
D21
GN
D22
GN
D23
GN
D24
GN
D25
GN
D26
GN
D27
GN
D28
GN
D29
GN
D30
GN
D31
GN
D32
GN
D33
GN
D34
GN
D35
GN
D36
GN
D37
GN
D38
GN
D39
GN
D40
GN
D41
GN
D42
GN
D43
GN
D44
GN
D45
GN
D46
GN
D47
GN
D48
GN
D49
GN
D50
GN
D51
GN
D52
GN
D53
GN
D54
GN
D55
GN
D56
GN
D57
GN
D58
GN
D59
GN
D60
GN
D61
GN
D62
GN
D63
GN
D64
GN
D65
GN
D66
GN
D67
GN
D68
GN
D69
GN
D70
GN
D71
GN
D72
GN
D73
GN
D74
GN
D75
GN
D76
GN
D77
GN
D78
GN
D79
GN
D80
GN
D81
GN
D82
GN
D83
GN
D84
GN
D85
GN
D86
GN
D87
GN
D88
GN
D89
GN
D90
GN
D91
GN
D92
GN
D93
GN
D94
GN
D95
GN
D96
GN
D97
GN
D98
GN
D99
C37 0.
1uF
C62
0.1u
F
CO
RE
&P
LL
S
up
ply
U11
E
MP
C85
40
U12
R12
T13
P13
M13
U14
R14
N14
T15
P15
M15
R16
N16
T17
P17
M17
AH
19A
H18
AH
17
L12
K12
VD
D1
VD
D2
VD
D3
VD
D4
VD
D5
VD
D6
VD
D7
VD
D8
VD
D9
VD
D10
VD
D11
VD
D12
VD
D13
VD
D14
VD
D15
VD
D16
AV
dd1
AV
dd2
AV
dd3
SE
NS
E_V
DD
SE
NS
E_V
SS
C41 0.
1uF
C57 10
uF
C48 0.
1uF
C52 0.
1uF
C54 10
uF
C67
0.1u
F
C45 0.
1uF
C36 0.
1uF
C61
0.1u
F
C40 0.
1uF
C64
0.1u
F
C56 10
uF
C69
10uF
C51 0.
1uF
C53 10
uF
C59
0.1u
F
C44 0.
1uF
C35 0.
1uF
C63
0.1u
F
C58 10
uF
C39 0.
1uF
C42 0.
1uF
C68
0.1u
F
C55 10
uF
C70
10uF
C50 0.
1uF
C43 0.
1uF
C34 0.
1uF
C65
0.1u
F
C47 0.
1uF
C38 0.
1uF
C66
0.1u
F
CompactPCI Reference Design, Rev. 1
Freescale Semiconductor 21
Example Interface Schematics
Figure 18. Compact PCI J1 and J2 Connectors
Connector J1
Connector J2
PC
I17
AD
17
PC
I30
AD
30
PC
I82
PE
RR
*
PC
I3A
D3
PC
I5A
D5
PC
I33
AD
33
AD
27P
CI2
7
AC
K64
*P
CI8
1
AD
25P
CI2
5
PC
I18
AD
18
PC
I80
RE
Q64
*
PC
I10
AD
10
PC
I16
AD
16
PC
I78
DE
VS
EL*
AD
58P
CI5
8
ST
OP
*P
CI7
7
PC
I6A
D6
AD
53P
CI5
3
AD
43P
CI4
3
AD
55P
CI5
5
C_B
E5
PC
I69
PC
I45
AD
45
PC
I79
IDS
EL*
PC
I26
AD
26
PC
I61
AD
61
PC
I8A
D8
AD
40P
CI4
0
PC
I31
AD
31
AD
0P
CI0
PC
I37
AD
37A
D32
PC
I32
AD
57P
CI5
7
AD
35P
CI3
5
PC
I75
TR
DY
*
PC
I13
AD
13
AD
22P
CI2
2
AD
11P
CI1
1
PC
ICLK
PC
I86
PC
I15
AD
15
AD
46P
CI4
6
C_B
E4
PC
I68
PC
I62
AD
62
AD
14P
CI1
4
PC
I34
AD
34
PC
I85
GN
T0
PC
I83
SE
RR
*
C_B
E6
PC
I70
AD
49P
CI4
9
PC
I7A
D7
C_B
E7
PC
I71
PC
I67
C_B
E3
PC
I47
AD
47
PC
I59
AD
59
PC
I23
AD
23
AD
41P
CI4
1
PC
I4A
D4
AD
44P
CI4
4
AD
36P
CI3
6
AD
60P
CI6
0
PC
I38
AD
38
C_B
E2
PC
I66
PC
I28
AD
28P
CI2
4A
D24
PC
I1A
D1
PC
I74
FR
AM
E*
PC
I29
AD
29P
CI8
4R
EQ
0
C_B
E1
PC
I65
AD
2P
CI2
PC
I52
AD
52
PA
RP
CI7
2
PC
I20
AD
20P
CI2
1A
D21
AD
54P
CI5
4A
D50
PC
I50
C_B
E0
PC
I64
PC
I19
AD
19
PC
I76
IRD
Y*
PA
R64
PC
I73
PC
I48
AD
48P
CI5
1A
D51
AD
39P
CI3
9A
D42
PC
I42
PC
I9A
D9
AD
63P
CI6
3
PC
I12
AD
12 AD
56P
CI5
6
+5V
+5V
+3.
3V
+5V
+5V
+5V
+3.
3V
+3.
3V
+5V
+3.
3V
+5V
+5V
+3.
3V
J1A
CO
NN
6x25
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
J1B
CO
NN
6x25
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
J1C
CO
NN
6x25
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
J1D
CO
NN
6x25
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
J1E
CO
NN
6x25
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
J1F
CO
NN
6x25
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
J2A
CO
NN
6x22
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
J2B
CO
NN
6x22
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
J2C
CO
NN
6x22
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
J2D
CO
NN
6x22
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
J2E
CO
NN
6x22
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
J2F
CO
NN
6x22
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
PC
I[0:8
6]
CompactPCI Reference Design, Rev. 1
22 Freescale Semiconductor
Example Interface Schematics
Figure 19. Clock and Reset Logic
SY
S_H
RE
SE
T_N
+3.
3V+
3.3V
+3.
3V
+3.
3V
+3.
3V
S5
Res
et S
witc
h
R25
81K
MPC9448
U14
MP
C94
48
31 29 27 25 23 21 19 17 15 13 11 9
3 4 2 1 5 6 7 10 14 18 22 26 30
8 12 16 20 24 28 32
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
PC
LKP
CLK
CC
LK
CLK
_SE
L
CLK
_ST
OP
OE
VC
CV
CC
VC
CV
CC
VC
CV
CC
VC
C
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
D
R25
71K
C72
0.1u
F
U15
MA
X63
14
32
4
1
MR
RE
SE
TV
DD
GND
Y1
66M
Hz
85
4
VD
DO
UT
GN
D
SY
S_H
RE
SE
T*
SY
SC
LKA
CompactPCI Reference Design, Rev. 1
Freescale Semiconductor 23
Example Interface Schematics
Figure 20. Local Power Supply Logic
This sets 1.2V
Note :- Default settings for Switchs
D4 D3 D2 D1 D0
0 0 1 1 1
+3.
3V
+1.
2V
+2.
5V
+5V
+5V
+5V
SW
3
SW
SP
DT
MAX1624
U18
MA
X16
24
2 7 56 17 16 8 15 14 13 10
1112191822212324134
9
20
PW
RO
K
D0
D2
D1
D3
D4
LG FR
EQ
CC
2
CC
1
RE
F
AG
NDFB
PD
RV
ND
RV
PG
NDDL
LXDH
BS
T
CS
L
CS
H
VCC
VDD
C90
1.0u
F C
ER
AM
IC
R26
740
.1K
R26
82K
C75
0.47
uF
+C
77
150u
FR
260
9K1
+C
8030
0uF
C86
0.1u
FS
W4
SW
SP
DT
R26
110
K
U16 MA
X16
27
8
2
14
7
5 3
6
GN
D
FB
OU
T
RE
F
EX
T
V+
SH
DN
CS
C76
0.1u
F
C78
0.1u
F
C89
0.6n
F
R26
439
R
C88
0.56
uF
L2 79nH
12
D3
1N58
20
21
R26
51.
7mC
854.
7nF
+C
794.
7uF
Q1
MT
B50
N06
VL
+C
873.
6mF
C82
0.1u
F
SW
2
SW
SP
DT
U17
MM
SF
3P02
HD
4
2
1
3
5 6 7 8
G
S1
N/C
S2 D1
D2
D3
D4
+C
74
68uF
L1 10uH
, 2.5
A
R25
9
R04
7
R26
639
R
C84
4.7n
F
SW
1
SW
SP
DT
R26
2
100K
D4 CM
PS
H-3
Q2
MT
B50
N06
VL
+C
834.
7uF
+C
73
68uF
R26
310
0K
C81
0.1u
F
CompactPCI Reference Design, Rev. 1
24 Freescale Semiconductor
Example Interface Schematics
Figure 21. Gb Ethernet Transceiver
LNK_10
AUTO-NEGOTIATION
ADVERTISE ALL CAPABILITIES
PREFER SLAVEDE
SC
RIP
TIO
N
TX
010
GMII TO COPPER MODE
Pin
To
Co
nfi
gu
rati
on
Co
nst
ant
Map
pin
g
LE
D_L
INK
1000
RX
110
MDC/MDIO INTERFACE
INT SIGNAL IS ACTIVE HIGH
50 OHM TERMINATION
DPLX
CO
NF
IG2
VD
DO
_3_3
V
CO
NN
EC
TIO
N
000
LE
D_L
INK
100
ENABLE 125 MHZ CLOCK
ENABLE MDI CROSSOVER
ENABLE AUTO
NEGOTIATION
CO
NF
IG3
BIT
[2:0
]
NO
TE
:S
EL
_2_5
V P
IN T
IED
TO
GN
D F
OR
3.3
VI/O
ENABLE PAUSE
PHYADR[4] = 0
PHYADR[3] = 0
CO
NF
IG1
100
LE
D_L
INK
10
111
111
CO
NF
IG5
LE
D_R
X
PIN
GN
D
Local 1.5V
supply for
PHY
VD
DO
_3_3
V
PHYADR[2] = 0, PHYADR[1] = 0, PHYADR[0] = 0
LNK_1000
DISABLE AUTO SELECTION OF FIBER/COPPER INTERFACE
ENABLE ENERGY DETECT
GMII TO COPPER
101
CO
NF
IG6
CO
NF
IG0
LNK_100
CO
NF
IG4
RXD4
GND_C7
MD
I2_P
A
DVDDL_G7A
RXD7
GN
D_K
6
DVDDL_G7A
GND_E5
RX
_CLK
GND_H4
MD
I1_P
A
GND_G5
TXD3
GND_F6
AV
DD
L_M
3
HD
AC
_NA
CLK
25
LED
_DU
PLE
XA
CONFIG_4
GND_G5
GND_J5
AVDDL_L2
AV
DD
L_M
8
ETH
ER
A15
RX
D1
VDDO_C6
LED
_TX
A
GN
D_L
4
GND_L6
TXD6
VDDO_C5
ETH
ER
A16
RX
D2
VSSC
LED_DUPLEXA
GND_F6
GND_H4
ETH
ER
A24
RX
_CLK
GND_G6
GND_L7
RXD3
GN
D_J
5
MD
I3_M
A
ETH
ER
A11
GTX
_CLK
LED_LINK_1000A
LED_RXA
GND_D6
GND_H5
GND_J4
DVDDL_H3A
AV
DD
L_M
7
GND_G4
ETH
ER
A2
TXD
2
LED_LINK_100A
GND_K3
RX
_ER
CLK25
AVDDL_M7
MD
I1_M
A
GND_D4
MD
I0_P
A
AVDDL_M3
AVDDL_B1
RX
D2
ETH
ER
A22
RX
_DV
LED
_LIN
K_1
0A
TXD2
GND_K3
GND_H6
GND_E4
LED_TXA
VDDO_H7
VDDO_E7
DVDDL_E3A
GND_J4
MD
I1_P
A
GND_G6
GND_E6
CO
L
LED_LINK_100A
MD
I2_M
A
TX_E
N
MDI0_PA
VDDO_E7
ETH
ER
A23
RX
_ER
GN
D_L
5
VD
DO
_C6
GN
D_C
4
GND_D6
LED_LINK_10A
ETH
ER
A17
RX
D3
ETH
ER
A0
TXD
0
ETH
ER
A19
RX
D5
DVDDL_E3A
TXD5
MD
I1_M
A
GND_D5
TXD4
AVDDL_M8
GND_F4
GN
D_L
7
GN
D_K
5
GND_H6
ETH
ER
A14
RX
D0
GND_F5
ETH
ER
A18
RX
D4
GND_L5
GND_F4
GND_F5
RXD5
ETH
ER
A13
CO
L
LED_LINK_10A
GND_G4
RX
D0
LED
_LIN
K_1
00A
ETH
ER
A9
TX_E
R
TXD
0
TXD1
GND_C7
ETH
ER
A1
TXD
1
VD
DO
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RXD6
MD
I2_M
A
VSSC
VDDO_J3
GN
D_D
5
GND_J6
TX_C
LK
TX_E
R
MD
I0_M
A
AVDDH_N5
CR
S
AVDDL_L2
MD
I2_P
A
ETH
ER
A4
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4
ETH
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N
DVDDL_D7A
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A
LED
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K_1
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LED_RXA
GND_L3
LED
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A
GND_E6
ETH
ER
A3
TXD
3
TXD7
CONFIG_2
GND_K5GND_K6
GND_L4
RX
D1
DVDDL_D7A
ETH
ER
A5
TXD
5
MD
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A
AV
DD
L_B
1
GN
D_L
6
GND_E4
ETH
ER
A10
TX_C
LK
LED_LINK_1000A
VDDO_H7
GND_J6
RX
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GTX
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GND_E5
VDDO_J3
GND_K4
ETH
ER
A12
CR
S
ETH
ER
A21
RX
D7
ETH
ER
A20
RX
D6
ETH
ER
A6
TXD
6
MD
I3_P
A
MD
I0_M
A
GND_C4
DVDDL_H3A
GND_H5
GND_L3
ETH
ER
A7
TXD
7
AV
DD
H_N
5
HD
AC
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GN
D_D
4
MD
IO
MD
C
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5V
VD
DO
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DO
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VD
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DD
L_1_
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VDDO_3_3V
AV
DD
L_2_
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AV
DD
L_2_
5V
VD
DO
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L_1_
5V
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AV
DD
L_2_
5V
AV
DD
L_2_
5V
+3.
3V
+1.
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AV
DD
H_3
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AV
DD
L_2_
5V
+1.
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VD
DO
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V
AV
DD
H_3
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C99
0.01
uF
R28
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1:1
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Pu
lse
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1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
TCT1
TD1_
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TD1_
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TCT2
TD2_
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TD2_
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TCT3
TD3_
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TCT4
TD4_
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MC
T1
MX
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MC
T2
MX
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2_M
MC
T3
MX
3_P
MX
3_M
MC
T4
MX
4_P
MX
4_M
C11
3
0.1u
F
R28
875
+C
9810
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R2762.49K 1%R
291
75
R28
949
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R28
449
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+C
934.
7UF
C94
0.1u
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C11
1
0.1u
F
Y2
25M
Hz
85
4
VD
DO
UT
GN
D
R29
049
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C92
0.1u
F
C11
5 0.1u
F
R27
0
332
R2754.7K
D5 LED_GREEN
R27
749
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R26
9
332
D6 LED_GREEN
R28110K
C10
4
0.01
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C10
9
0.1u
F
C10
6 0.1u
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C11
8
0.01
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C10
1
0.1u
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D7 LED_GREEN
C95
0.01
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C10
2
0.01
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D8 LED_GREEN
D10 LED_GREEN
R28
649
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C11
4
0.01
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R28
349
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C91
0.1u
F
U19
M88
E10
11
A8
B7
A7
A6
B6
C6
B4
A5
B5
C5
D5
D4
C4
A4
C3
B3
A3
B2
A2
A1
B1
C1
C2
D1
D2
H1
D3
E1
E2
G4
E3
E4
F1
F2
G1
F3
F4
G2
G3
G5
H2
H3
H4
H5
J1
J2
J3
J4
K1
K2
K3
K4
L2
L1
L3
M1
M2
N1
N2
M3
N3
L4 M4
N4
J5 K5
L5 M5
N5
L6 M6
K6
N6
N7
L7 M7
N8
M8
N9
M9
L8
L9
K9
K8
K7
J9
J7
J8
J6
H7
H9
H6
H8
G7
G6
G9
G8
F7
F9
F6
F8
F5
E6
E8
E5
E7
E9
D9
D8
D7
D6
C7
C8
C9
B8
B9
A9
RX
D_2
RX
D_1
RX
D_0
RX
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RX
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VD
DO
TX_C
LK
CO
L
RX
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VD
DO
GN
D
GN
D
GN
D
CR
S
SCLK_M
GTX
_CLK
TX_E
R
TXD
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TX_E
N
CO
MA
AV
DD
L
SIN_M
SOUT_M
SIN_P
SOUT_P
TXD_6
SCLK_P
TXD_1
CTRL_15
GND
DVDDL
GND
TXD_2
TXD_3
TXD_4
DVDDH
GND
TXD_5
DVDDH
GND
TXD_7
DVDDL
GND
GND
XTAL2
XTAL1
VDDO
GND
TCK
RESET
VSSC
GND
AVDDL
TMS
GND
TRST
RST
MDI0_P
MD
I0_M
AV
DD
L
MD
I1_P
GN
D
CTR
L_25
MD
I1_M
GN
D
GN
D
GN
D
HD
AC
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AV
DD
H
GN
D
HD
AC
_N
GN
D
MD
I2_P
MD
I2_M
GN
D
AV
DD
L
MD
I3_P
AV
DD
L
MD
I3_M
TDI
TDO
CONFIG_4
CONFIG_3
CONFIG_2
CONFIG_6
CONFIG_1
CONFIG_5
CONFIG_0
GND
VDDO
LED_TX
GND
LED_RX
DVDDL
GND
LED_DPLX
LED_LINK1000
SEL_2_5V
LED_LINK100
GND
LED_LINK10
GND
GND
MDC
GND
VDDO
INT
MDIO
CLK125
DVDDL
GND
GND
RXD_6
RXD_7
RXD_3
RXD_5
RXD_4
LT1763CS8-1.5
U20
LT17
63C
S8
8 5
3421
6 7
VIN
SH
DN
GN
D
BY
P
SE
NS
E
VO
UT
GN
D
GN
D
C11
2
0.01
uF
D9 LED_GREEN
R28
749
.9
C11
7 0.1u
F
R27
1
332
C11
6
0.01
uF
R28
275
C96
0.1u
F
R27
949
.9
R27
2
332
R29
249
.9
R27
3
332
C10
8 0.1u
F
R27
4
332
C10
0 1000
P/3
KV
C10
7
0.01
uF
C11
0
0.01
uF
R29
349
.9
C10
5
0.1u
F
CO
N1
RJ4
5
12345678
DA
_P
DA
_M
DB
_P
DC
_P
DC
_M
DB
_M
DD
_P
DD
_M
R27
8
22R
C10
3
0.1u
F
C97
0.01
uF
SY
S_H
RE
SE
T*
GTX
_CLK
125
MD
C
MD
IO
ETH
ER
A[0
:24]
CompactPCI Reference Design, Rev. 1
Freescale Semiconductor 25
Example Interface Schematics
Figure 22. RS232 Interface Logic
Not
e P
olar
ity
+3.
3V
+C
119
0.1u
F
+
C12
1
0.1u
F
P1
D9
Con
nect
or
162738495
+C
122
0.1u
F
U22
MA
X32
32
13 14 8 7 2 15
912 11 10 6 164 5
1 3
R1I
N
T1O
UT
R2I
N
T2O
UT
V+
GN
D
R2O
UT
R1O
UT
T1I
N
T2I
N V-
VC
C
C2+ C2-
C1+
C1-
P2
D9
Con
nect
or
162738495
+C
120
0.1u
F
+C
123
0.1u
F
SIN
0
SIN
1
SO
UT
0
SO
UT
1
CompactPCI Reference Design, Rev. 1
26 Freescale Semiconductor
Example Interface Schematics
Figure 23. Optional RapidIO Connector
Gu
ide
Pin
Gu
ide
Pin
RIO
19R
IO_T
D7*
RIO
31R
IO_R
D3*
RIO
20R
IO_R
CLK
RIO
_TD
0*
RIO
_TC
LK*
RIO
_TD
6
RIO
27R
IO_R
D1*
RIO
25R
IO_R
D0*
RIO
15R
IO_T
D5*
RIO
34R
IO_R
D5
RIO
30R
IO_R
D3
RIO
32R
IO_R
D4
RIO
_TD
2
RIO
_RD
0*
RIO
36R
IO_R
D6
RIO
_TF
RA
ME
RIO
_RD
5
RIO
18R
IO_T
D7
RIO
16R
IO_T
D6
RIO
4R
IO_T
D0
RIO
_TD
5
RIO
_RD
4
RIO
_RD
2
RIO
2R
IO_T
FR
AM
E
RIO
0R
IO_T
CLK
RIO
10R
IO_T
D3
RIO
_TD
3*
RIO
_TD
7
RIO
_RD
7
RIO
26R
IO_R
D1
RIO
14R
IO_T
D5
RIO
_TD
6*
RIO
_RF
RA
ME
*
RIO
_RD
2*
RIO
_RD
1
RIO
_RD
0
RIO
3R
IO_T
FR
AM
E*
RIO
23R
IO_R
FR
AM
E*
RIO
_TD
1*
RIO
_TD
4*
RIO
_TD
7*R
IO_R
D1*
RIO
8R
IO_T
D2
RIO
33R
IO_R
D4*
RIO
_RD
6*
RIO
9R
IO_T
D2*
RIO
1R
IO_T
CLK
*
RIO
13R
IO_T
D4*
RIO
_TD
4
RIO
_RD
5*
RIO
39R
IO_R
D7*
RIO
11R
IO_T
D3*
RIO
_RF
RA
ME
RIO
_RD
3
RIO
7R
IO_T
D1*
RIO
_TD
3
RIO
_RD
6
RIO
35R
IO_R
D5*
RIO
12R
IO_T
D4
RIO
5R
IO_T
D0*
RIO
21R
IO_R
CLK
*
RIO
_TF
RA
ME
*
RIO
_TD
1
RIO
_TC
LK
RIO
38R
IO_R
D7
RIO
37R
IO_R
D6*
RIO
_TD
2*
RIO
_TD
0
RIO
_RC
LK*
RIO
_RD
3*
RIO
17R
IO_T
D6*
RIO
6R
IO_T
D1
RIO
29R
IO_R
D2*
RIO
22R
IO_R
FR
AM
E
RIO
_TD
5*
RIO
_RD
4*
RIO
_RC
LK
RIO
28R
IO_R
D2
RIO
24R
IO_R
D0
RIO
_RD
7*
+3.
3V
+5V
AB
CD
EF
GH
BG
DG
FG
HG
AB
CD
EF
GH
J4
1460
902-
2
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10B1
B2
B3
B4
B5
B6
B7
B8
B9
B10C1
C2
C3
C4
C5
C6
C7
C8
C9
C10D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
BG
1
BG
2
BG
3
BG
4
BG
5
BG
6
BG
7
BG
8
BG
9
BG
10
DG
1
DG
2
DG
3
DG
4
DG
5
DG
6
DG
7
DG
8
DG
9
DG
10
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
HG
1
HG
2
HG
3
HG
4
HG
5
HG
6
HG
7
HG
8
HG
9
HG
10
FG
1
FG
2
FG
3
FG
4
FG
5
FG
6
FG
7
FG
8
FG
9
FG
10
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
BG
1
BG
2
BG
3
BG
4
BG
5
BG
6
BG
7
BG
8
BG
9
BG
10
DG
1
DG
2
DG
3
DG
4
DG
5
DG
6
DG
7
DG
8
DG
9
DG
10
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10G1
G2
G3
G4
G5
G6
G7
G8
G9
G10F1
F2
F3
F4
F5
F6
F7
F8
F9
F10E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
HG
1
HG
2
HG
3
HG
4
HG
5
HG
6
HG
7
HG
8
HG
9
HG
10
FG
1
FG
2
FG
3
FG
4
FG
5
FG
6
FG
7
FG
8
FG
9
FG
10
J3
2239
56-1
1
ABCJ6
2239
55-2
A1
A2
A3
A4
B1
B2
B3
B4
C1
C2
C3
C4
J7
2239
56-1
1
ABCJ5
2239
55-2
A1
A2
A3
A4
B1
B2
B3
B4
C1
C2
C3
C4
RIO
[0:3
9]
CompactPCI Reference Design, Rev. 1
Freescale Semiconductor 27
Example Interface Schematics
Figure 24. MPC8540 COP Debug Connector
CO
P_S
RE
SE
T
DE
BU
G5
CO
P_H
RE
SE
T
CO
P_T
MS
CO
P_T
CK
CO
P_T
DI
DE
BU
G1
CO
P_T
DI
DE
BU
G2
CO
P_T
DO
DE
BU
G0
CO
P_T
CK
CO
P_H
RE
SE
TD
EB
UG
4C
OP
_TR
ST
DE
BU
G3
CO
P_T
MS
CO
P_T
DO
DE
BU
G6
CO
P_S
RE
SE
T
DE
BU
G7
CO
P_C
KS
TP
_IN
*
DE
BU
G8
CO
P_C
KS
TP
_OU
T*
CO
P_C
KS
TP
_IN
*
CO
P_C
KS
TP
_OU
T*
CO
P_T
RS
T
+3.
3V+
3.3V
R29
410
KR
297
10K
R29
92K
R29
810
KR
300
10K
R29
610
KR
295
10K
KEY
J8 CO
PC
ON
N
1516
12
34
56
78
910
1112
1314
DE
BU
G[0
:8]
CompactPCI Reference Design, Rev. 1
28 Freescale Semiconductor
Document Revision History
5 Document Revision HistoryTable 2 provides a revision history for this white paper.
Table 2. Document Revision History
Revision Date Change(s)
1 11/2004 Template update. Updated schematics related to DDR hook-up.
0 8/2003 Initial release.
CompactPCI Reference Design, Rev. 1
Freescale Semiconductor 29
Document Revision History
THIS PAGE INTENTIONALLY LEFT BLANK
CompactPCI Reference Design, Rev. 1
30 Freescale Semiconductor
Document Revision History
THIS PAGE INTENTIONALLY LEFT BLANK
CompactPCI Reference Design, Rev. 1
Freescale Semiconductor 31
Document Revision History
THIS PAGE INTENTIONALLY LEFT BLANK
MPC8540PCIWPRev. 111/2004
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