an2170 application note · june 2005 1/16 an2170 application note mosfet device effects on phase...

1/16June 2005

AN2170APPLICATION NOTEMOSFET Device Effects on

Phase Node Ringing in VRM Power Converters

Rev 1

INTRODUCTIONThe growth in production volume of industrial equipment (e.g., power DC-DC converters devoted to low-medium-voltage applications) has dramatically increased in recent years. This widespread increase oc-curred along with a similar production increase of power MOSFET devices, due to their higher switchingperformance and ease of control with respect to bipolar transistors. High-tech products require more andhigher performance devices because of advancing specifications and a growing demand for highly effi-cient systems and equipment, such as PC motherboards, power supplies, and hand tools. These stringentrequirements demand innovation from power device designers, who must design to performance specifi-cations, including suitable On-state resistance and gate-charge values, as well as high reliability charac-teristics which help to reduce wasted power.The last generation of low voltage Power MOSFETs has achieved very impressive performances in termsof Figure of Merit (FOM) RON*Qg. These switches have very low static loss, increased switching speed,and very low driving energy requirements. However, these higher performing devices have also highlight-ed some undesired phenomena already present in their application.– In particular, the fast voltage transition of the phase node can cause the inadvertent turn-on of the low-

side switch, resulting in a converter malfunction and reducing efficiency.– Another consequence of the increased switching speed is the ringing phenomenon, which occurs on

the phase node of a Buck converter used as a Voltage Regulated Module (VRM). Although this ringing does not cause power loss (because of the fairly high Q), it could induce some sort of malfunction and/or undesired stress of the power switches.

For these reasons, it is useful to understand the main parameters, their influence, and possible ways tominimize undesired effects.

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AN2170 - APPLICATION NOTE

TABLE OF CONTENTS

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

CdV/dt-INDUCED TURN-ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 1. Buck Converter Simplified Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Figure 2. Buck Converter Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Figure 3. Low-Side Switch Current Paths, Control MOSFET Turned On . . . . . . . . . . . . . . . . . . . . . 5Figure 4. Minimum dV/dt to Cause VGS > VTH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

VOLTAGE RINGING ON THE PHASE NODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 5. Switching Waveforms with Voltage Ringing on the Phase Node. . . . . . . . . . . . . . . . . . . . 6Stray Inductance Effects on Phase Node Over Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Figure 6. Energizing of L, L1, L2, L3 During Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Figure 7. Turn-on of the Upper Device and Over-Voltage Phenomenon . . . . . . . . . . . . . . . . . . . . . 7

APPROACHES TO VOLTAGE PHASE NODE RINGING REDUCTION . . . . . . . . . . . . . . . . . . . . . . . . 8

PCB Layout Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Figure 8. VRM Converter Experimental Set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Table 1. VRM Converter Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Changing the Low-Side Switch Gate Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Using a Snubber Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Figure 9. Gate Resistance Effect on Strip MOSFET Switching: Without External Gate Resistance10Figure 10.Gate Resistance Effect on Strip MOSFET Switching: With 3.3Ω Gate Resistance . . . . 10Figure 11.Snubber Circuit Effect on Strip MOSFET Switching: Without Snubber . . . . . . . . . . . . . . 11Figure 12.Snubber Circuit Effect on Strip MOSFET Switching: With Snubber . . . . . . . . . . . . . . . . 11Figure 13.Snubber Circuit, Cross-Conduction Effects on the VRM Efficiency . . . . . . . . . . . . . . . . 12

CONCLUSION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

APPENDIX A.VOLTAGE OSCILLATION SPIKE POTENTIAL ANALYSIS . . . . . . . . . . . . . . . . . . . . . 13

Figure 14.Simplified Equivalent Circuit During Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Figure 15.Definition of Peak Voltage and Oscillation Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . 13Peak Voltage and Oscillation Frequency Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 2. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

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CdV/dt-INDUCED TURN-ONWith buck converters dedicated to VRM applications (see Figure 1. and Figure 2.), it is essential that theuser chooses the appropriate pair of switching MOSFETs. Devices having quite similar nominal charac-teristics can behave in a very different manner, leading to an appreciably altered overall system efficiency.This is especially the case with the switching behavior of a high-side switch which has a significant effecton the low-side switch. The rise speed of the phase node when the high-side device switches on couldhave two detrimental effects, depending on the device characteristics and how fast the voltage transitionis.

Figure 1. Buck Converter Simplified Schematic

Figure 2. Buck Converter Waveforms

PhaseNode

ControlIC VO

SW2

SW1 L

C+

VIN

AI11108

+–

VGS (SW1)

VGS (SW2)

Dead Time

ISW1 IL

IL

IL

ISW2

ID_SW2

tON tOFF

TS

δTS

AI11109

(1 – δ)TS

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The fast turn-on of the high-side switch (the control MOSFET) could induce a parasitic turn-on of the syn-chronous MOSFET, thus causing undesired conduction. This cross-conduction may originate from an im-proper dynamic polarization of the gate of the low-side device. Despite the fact that the gate is forced toGround by the control driver (see Figure 3., page 5), the capacitive divider that is formed by the parasiticcapacitances CGATE-DRAIN (CGD) and CGATE-SOURCE (CGS) forces the gate voltage of the low-side switchto increase, and the threshold voltage of the device can be overcome. The drain-source voltage rate-of-change leads to a current injection into the MOSFET gate, thus increasing the voltage at the gate node.If the voltage rise time of the phase node (see Figure 3. and Figure 4., page 5) is much less than the timeconstant of the equivalent gate circuit of the low side switch (1),

then the maximum gate voltage is described by the following equation (2):

Since a spurious turn-on causes power loss, which in turn leads to decreased efficiency, any way to avoidit is highly recommended. As shown in the maximum gate voltage equation (2), it is obvious that in orderto reduce the possibility of spurious turn-on of the low-side switches, the expression, “CGD/(CGS + CGD)”deserves particular attention on the part of device designers. In fact, the amplitude of the gate voltagepeak is dependent on the absolute value of the intrinsic capacitances of the device, as well as on the ca-pacitive divider at the gate node (which also needs to be considered). In other words, in order to reducethe detrimental effects of fast variations of the drain node potential on the gate node, designers need toachieve a well-balanced capacitive divider and low impedance gate path at the gate node of the low-sideswitch.Additionally, the dV/dt in the drain node can also be responsible for the turn-on of the parasitic transistorin the inner MOSFET structure. If the voltage at the base node of the Bipolar Junction Transistor (BJT)gets over the built-in potential of the base-emitter junction, it can lead to possible device failure.Due to the dV/dt in the drain node, the drain-body capacitance (CDB) produces a current injection in thebase of the parasitic NPN bipolar transistor (see Figure 3.). Therefore, if the voltage drop on the parasiticresistor RB exceeds the base emitter threshold voltage, the parasitic NPN bipolar transistor will turn on.This condition can be expressed by using the following equation (3):

A lot of care has been taken at the Power MOSFET design level to minimize both RB and CDB. The designallows for safe switching even if dV/dt exceeds several volts per nanosecond.

Tm Rt CGS CGD+( )«

VGS max,

CGD

CGD CGS+-----------------------------Vm≅

CDB

dVDSdt

--------------VBERB----------=

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Figure 3. Low-Side Switch Current Paths, Control MOSFET Turned On

Figure 4. Minimum dV/dt to Cause VGS > VTH

ZGS

CDB

RB

a

AI11110

CGD

NPNdVdt

Source

Drain

Gate

CGS

b

t Tm

VDS

VGSVTH

Vm

AI11111

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VOLTAGE RINGING ON THE PHASE NODEAnother phenomenon can be caused by the concurrent effect of the high switching speed, the stray induc-tance of the board, and the parasitic capacitance of both the MOSFET and the eventual schottky diode. Itis the presence of wide voltage oscillations on the so-called “phase node” (see Figure 5.).The parasitic inductance is energized during the synchronization cycle as it is depicted in Figure6., page 7. However, as long as the high-side switch is turned-on (see Figure 7., page 7), the energy thathas been previously stored in the inductor will lead to voltage oscillations with potentially dangerous volt-age spikes. A theoretical analysis of this phenomenon using a simple, comparable circuit is given in AP-PENDIX A., page 13, which explains some of the relationships between voltage peak, oscillationfrequency, the dumping factor of some circuitry elements, as well as device characteristics.

Figure 5. Switching Waveforms with Voltage Ringing on the Phase Node

Note: VGS=5V/div, VDS=5V/div, time=100ns/div

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Stray Inductance Effects on Phase Node Over Voltage

The “C” capacitance is equal to the output (COSS) drain-to-source capacitance of the low-side MOSFET.If a Schottky diode is used, its capacitance has to be taken in account as well.Note: “L” is considered the effective stray inductance of the high-side power MOSFET which is added tothe trace inductance of the high-side MOSFET’s source to the low-side drain connection, as well as to thetrace inductance of the low-side ground connection.The same consideration applies to “R,” and oscillations only occur if:

Figure 6. Energizing of L, L1, L2, L3 During Synchronization

Figure 7. Turn-on of the Upper Device and Over-Voltage Phenomenon

R 2 LC----<

Turned OFF

Charge

VCC

L3

L2

C1

+

+

+

–

–

AI11115

Load

High-side

Low-side

L1

L

C

+

+

–

–

ExtraVoltage

VCC

L3

L2

C1

+

+

+

–

–

AI11116

Load

High-side

Low-side

L1

L

C

+

+

–

–

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APPROACHES TO VOLTAGE PHASE NODE RINGING REDUCTIONVoltage phase node ringing is influenced by several parameters. Several circuit approaches may be usedto reduce the severity of this transient:■ Layout Optimization of the Printed Circuit Board (PCB)■ Changing the Low-Side Switch Gate Resistance■ Use a Snubber Circuit

PCB Layout Optimization

This minimizes the effects of the parasitic component controlling this phenomenon, which includes bothstray inductances and capacitances. Good layout technique involves the following:

– The output capacitor positioning such that they are located in symmetrically in relation to the output inductors of the converter (this will minimize the output voltage ripple).

– The inductance and capacitor connections have to be as short as possible, and formed with a wide area of copper.

– A multilayer PCB is required to provide an effective Ground plane.– The MOSFET drive connection should be short, and the high current paths should be wide and

short.Note: In order to attain good thermal exchange, some of the board areas may be used to provide a heat sink to the MOSFETs and diodes.

If PCB optimization is not enough to limit the ringing to the desired value, then a design with an appropriateresistance value and an auxiliary snubber circuit (connected in parallel to the low-side switch device) hasto be considered. The design can be applied to a test circuit to see how it will work with an actual VRM(see Figure 8.). This type of power converter has the following characteristics:– Switching frequency = 300kHz– Rated Input Voltage = 12V– Rated Output Voltage = 1.8V– Rated Current = 10A

Figure 8. VRM Converter Experimental Set-up

High-side

Low-side

ControlIC

VOUT

+

–

VIN

+

–

AI11118

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

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A logic and control IC unit is used to synchronize the gate voltages of the low-side and high-side switchesto provide a suitable dead-time between the two control signals. The output voltage of the buck converteris sensed through a resistive network that acts as the input signal on the IC unit logic for dynamic regula-tion of the output voltage during load variations.The switching behavior of the low-side device has been tested with different solutions. The main electricalcharacteristics of the two switching devices are reported in Table 1.

Table 1. VRM Converter Device Characteristics

Changing the Low-Side Switch Gate Resistor

After the PCB design has been optimized, the next adjustment would the gate resistance of the low-sideswitch. The increased gate resistance value allows for a reduction of voltage ringing (see Figure9., page 10 and Figure 10., page 10).In the experimental results reported for Figure 10., it appears that both the ringing and the voltage spikesare reduced as long as the gate resistance increases. However, with this adjustment, the increased pres-ence of noise that exceeds the gate threshold of the Power MOSFET has also been detected. This causesthe spurious turn-on of the converter which originates from the increased gate impedance, and thereforedecreases the converter efficiency (see Figure 13., page 12).

Using a Snubber Circuit

A more efficient way to reduce the ringing voltage with very few consequences to the converter efficiencyis to use a snubber circuit. Figure 11., page 11 and Figure 12., page 11 illustrate the commutation differ-ence without and with a light RC Snubber (C = 1nF, R = 4.7Ω) connected in parallel to the low-side MOS-FET. The beneficial effect of the snubber circuit on the voltage ringing reduction clearly emerges.Moreover, this solution leads to a low number of voltage spikes and a small efficiency decrease with re-spect to the commutation without the snubber circuit. Figure 13., page 12 demonstrates the converter ef-ficiency with and without the snubber circuit.

Device Type BVDSS [V] VTH (min) [V] RDSon[mΩ] Qg [nC] RG [Ω] COSS [pF]

High-side 30 1.0 8 9 1.2 285

Low-side 30 1.0 3.25 30 2.3 650

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Figure 9. Gate Resistance Effect on Strip MOSFET Switching: Without External Gate Resistance

Note: VGS=5V/div, VDS=5V/div, time=100ns/div.

Figure 10. Gate Resistance Effect on Strip MOSFET Switching: With 3.3Ω Gate Resistance


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Figure 11. Snubber Circuit Effect on Strip MOSFET Switching: Without Snubber


Figure 12. Snubber Circuit Effect on Strip MOSFET Switching: With Snubber


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Figure 13. Snubber Circuit, Cross-Conduction Effects on the VRM Efficiency

CONCLUSIONThe parasitic components of the board and high commutation speed of the strip MOSFET device indicatethe probable presence of high voltage ringing in the phase node. The previously mentioned approaches,such as increasing the gate resistance or using a suitable snubber circuit have been successfully testedand proven to reduce phase node voltage ringing. The use of a small snubber circuit has been observedto significantly reduce the phase node voltage ringing without negatively affecting converter efficiency.

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APPENDIX A. VOLTAGE OSCILLATION SPIKE POTENTIAL ANALYSIS

Figure 14. Simplified Equivalent Circuit During Ringing

Note: Oscillation occurs if R < RLIM.

Figure 15. Definition of Peak Voltage and Oscillation Frequency

R L

CVO

AI11117

T = 1/freq

VPEAK

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Peak Voltage and Oscillation Frequency Analysis

Note: Ringing occurs only if R<Rlim.

Freq 1

2π LC------------------=

VPEAK VO 1 e

πω----–⎝ ⎠

⎛ ⎞

π Γ+( )sin

ω LC--------------------------------------–

⎝ ⎠⎜ ⎟⎜ ⎟⎜ ⎟⎛ ⎞

=

ω 1LC--------

R2L-------⎝ ⎠⎛ ⎞ 2

–=

Γ arcωα----⎝ ⎠⎛ ⎞tan=

α R2L-------=

R Rlim 2 LC----=<

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REVISION HISTORY

Table 2. Document Revision History

Date Version Description

21-Jun-05 1 First edition

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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

© 2005 STMicroelectronics - All rights reserved

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an2170 application note · june 2005 1/16 an2170 application note mosfet device effects on phase...

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