Rev. 0.2 10/06 Copyright © 2006 by Silicon Laboratories AN72

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RING DETECTION/VALIDATION WITH THE Si305X DAAS

1. Overview

This application note is a guide to implementing ringvalidation and detection using the Si305x products.There are several methods available to detect ringingas well as a hardware validation feature to qualify thefrequency and cadence of signals. In addition to ringdetection, these features can also be used for polarityreversal detection, which is required for features, suchas UK caller ID.

2. Ring Detection MethodsRing detection on the Si305x can be achieved usingone of three methods. The first method uses the RGDTpin (available only on the Si3050/56). The second usesthe RDT, RDTP, and the RTDN bits. Finally, the SerialData out pin can be used to detect ringing signals. All ofthese methods require the DSP to qualify the frequencyand cadence of the ringing signal. Alternatively, thehardware ring validation feature discussed can be usedin place of using the DSP to monitor frequency.

On the Si305x products, the ringing signal is resistivelycoupled from TIP and RING to the line side device. Thesignal appearing on these pins can be detected in Full-Wave or Half-Wave mode. Full-wave ring detection isaccomplished by setting the RFWE bit. This bit affectseach of the three methods as discussed below. TheFull-Wave mode can be used to detect polarityreversals during caller ID, etc (excluding the Si3007/8).The actual voltage level that trips the ring detector canbe programmed with the RT bit (N/A for Si3007/8).When cleared, the voltage threshold is in the range from13.5 to 16.5 Vrms. When set, the threshold voltage isincreased from 19.35 to 23.65 Vrms. The three detectionmethods are discussed in detail in the followingsections.

2.1. RGDT Pin Method (Si3050/56 only)The RDGT pin can be monitored for activity on theRNG1 and RNG2 pins. In Half-Wave Detection mode(RFWE = 0), every time the voltage on these pinscrosses the positive threshold, the RGDT pin will beasserted. In Full-Wave Detection mode (RFWE = 1), avoltage above the positive or below the negativethreshold will cause the RGDT pin to be asserted. Inthis case, the frequency on the pin is twice thefrequency of the actual ringing waveform.

The RGDT pin is an open-drain output, and the polarity ofthis pin can be changed by setting the RPOL bit (Register14, bit 1). It requires a 4.7 k pullup or pulldown forproper operation. If multiple devices are used, the RGDTpins can be connected to a single input with thecombined pullup or pulldown resistance equal to 4.7 k.

2.2. Ring Detect Bits MethodThe second method of ring detection uses the RDT,RDTP, and RDTN bits. RDTP is set whenever thevoltage at the line side device exceeds the positivethreshold, and the RDTN bit is set when the voltageexceeds the negative threshold. When the signal at thedevice is between the thresholds, neither bit is set.

The RDT behavior is also based on the voltage. Whenthe RFWE bit is 0, a positive ring signal sets the RDT bitfor a set period of time. When the RFWE bit is 1, apositive or negative ring signal sets the RDT bit.

The RDT bit acts as a one-shot pulse. When a new ringsignal is detected, the one shot is reset. If no new ringsignals are detected prior to the one-shot counterreaching 0, the RDT bit clears. The length of this countis five seconds. The RDT bit is also reset to 0 by an off-hook event.

When the RDTM bit is set, a hardware interrupt occurson the interrupt pin when RDT is triggered. Thisinterrupt can be cleared by writing the RDTI bit to 0. Thefunction of the interrupt pin is slightly different if RingValidation mode is enabled as described in the RingValidation section.

2.3. Serial Data Out MethodThe third method of ring detection uses the datacommunication interface to transmit ring data. If theisolation capacitor link is active (PDL = 0) and thedevice is in the on-hook state, the ring data is presentedon the Serial Data Out Pin. The waveform on this pindepends on the state of the RFWE bit and whether theDAA is in On-Hook Monitor mode.

When RFWE is 0, the serial data is –32768 (0x8000)while the voltage at the device is between thethresholds. When a ring is detected, the data transitionsto +32767 when the ring signal is positive and then goesback to –32768 when the ring is near 0 and negative.Thus, a near square wave is presented by the SDO datathat swings from –32768 to +32767 in cadence with thering signal.

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2 Rev. 0.2

When RFWE is 1, the serial data pin sits at approximately+1228 while the voltage at the device is between thethresholds. When the ring becomes positive, the SDOdata transitions to +32767. When the ring signal goesnear 0, the SDO data remains near 1228. As the ringbecomes negative, the SDO data transitions to –32768.This repeats in cadence with the ring signal.

A simple method to see the ring signal on the serial datapin is to observe the MSB of the data. The MSB togglesat the same frequency as the ring signal independent ofthe Ring Detector mode. This is adequate informationfor determining the ring frequency.

When using the Si3052 system side device, the data ispresented in a parallel format on the PCI bus, but thewaveform data is the same as described above.

3. Hardware Ring ValidationRinging signals are validated using a state machine witha series of bits to specify valid frequencies andcadences. These bits can be used to distinguishbetween actual ring signals and false ring trips and todetect and distinguish between distinctive ringingsignals. They also eliminate software algorithmsrequired to qualify ringing signals in previous generationproducts. The state machine is shown in Figure 1. Thefollowing is a summary of the relevant bits:

RNGV—Ring Validation EnableEnables/Disables hardware ring validation.

RAS[5:0]—Ring Assertion TimeSets minimum valid ring frequency.

RMX[5:0]—Ring Assertion Maximum CountSets maximum valid ring frequency in conjunction with RAS.

RCC[2:0]—Ring Confirmation CountSets minimum valid cadence on-time.

RTO[3:0]—Ring TimeoutSets minimum valid cadence off-time.

RDLY[2:0]—Ring DelaySets delay from valid ring frequency to interrupt generation. Can be used to avoid going off-hook during power cross tests.

RDT—Ring DetectIndicates ring is occurring.

RDTI—Ring Detect InterruptIndicates valid ring had occurred.

RDTM—Ring Detect MaskUsed to mask RDTI to AOUT/INT pin.

RDI—Ring Detect Interrupt ModeControls whether an interrupt occurs at the beginning only or the beginning and the end of a ring burst.

By programming these bits to proper values as shown inthe following sections, the programmer can accuratelydistinguish between valid and invalid ringing signals.

3.1. RNGV—Ring Validation Enable (R24[7])When set, this bit enables the usage of the built-inhardware validation feature. When cleared, this featureis disabled and ring detection must be performed usingone of the previously-mentioned methods.

3.2. RAS—Ring Assertion Time (R24[5:0])At the first positive detect of any signal, a counterpreviously loaded with the value in the RAS bits beginsto count down at a constant rate. As it counts down, thestate machine checks for additional positive detects. Ifno additional positive detects occur during a perioddefined by a counter loaded with the value of the RASbits, a polarity reversal has occurred and the statemachine outputs a line reversal and resets itself. Ifadditional positive detects are present and the RAScounter has not expired, the frequency of the signal ishigh enough and may be considered valid.

The actual value loaded into the RAS bits is in binarycoded increments of 2 ms. The value is calculated usingthe following formula:

RAS[5:0] = 1/(2 x fmin x 2 ms)

where fmin is the lower limit of the valid ring frequencyrange. Fmin is multiplied by 2 because there are twodetects per cycle of the ringing signal. Also, the 2 msfactor is used because of the coding mentioned above.The default value of RAS is 11001b, which translates toan fmin of 10 Hz.

3.3. RMX—Ring Assertion Maximum Count (R22[5:0])

At the negative detect of the ringing signal, the value inthe RAS counter is compared to the value of the RMXbits to determine if the signal frequency is in or out ofthe valid frequency range. If the RAS timer value is lessthan or equal to the RMX value, the frequency is valid;otherwise, it is too high.

The value loaded into the RMX bits is also in binarycoded increments of 2 ms and is calculated using thefollowing formula:

RMX[5:0] = RAS[5:0] - 1/(2 x fmax x 2 ms)

where fmax is the upper limit of the valid ring frequencyrange. The default value is 10110b, which translates toan fmax of 83.3 Hz. A timing diagram for both RAS andRMX is shown in Figure 2.

When using the Si3007 or Si3008 lineside device, theRMX value should be loaded with a value 1 less thanRAS to ensure proper ring detection for ringing signalswith low DC battery feeds.

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Figure 1. Si3050/52/54 Ring Validation State Diagram

SLEEPcount1 <— ring_timeoutcount2 <— inversion_assertoutput line_reversal = FALSEoutput valid_ring = FALSE

CHECK_REVERSALdecrement count1decrement count2 on line_activity

ASSERT_REVERSAL

output line_reversal = TRUEcount2 <— distinctive_ring_conf

count1 <— ring_assert

TRIGGER

decrement count1decrement count2

Reject short events, transients,out-of-band signals

count2 <— ring_conf

count1 <— ring_timeout

SCREEN

decrement count1decrement count2

Filter out multiple triggers fromdistinctive ringing cadences

count2 <— ring_conf

count1 <— ring_timeout

ENDRING

decrement count1output valid_ring = TRUE

Find end of a valid ringing signaltimeout1

timeout1

(high frequency detect)

line_activity & (count1 > rmax)

timeout1 (low frequency detect)

line_activity & ring validation enabled

timeout2

line_activity &(count1 <= rmax)

line_activity

line_activity & timeout2

timeout2

line_activity

State-Machine OperationState machine is evaluated at16 kHz intervals

State-Machine Inputsline_activity : Tip/Ring voltagecrosses ring voltage thresholdtimeout1 : count1 = = 0timeout2 : count2 = = 0

ring_timeout = RTO[3:0]x2048inversion_assert = IASdistinctive_ring_conf = f(RCC[2:0])ring_assert = RAS[5:0]x32rmax = RMX[5:0]x32ring_conf = RDLY[2:0]x4096

State-Machine Outputsline_reversal 1: = battery reversal detectedvalid_ring 1: = ring signal validated

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4 Rev. 0.2

Figure 2. Ring Validation Frequency Example

Figure 3. Ring Validation—RCC[2:0] Bits

Figure 4. Ring Validation—RTO[3:0] Bits

RMX

Value

RAS Timer

Valid

Region

RMX

Value

RMX

Value

Low f

Region

High f

Region

RING FREQUENCY TOO LOW RING FREQUENCY IN RANGE RING FREQUENCY TOO HIGH

1024 ms

On - time

RCC = 640 ms

On-time > RCC Valid

RCC = 640 ms

384 ms

On - time

On-time < RCC Invalid

1024 ms

On - time

512 ms

Off - timeDetect

Off-time < RTO No 2nd Detect

1024 ms

On - time1024 ms

Off - time

Detect

Off-time > RTO 2nd Detect

2nd Detect

RTO RTO

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Rev. 0.2 5

Figure 5. Ring Validation—RDLY[2:0] Bits

3.4. RCC—Ring Confirmation Count (R23[2:0])

The value of the RCC bits is loaded into another counterthat begins counting down after the signal frequencyhas been validated by RAS and RMX. If the frequencyfalls out of the valid range any time before the counterexpires, then the ring is not valid. If the frequency staysin range until the counter expires, then the ring signalmeets the on-time requirement. The range of the RCCbits is 100 to 1024 ms, and the default value is 512 ms.The function of RCC is summarized in Figure 3.

3.5. RTO—Ring Timeout (R23[6:3])After the ring signal has been present for a durationequal to RCC, the state machine stops looking atfrequency and starts looking for the end of the ringburst. The state machine determines the end of a ringburst by starting a timer that is previously loaded withthe value encoded in RTO. This timer is reset whenevera detection occurs. If the timer expires, the ring burst isconsidered to have ended. In addition, the statemachine is reset at this time. These bits can be used todetect and distinguish between distinctive ringingsignals. The default value for RTO is 640 ms, and therange is from 128 to 1920 ms. Figure 4 shows thefunction of RTO.

3.6. RDLY—Ring Delay (R23[7], R22[7:6])The RDLY bits are used to delay the interrupt fromoccurring a certain amount of time from when thefrequency and on-time has been validated. This isaccomplished using a countdown timer. To get aninterrupt, the RDLY timer must expire before the RTO

timer expires because the latter causes the statemachine to be reset.

RDLY can be used to keep the DAA from going off-hookduring 50/60 Hz power cross tests, which could bedetected as a valid ring. The RDLY default value is512 ms, and the range is from 0 to 1792 ms. A timingdiagram for RDLY is shown in Figure 5.

4. Interrupt Generation in Ring Validation Mode

With Ring Validation enabled, the output of the statemachine controls when an interrupt is generated andthe RDTI bit is set. The RDTI bit follows the rising edgeof the RDT bit. The RDT bit still acts like a one shot, butthe RDTI bit can be cleared during the ring signal.

In Ring Validation mode, the state machine controls theRDT bit instead of RDT being a one-shot pulse with a5 second width.

If an interrupt is needed at the beginning and the end ofthe ring burst, the RDI bit should be set. This bit allowsan interrupt to occur on the rising and falling edge of thering burst. To see both interrupts, the RDTI bit must becleared before the end of the burst. The beginninginterrupt is triggered by the rising edge of the RDT bit,and the ending interrupt is triggered by RDT falling,which occurs when the RTO counter expires in the ringvalidation state machine.

RDLY = 128 ms

RCC = 512 ms

1024 ms

Detect

RDLY = 768 ms

RTO = 256 ms

384 ms

On-time

No Detect—RDLY never reaches 0

On-time

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6 Rev. 0.2

DOCUMENT CHANGE LIST

Revision 0.1 to Revision 0.2 Updated to include Si3007/8 line side ring validation

considerations.

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