Design of Analog CMOS Circuits Using Gm/ID–Based Methods

EEE 523 - Advanced Analog Integrated CircuitsErik Mentze 01.27.12

References1. F. Silveria et al. “A gm/Id based methodology for the design of CMOS analog circuits and its

application to the synthesis of a silicon-on-insulator micropower OTA,” IEEE Journal of Solid-State Circuits, Sep. 1996, pp 1314-1319.

2. D. Foty, M. Bucher, D. Binkley, “Re-interpreting the MOS transistor via the inversion coefficient and the continuum of gms/Id,” Proc. Int. Conf. on Electronics, Circuits and Systems, pp. 1179-1182, Sep 2002.

3. B.E. Boser, “Analog Circuit Design with Submicron Transistors,” IEEE SSCS Meeting, Santa Clara Valley, May 19, 2005, http://www.ewh.ieee.org/r6/scv/ssc/May1905.pdf.

4. H.D. Dammak, et al. “Design of Folded Cascoe OTA in Different Regions of Operation through gm/ID Methodology,” World Academy of Science, Engineering, and Technology, 45, 2008.

5. P. Jespers, The gm/Id Methodology, a sizing tool for low-voltage analog CMOS Circuits, Springer, 2010.

6. T. Konishi, et al, “Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using gm/ID Lookup Table Methodology,” IEICE Trans. Electron., Vol.E94-C, NO.3 March 2011.

7. B. Murmann, “MOS Transistor Modeling Gm/ID-based Design,” EE214 Course Reader, Stanford University, Stanford CA, 2011.

The Model Problem

Nothing Reality

SPICE“Square Law”

EKVGm/ID

Square Law Equations

𝐼𝐷=12

𝜇𝐶𝑜𝑥𝑊𝐿 (𝑉 𝐺𝑆−𝑉 𝑡 )2 [1+λ (𝑉 𝐷𝑆−𝑉 𝐷𝑆(𝑠𝑎𝑡 ))]

𝐼𝐷=𝜇𝐶𝑜𝑥𝑊𝐿 [ (𝑉 𝐺𝑆−𝑉 𝑡 )𝑉 𝐷𝑆−

𝑉 𝐷𝑆❑ 2

2 ]

𝑉 𝐺𝑆≥𝑉 𝑇𝐻 𝑉 𝐷𝑆 ≥𝑉 𝐺𝑆−𝑉 𝑇𝐻Saturation

𝑉 𝐺𝑆≥𝑉 𝑇𝐻 𝑉 𝐷𝑆 ≤𝑉 𝐺𝑆−𝑉 𝑇𝐻Triode

process “constants”

operating point informationdesign term

process “constant”

design term operating point information

uCox (“KP”) Simulation

Dependence on: overdrive voltage, gate length, etc.

SPICE Model

Found One!

Process constants handled by curve fittingBSIM 3v3 uses 110 parameters!

The Model Problem

Nothing Reality

SPICE“Square Law”

EKVgm/ID

Square Law Model:Useful for hand calculationsOversimplifies process constants20%-80% Error

SPICE Model:Useful for computer simulationCurve Fitting for process constantsExcellent accuracy (if done properly)

The purpose of any model: To give you the right answer!

Gm/ID Model:Useful for hand calculations<10% ErrorTwo approaches to process constants…

Handling Process Constants

• Analytical– Takes device physics into account, typically using the EKV

model– Derived expressions from physical device parameters

• Experimental– Lookup table approach, storing device characteristics

generated by SPICE simulation or measurement results– “The gm/ID lookup table methodology enables an analytical

design optimization by overwhelming the inaccuracy observed in the square-law MOS transistor model”

gm/ID-Based Design

Set of normalized figures of merit to describe FET transistors

– Transconductance Efficiency• FET Operating Point• Want large gm for as little current as possible

– Current Density• How wide does the device need to be?

– Transit Frequency• Want large gm, with as little Cgg as possible

– Intrinsic Gain• Want large gm, with large ro (small go)

𝑔𝑚

𝐼𝐷

𝑔𝑚

𝐶𝑔𝑔

(𝑔𝑚

𝑔𝑜)𝑔𝑚𝑟 𝑜

𝐼𝐷

𝑊

What is gm/ID?• A way of representing the FET operating point

– Overdrive voltage () is only valid in strong inversion

– can represent an equivalent bias condition for strong, moderate, and weak inversion, with smooth transitions between each.

• A design parameter that couples small signal transconductance and large signal bias current.– How much bias current do I need to achieve a required amount of

transconductance?

• A measure of efficiency to generate gm from a given ID

– Large gm/ID value implies larger transconductance for a constant current

• Similar to normalized BJT transconductance:

Extracting Device Characteristics1. Vds set to ½ Vpwr

2. Sweep Vgs: 0 to Vpwr

3. Measure required parameters:- gm, Id, ro, Cgg

4. Repeat for various lengths (fixed W)

Notes:• To a first order, the measurement is independent of Vds• Body effects are neglected• and thus measurements are independent of W

Strong Inversion

Weak Inversion“subthreshold”

Moderate Inversion

Favors DC Gain Favors BW

𝑔𝑚

𝐼𝐷

∝ 𝑊𝑊

𝐼𝐷

𝑊∝ 𝑊

𝑊

Strong Inversion Weak Inversion

𝑔𝑚𝑟 𝑜=𝑔𝑚

𝑔𝑜

Strong Inversion Weak Inversion

𝑓 𝑡=12𝜋

∙𝑔𝑚

𝐶𝑔𝑔

Lookup Table Functions

• Can I avoid using a ruler on a printed out chart? – YES! By using a scripting language such as MATLAB, Python,

etc…• Based on extracted data from SPICE simulations:

– lookup.ft(fet, length, gm/id)– lookup.gmro(fet, length, gm/id)– lookup.idw(fet, length, gm/id)– lookup.gmid(fet, length, fom, fom_value)– lookup.length(fet, gmid, fom, fom_value)

• Useful for:– Quick lookup while doing hand calculations– Design optimization scripts

Comparison to Square Law Equations

𝑔𝑚

𝐼𝐷

=𝜇 𝐶𝑜𝑥

𝑊𝐿 (𝑉 𝐺𝑆−𝑉 𝑡 )

12

𝜇 𝐶𝑜𝑥𝑊𝐿

(𝑉 𝐺𝑆−𝑉 𝑡 )2=2

𝑉 𝑜𝑣

𝑔𝑚

𝐶𝑔𝑔

=𝜇𝐶𝑜𝑥

𝑊𝐿 (𝑉 𝐺𝑆−𝑉 𝑡 )

23

𝐶𝑜𝑥 ∙𝑊 ∙𝐿=32∙𝜇𝑉 𝑜𝑣

𝐿2

𝑔𝑚𝑟 𝑜=𝜇𝐶𝑜𝑥𝑊𝐿 (𝑉 𝐺𝑆−𝑉 𝑡 ) ∙ 1

λ ∙12

𝜇 𝐶𝑜𝑥𝑊𝐿

(𝑉 𝐺𝑆−𝑉 𝑡 )2=

2λ𝑉 𝑜𝑣

𝑉 𝑜𝑣=2𝑔𝑚

𝐼𝐷

Comparison to Square Law Equations

Square law equations breakdown at Vov ~200mV

𝑔𝑚

𝐼𝐷

= 2𝑉 𝑜𝑣

Comparison to Square Law Equations

Good estimate of “Vdsat”: voltage required to extract gain

Gm/ID-Based Design

• Replaces a set of equations to solve with a set of figures of merit to balance

• Complex process parameters are “overwhelmed” with lookup charts (or lookup table functions)

• Accurately models operation over weak, moderate, and strong inversion

• Avoids over-dependence on SPICE simulations

Sample Design Flow

1. From a given specification, determine the required gm

2. Choose a bias current based on required gm and desired gm/ID operating point.

3. Lookup transistor “W” from gm/ID vs. ID/W chart. (L is typically chosen based on technology or gain requirements)

Simple ExampleSpecs and Objectives:

tsmc18 process (3V)RL=1kΩ, CL=50fF, Ri=10kΩ

DC Gain = -4 v/vEstimate pole locations

Simple Design Flow

1. From the given specification, determine the required gm

2. Choose a bias current based on required gm and desired gm/ID operating point.

3. Lookup transistor “W” from gm/ID vs. ID/W chart. (L is typically chosen based on technology and over gain requirements)

Small Signal Model

  

Simple Design Flow

1. From the given specification, determine the required gm

2. Choose a bias current based on required gm and desired gm/ID operating point.

3. Lookup transistor “W” from gm/ID vs. ID/W chart. (L is typically chosen based on technology and over gain requirements)

Small Signal Model

𝑔𝑚

𝐼𝐷

=10 𝐼𝐷=4𝑚𝑆10

=0.4𝑚𝐴

Simple Design Flow

1. From the given specification, determine the required gm

2. Choose a bias current based on required gm and desired gm/ID operating point.

3. Lookup transistor “W” from gm/ID vs. ID/W chart. (L is typically chosen based on technology and over gain requirements)

Id/W=7.33

Simple Example

Test Circuit

𝐼𝐷

𝑊=7.33 𝑊=

𝐼𝐷

7.33=400𝜇 𝐴

7.33=54.57𝜇𝑚

𝐿=350𝑛𝑚

Simulation ResultsParameter Hand

CalcSim % error

Av(DC) 4.0 V/V 3.953 V/V 1%

gm 4 mS 4.089 mS 2.2%

gm/ID 10.0 S/A 10.15 S/A 1.5%

Simple Example – Estimate BW

 

|𝐴𝑉 ( 𝑠)|≅ 𝑔𝑚 𝑅𝐿 ∙(1+ 𝑠

𝜔𝑧)

(1+ 𝑠𝜔𝑝

)𝐶𝑔𝑔≡𝐶𝑔𝑠+𝐶𝑔 𝑏+𝐶𝑔 𝑑

𝐶𝑑𝑑≡𝐶𝑑𝑏+𝐶𝑔𝑑

𝐶𝑔𝑔=12𝜋

∙𝑔𝑚

𝑓 𝑡𝜔𝑝≅1

𝑅 𝑖 [ 𝐶𝑔𝑔+𝑔𝑚 𝑅𝐿 ∙𝐶𝑔𝑑 ]𝐶𝑔𝑑=?

Normalized Capacitance

Factors for approximating:

𝐶𝑔𝑑=(𝐶𝑔𝑑

𝐶𝑔𝑔) ∙𝐶𝑔𝑔

𝐶𝑑𝑑=(𝐶𝑑𝑑

𝐶𝑔𝑔)∙𝐶𝑔𝑔

Simple Example – Estimate BW

 

|𝐴𝑉 ( 𝑠)|≅ 𝑔𝑚 𝑅𝐿 ∙(1+ 𝑠

𝜔𝑧)

(1+ 𝑠𝜔𝑝

)𝐶𝑔𝑔≡𝐶𝑔𝑠+𝐶𝑔 𝑏+𝐶𝑔 𝑑

𝐶𝑑𝑑≡𝐶𝑑𝑏+𝐶𝑔𝑑

𝐶𝑔𝑔=12𝜋

∙𝑔𝑚

𝑓 𝑡𝜔𝑝≅1

𝑅 𝑖 [ 𝐶𝑔𝑔+𝑔𝑚 𝑅𝐿 ∙𝐶𝑔𝑑 ]𝐶𝑔𝑑=(𝐶𝑔𝑑

𝐶𝑔𝑔) ∙𝐶𝑔𝑔

ft = 7.01GHz

Simple Example – Estimate BW

|𝐴𝑉 ( 𝑠)|≅ 𝑔𝑚 𝑅𝐿 ∙(1+ 𝑠

𝜔𝑧)

(1+ 𝑠𝜔𝑝

)𝐶𝑔𝑔≡𝐶𝑔𝑠+𝐶𝑔 𝑏+𝐶𝑔 𝑑

𝐶𝑑𝑑≡𝐶𝑑𝑏+𝐶𝑔𝑑

𝐶𝑔𝑔=12𝜋

∙𝑔𝑚

𝑓 𝑡

=90.8 𝑓𝐹𝜔𝑝≅

1𝑅 𝑖 [ 𝐶𝑔𝑔+𝑔𝑚 𝑅𝐿 ∙𝐶𝑔𝑑 ]

=656.17𝑀𝑟𝑎𝑑

𝑠𝐶𝑔𝑑=(𝐶𝑔𝑑

𝐶𝑔𝑔) ∙𝐶𝑔𝑔=0.17 ∙90.8=15.4 𝑓𝐹¿104.4𝑀𝐻𝑧

𝜔 𝑧=𝑔𝑚

𝐶𝑔𝑑

=260 𝑀𝑟𝑎𝑑𝑠

=41.3𝐺𝐻𝑧

Simulation Results

Summary of Normalized Design Parameters

𝑔𝑚

𝐼𝐷

𝑔𝑚

𝐶𝑔𝑔

(𝑔𝑚

𝑔𝑜)𝑔𝑚𝑟 𝑜

𝐼𝐷

𝑊

𝐶𝑔𝑑

𝐶𝑔𝑔

𝐶𝑑𝑠

𝐶𝑔𝑔

Primary Design Parameters

Secondary Design Parameters

Gm/ID-Based Design

• Replaces a set of equations to solve with a set of figures of merit to balance

• Complex process parameters are “overwhelmed” with lookup charts (or lookup table functions)

• Accurately models operation over weak, moderate, and strong inversion

• Avoids over-dependence on SPICE simulations

OTA Simulation / Optimization

M1 M2

M3 M4M41M31

M5M51

VpVm

CL

𝐴𝑉=𝐾 ∙𝑔𝑚 ∙ (𝑟𝑜 4∨¿𝑟𝑜5 )1 : K

1 : K

𝑔𝑚(𝑒𝑓𝑓 )=𝐾 ∙𝑔𝑚

𝑓 𝑢𝑛=𝑔𝑚(𝑒𝑓𝑓 )

2𝜋 𝐶𝐿

𝑓 3𝑑𝐵=1

2𝜋 (𝑟 𝑜4∨¿𝑟𝑜5 )𝐶𝐿

Design Choices:K and gm set DC gainK and gm set unity gain frequency

So which should I use? K or gm? Why not try both…

gm/ID simulation results

gm/IDtail current (mA)

total current (mA)

Cload = 5pFfun = 10MHzAV(DC) = 1000 V/V

Limitations

• Lookup tables extracted from SPICE simulations– Only as accurate as the SPICE curve fitting

• Process and temperature corner cases

• Body Effects– Cascode architecture

• Drain-Source voltage variation

Appendix

• Simple Current Mirror• Cascode Current Mirror

Current Mirror Design Example

Design goals:1. Good DC current matching

• small gm/ID (strong inv)

2. Reasonable headroom

• large gm/ID (weak inv)

3. High Output Resistance• small gm/ID (strong inv)

Design Option 1: gm/ID = 5

𝑔𝑚

𝐼𝐷

=5 lookup 𝐼𝐷

𝑊=10.8 𝑊=

𝐼𝐷

10.8=25𝜇 𝐴10.8

=2.3𝜇𝑚

𝐿=1𝜇𝑚choose

𝑉 𝑑(𝑠𝑎𝑡 )≅2

𝑔𝑚

𝐼𝐷

=0.4𝑉

𝑔𝑚𝑟 𝑜=328

𝑟𝑜≅ 2.6𝑀Ω

𝑔𝑚≅ 125𝜇𝑆

Design Option 2: gm/ID = 10

𝑔𝑚

𝐼𝐷

=10 lookup 𝐼𝐷

𝑊=1.98 𝑊=

𝐼𝐷

1.98=25𝜇 𝐴1.98

=12.5𝜇𝑚

𝐿=1𝜇𝑚choose

𝑉 𝑑(𝑠𝑎𝑡 )≅2

𝑔𝑚

𝐼𝐷

=0.2𝑉

𝑔𝑚𝑟 𝑜=413

𝑟𝑜=1.65𝑀 Ω

𝑔𝑚≅ 250𝜇 𝑆

Cascode Current Mirror Example

matching

gmro

𝑅𝑜≅ 𝑔𝑚1𝑟𝑜1𝑟 𝑜2

Optimize separately• High gm/Id for gain• Low gm/Id for matching

Design Cascode Current Source𝑔𝑚

𝐼𝐷

=5 lookup 𝐼𝐷

𝑊=10.8 𝑊=

𝐼𝐷

10.8=25𝜇 𝐴10.8

=2.3𝜇𝑚

𝐿=1𝜇𝑚choose

𝑉 𝑐𝑜𝑚𝑝≅ 0.2+0.4=0.6𝑉

𝑔𝑚2𝑟 𝑜2=413

𝑟𝑜1≅ 2.6𝑀 Ω

𝑅𝑜≅ 1𝑇 Ω

𝑔𝑚

𝐼𝐷

=10 lookup 𝐼𝐷

𝑊=1.98 𝑊=

𝐼𝐷

1.98=25𝜇 𝐴1.98

=12.5𝜇𝑚

1.2% 𝑒𝑟𝑟𝑜𝑟 𝑎𝑡 𝑉 𝑑𝑠=0.6𝑉