ananth shetty k r

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ANANTH SHETTY K [email protected]

8105010222Bengaluru

Karnataka-560054Career Objective

To work in a environment where I can use my knowledge and experience in the field of VLSIfor the betterment of myself and the organization I work for.

Core Competancy

Good understanding of full custom IC design flow, MOS theory.Good understanding of IC fabrication process/semiconductor manufacturing.Worked on technology nodes like 180nm, 90nm and 28nm.Good understanding of short channel effects.Worked on IC studio simulator from Mentor Graphics, Pyxis Editor and Calibre Verificationtool.Experienced different types of DRC and LVS errors such as shorts, opens, property errors,device mismatch, soft-check.Good understanding of Analog Layout Techniques such as Common - Centroid, Inter-digitizedfingers and symmetry.Good understanding of DFM issues such as Latch-Up, Antenna Effects, OPC, Electro Migrationand CMP.Basic working knowledge of Linux.Basic understanding of layout proximity effects such as WPE and LOD.

Education DetailsPG Diploma in Advanced Diploma in ASIC Design - Full Custom 2016 RV-VLSI Design CenterMaster Degree in Industrial Electronics 2015 SJCE, Mysore, with 8.48 CGPABachelor Degree in Electronics and Communication 2012 KLEIT, Hubli, with 70.1 %PUC / 12th 2008 Fatima Composite PU College, with 78 %SSLC 2006 Saint Andrew's English Medium High School, with 82.24 %



Domain Specific ProjectRV-VLSI Design CenterStandard Cell Layout Design Engineer May-2016 to Jun-20169-T Standard Cell Library Design in 90nm ProcessDescription

Designing the library which consists of cells with varied drive strengths. Layouts drawn shouldmeet DRC, compatibility and LVS rules respectively. Making the layout more effective by wellsharing, diffusion sharing in order to reduce parasitics.

Tools

ICstudio from Mentor Graphics - 1. Pyxis (Schematic and Layout Editor) 2. Calibre (DRC, LVSCheck)

Challenges

Fitting the layout within the given PR-Boundary and maintaining DRC rules.Analyzing LVS errors such as nets and instances.Layout optimization techniques for better floor planning by means of diffusion sharing.To reduce parasitics by avoiding poly routing and routing using only M1 layer was difficult.

RV-VLSI Design CenterAnalog Layout Engineer Jun-2016 to Jun-2016Two Stage Op-amp Layout Design in 180nm ProcessDescription

Designing layout of 2 stage op-amp with different floor plans by using various device matchingtechniques and implementing one of them. Sitting of guard rings around active transistors toavoid latch up. Layout should be DRC and LVS free.

Tools

IC studio from Mentor Graphics - 1. Pyxis: Schematic and Layout Editor 2. Calibre : DRC, LVSCheck

Challenges

Effective floor planning using device matching techniques for sensitive transistor pair.Placement of dummy transistors for minimum mismatch and providing guard ring forprotection.To reduce parasitics by avoiding poly routing, by adding more number of contacts in thediffusion and by fingering.Maintaining the optimum metal spacing to avoid cross talk.



RV-VLSI Design CenterStandard Cell Layout Design Engineer Jun-2016 to Jul-2016Design of Standard Cells for SRAM in 28nm ProcessDescription

Designing Leaf Cells for combinational circuits : INVERTER: INVx1, INVx2. NAND: NAND2x1,NAND2x2, NAND2x4. NOR: NOR3x1, NOR3x2, NOR3x4. AND: AND2x1, AND3x1. OR: OR3x1,OR3x2, OR3x4 and performing verification process of leaf cells by DRC, LVS Check

Tools

ICstudio from Mentor Graphics - 1. Pyxis : Schematic and Layout Editor 2. Calibre: DRC, LVSCheck

Challenges

Placing contacts and poly’s on grid.Reducing the parasitics by making use of metal routing and avoiding poly routing.Fitting the layout within the given PR-Boundary by considering compatibility rules.Making the layout as optimized as possible by drain sharing, transistor fingering.

RV-VLSI Design CenterAnalog Layout Engineer Jul-2016 to Aug-2016Leaf Cells Design of 6-T SRAM in 28nm ProcessDescription

Layout design of Pre-charge block with MUX factor 4, Sense amplifier block using devicematching techniques, and other blocks such as D-in block, D-out block, Decoder block, ControlBlock and Scan block by maintaining proper design constraints

Tools

ICstudio from Mentor Graphics - 1. Pyxis: Schematic and Layout Editor 2. Calibre: DRC, LVSCheck.

Challenges

Designing the floor plan of the whole layout within given area.Placement of poly and contact on grids.Placement of pins for easy abutting with neighboring blocks.To meet the layout constraints.



B.E / B.Tech Academic ProjectKLEIT, HubliBlind Navigation and Safety with GSM ModemDescription

1. Gas leakage sensing 2. Fire Sensing 3. Door Break Detection 4. Obstacle Detection and 5.Outdoor navigation system for blind pedestrians.

Tools

ST-TX01 ASK Tx Module, ST-RX01 ASK Rx Module, HT12E Encoder, HT12D Decoder, MAX232, APR9600 Voice Processor, GSM Modem. Keil uVision 3.2, Embedded C.

Challenges

1. Maintaining the proper range of distance to receive signals 2. Maintaining the proper delaybetween the message segments so that the message is received quickly and appropriately

M.E / M.Tech Academic ProjectSJCE, MysoreA Robust Algorithm for Text Detection in Complex Background ImagesDescription

1. Detects text of varying sizes, different background, different languages and orientation 2.To perform Edge Box filtering to filter out the non-text regions 3. To binarize the image byemploying connected component analysis

Tools

MATLAB - Version 8.5 and Release R2015a

Challenges

1. Detecting the text which is partially occluded 2. Detecting the text where text componentsare stuck together 3. Detecting the text with varying illumination 4. Detecting the text whenthe background of the image is textured

ananth shetty k r

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