and optimization for digital systems
TRANSCRIPT
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ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
Lec 12: October 2, 2020Scaling
Penn ESE 370 Fall 2020 - Khanna
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Today
! Layout Roundup" Standard cells
! VLSI Scaling Trends/Disciplines! Effects! Alternatives (cheating)
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Standard Cells
! Lay out gates so that heights match" Rows of adjacent cells" Standardized sizing of gate heights
! Motivation: automated place and route" EDA tools convert HDL to layout
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Standard Cells
Penn ESE 370 Fall 2020 - Khanna 4
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Standard Cell Layout Example
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Standard Cell Area
invnand3All cellsuniformheight
Width ofchannel
determinedby routing
Cell area
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Standard Cell Layout Example
http://www.laytools.com/images/StandardCells.jpgPenn ESE 370 Fall 2020 - Khanna 7
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4x4 6T SRAM Memory
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Circuit Extraction
! Circuit extraction extracts a schematic representation of a layout, including transistors, wires, and possibly wire and device resistance and capacitance.
! Circuit extraction is used for LVS, and for spice simulation of layouts
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Circuit Extraction
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Circuit Extraction
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Scaling
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Standard Cells
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Scaling Technology
! Premise: features scale “uniformly”" everything gets better in a predictable manner
! Parameters:# l (lambda) -- Mead and Conway (L=2l)# F -- Half pitch – ITRS (F=2l=L)# S – scale factor – Rabaey
# F’=F/S# S>1
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(TypicalDRAM)
Metal Pitch
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Microprocessor Trans Count 1971-2015
15Kenneth R. Laker, University of Pennsylvania, updated 20Jan15
Curve shows transistor count doubling every
two yearsPentium
40048006
8080Mot 6800
8086
Mot 6800080286
80386
80486
MOS 6502Zilog Z80
80186
AMD K5Pentium II
Pentium IIIAMD K7
Pentium 4AMD K8
AMD K10 AMD 6-Core Opteron 24004-Core i7
2-Core Itanium 26-Core i76-Core i716-Core SPARC T3
10-Core Xenon IBM 4-Core z196IBM 8-Core POWER7
4-Core Itanium Tukwilla
2015: Oracle SPARC M7, 20 nm CMOS,32-Core, 10B 3-D FinFET transistors.
2015Penn ESE 370 Fall 2020 - Khanna
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Intel Cost Scaling
16
http://www.anandtech.com/show/8367/intels-14nm-technology-in-detail
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More Moore $ Scaling
! Geometrical Scaling" continued shrinking of horizontal and vertical physical
feature sizes
! Design Equivalent Scaling" design technologies that enable high performance, low
power, high reliability, low cost, and high design productivity even if neither geometrical nor equivalent scaling can be used
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22nm 3D FinFET Transistor
18
Tri-Gate transistors with multiple fins connected together
increases total drive strength for higher performance
http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-Details_Presentation.pdf
High-k gate
dielectric
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ITRS Roadmap
! International Technology Roadmap for Semiconductors" Try to predict where industry going
! ITRS 2.0 started in 2015 with new focus" System Integration, Heterogeneous Integration,
Heterogeneous Components, Outside System Connectiviy, More Moore, Beyond CMOS and Factory Integartion.
! http://www.itrs2.net/
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More-than-Moore
20
“More-than-Moore”, International Road Map (IRC) White Paper, 2011.
International Technology Road Map for Semiconductors
Scaling
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Preclass 1
! Scaling from 32nm $ 22nm, what is 1/S?" Scaling minimum gate length" And pitch distance
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MOS Transistor Scaling - (1974 to present)
1/S=0.7 per technology node
[0.5x per 2 nodes]
Pitch Gate
Source: 2001 ITRS - Exec. Summary, ORTC Figure, Andrew KahngPenn ESE 370 Fall 2020 - Khanna 22
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Scaling
! Channel Length (L)! Channel Width (W)! Oxide Thickness (tox) ! Doping (Na)! Voltage (VDD,Vt,)
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Full Scaling (Ideal Scaling)
! Channel Length (L) 1/S! Channel Width (W) 1/S! Oxide Thickness (tox) 1/S! Doping (Na) S! Voltage (VDD,Vt,) 1/S
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Effects on Physical Properties and Specs?
! Area! Capacitance
" Cox and Cgate
! Resistance! Current (Id)! Gate Delay (tgd)! Wire Delay (twire)
! Power " Same frequency" Scaled frequency
! Power Density" Same frequency" Scaled frequency
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Preclass 2 - table
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Area
! l’% l/S! Area impact?! A = L ×W! L
W1/S=0.7
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Area
! l’% l/S! Area impact?! A = L ×W! A’% A/S2
! 32nm % 22nm! 50% area! 2 × transistor capacity
for same area
L
W1/S=0.7
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Capacitance
! Capacitance per unit area scaling?
" Cox= eSiO2/tox
" t’ox% tox/S
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Capacitance
! Capacitance per unit area scaling?
" Cox= eSiO2/tox
" t’ox% tox/S" C’ox % Cox×S
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Capacitance
! Gate Capacitance scaling?
# Cgate= A×Cox
# A’% A/S2
# C’ox % Cox×S
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Capacitance
! Gate Capacitance scaling?
# Cgate= A×Cox
# A’% A/S2
# C’ox % Cox×S# C’gate % Cgate/S
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Wire Resistance
! Resistance scaling?! R=rL/(W*t)
" L, t remain similar (not scaled)
! W$ W/S
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Wire Resistance
! Resistance scaling?! R=rL/(W*t)
" L, t remain similar (not scaled)
! W$ W/S! R’ $ R×S
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Current
! Which Voltages matters here? (Vgs,Vds,Vth…)! Transistor charging looks like
voltage-controlled current source! Saturation Current scaling?
Id=(µCOX/2)(W/L)(Vgs-VTH)2
Vgs,VTH: V’$ V/SW’$ W/SL’$ L/SC’ox$ Cox×S
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Current
! Which Voltages matters here? (Vgs,Vds,Vth…)! Transistor charging looks like
voltage-controlled current source! Saturation Current scaling?
Id=(µCOX/2)(W/L)(Vgs-VTH)2
Vgs,VTH: V’$ V/SW’$ W/SL’$ L/SC’ox$ Cox×S
I’d=(µCOXS/2)((W/S)/(L/S))(Vgs/S-VTH/S)2
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Current
! Which Voltages matters here? (Vgs,Vds,Vth…)! Transistor charging looks like
voltage-controlled current source! Saturation Current scaling?
Id=(µCOX/2)(W/L)(Vgs-VTH)2
Vgs,VTH: V’$ V/SW’$ W/SL’$ L/SC’ox$ Cox×S
I’d$Id/SPenn ESE 370 Fall 2020 - Khanna 36
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Current
! Velocity Saturation Current scaling?
Vgs,VTH: V’$ V/SL’$ L/S W’$ W/SC’ox$ CoxS
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Current
! Velocity Saturation Current scaling?
Vgs,VTH: V’$ V/SL’$ L/S W’$ W/SC’ox$ CoxS
I’d$ Id/S
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€
IDS ≈νsatCOXW VGS −VTH −VDSAT
2%
& '
(
) *
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Gate Delay
# Gate Delay scaling?# tgd=Q/I=(CV)/I# V’$ V/S# I’d$ Id/S# Cg’$ Cg/S
Note: Ids modeled as current source; V is changing with scale
factor
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Gate Delay
# Gate Delay scaling?# tgd=Q/I=(CV)/I# V’$ V/S# I’d$ Id/S# Cg’$ Cg/S# t’gd$ tgd/S
Note: Ids modeled as current source; V is changing with scale
factor
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Wire Delay
# Wire delay scaling?# twire=R´C
# R’ $ R×S# C’$ C/S
! Again assuming (logical) wire lengths remain constant
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Wire Delay
# Wire delay scaling?# twire=R´C
# R’ $ R×S# C’$ C/S# t’wire $ twire
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! Again assuming (logical) wire lengths remain constant
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Power Dissipation (Dynamic)
! Capacitive (Dis)charging scaling?! P=(1/2)CV2f
! V’$ V/S! C’$ C/S
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Power Dissipation (Dynamic)
! Capacitive (Dis)charging scaling?! P=(1/2)CV2f
! V’$ V/S! C’$ C/S
! P’$ P/S3
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Power Dissipation (Dynamic)
! Capacitive (Dis)charging scaling?! P=(1/2)CV2f
! V’$ V/S! C’$ C/S
! P’$ P/S3
! Increase Frequency?
! tgd $ tgd/S
! So: f $ f×S
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Power Dissipation (Dynamic)
! Capacitive (Dis)charging scaling?! P=(1/2)CV2f
! V’$ V/S! C’$ C/S
! P’$ P/S3
! Increase Frequency?
! tgd $ tgd/S
! So: f $ f×S
! P $ P/S2
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Effects? (Preclass 2)
! Area 1/S2
! Capacitance (Cox, Cg) S, 1/S! Resistance S! Threshold (Vth) 1/S! Current (Id) 1/S! Gate Delay (tgd) 1/S! Wire Delay (twire) 1! Power 1/S3, 1/S2
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1/S=0.7
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Power Density
! P’ % P/S2 (increased frequency)! P’ % P/S3 (same frequency)! A’ % A/S2
! Power Density: P/A two cases?
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Power Density
! P’ % P/S2 (increased frequency)! P’ % P/S3 (same frequency)! A’ % A/S2
! Power Density: P/A two cases?" P/A % P/A increase freq." P/A % (P/A)/S same freq.
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But…
! Don’t like some of the implications! High resistance wires! Higher gate oxide capacitance! Atomic-scale dimensions
! …. Quantum tunneling
! Need for more wiring! Not scale speed fast enough
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Improving Resistance
! R=rL/(W×t)! W’$ W/S
" L, t similar
! R’ $ R×S
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Improving Resistance
! R=rL/(W×t)! W’$ W/S
" L, t similar
! R’ $ R×S
What might we do?Decrease ρ (copper) – introduced 1997http://www.ibm.com/ibm100/us/en/icons/copperchip/
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Capacitance and Leakage
! Capacitance per unit area" Cox= eSiO2/tox
" t’ox% tox/S" C’ox % Cox×S
What’s wrong with tox = 1.2nm?
source: Borkar/Micro 2004Penn ESE 370 Fall 2020 - Khanna 53
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Capacitance and Leakage
! Capacitance per unit area" Cox= eSiO2/tox
" t’ox% tox/S" C’ox % Cox×S
What might we do?Reduce dielectric constant, e, and not scale
thickness to mimic tox scaling.Penn ESE 370 Fall 2020 - Khanna 54
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High-K dielectric Survey
Wong/IBM J. of R&D, V46N2/3P133—168, 2002Penn ESE 370 Fall 2020 - Khanna 55
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Wire Layers = More Wiring
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Gate Delay
# tgd=Q/I=(CV)/I# V’$ V/S# I’d$ Id/S# Cg’$ Cg/S# t’gd$ tgd/S
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How might weaccelerate speed up?
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Gate Delay
# tgd=Q/I=(CV)/I# V’$ V
# I’d=(µCOXS/2)((W/S)/(L/S))(Vgs-VTH)2
# I’d$ Id×S
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Don’t scale V!
How might weaccelerate speed up?
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Gate Delay
# tgd=Q/I=(CV)/I# V’$ V
# I’d=(µCOXS/2)((W/S)/(L/S))(Vgs-VTH)2
# I’d$ Id×S# Cg’$ Cg/S# t’gd$ tgd/S2
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Don’t scale V!
How might weaccelerate speed up?
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But… Power Dissipation (Dynamic)
! Capacitive (Dis)charging
# P=(1/2)CV2f# V’$ V# C’$ C/S# P’$ P/S
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But… Power Dissipation (Dynamic)
! Capacitive (Dis)charging
# P=(1/2)CV2f# V’$ V# C’$ C/S# P’$ P/S
! Increase Frequency?# t’gd $ tgd/S2
# f’ $ f×S2
# P’ $ P×S
If don’t scale V, power dissipation doesn’t scale down!
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…And Power Density
! P’$ P×S (increase frequency)! A’$ A/S2
! What happens to power density?
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…And Power Density
! P’$ P×S (increase frequency)! A’$ A/S2
! What happens to power density?
! P/A $ S3×P
! Power Density Increases!
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Historical Voltage Scaling
! Frequency impact?! Power Density impact?
http://software.intel.com/en-us/articles/gigascale-integration-challenges-and-opportunities/
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Scale V separately with Factor U, (U<S)
! tgd=Q/I=(CV)/I! V’$V/U
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Scale V separately with Factor U
! tgd=Q/I=(CV)/I! V’$V/U
! I’d=(µCOXS/2)((W/S)/(L/S)(Vgs/U-VTH/U)2
! I’d$ S/U2×Id
! C’$ C/S
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Scale V separately with Factor U
! tgd=Q/I=(CV)/I! V’$V/U
! I’d=(µCOXS/2)((W/S)/(L/S)(Vgs/U-VTH/U)2
! I’d$ S/U2×Id
! C’$ C/S! t’gd$ ((1/(SU))/(S/U2))×tgd
! t’gd$ (U/S2)×tgd
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Scale V separately with Factor U
! tgd=Q/I=(CV)/I! V’$V/U
! I’d=(µCOXS/2)((W/S)/(L/S)(Vgs/U-VTH/U)2
! I’d$ S/U2×Id
! C’$ C/S! t’gd$ ((1/(SU))/(S/U2))×tgd
! t’gd$ (U/S2)×tgd
! f’ $ (S2/U)×fPenn ESE 370 Fall 2020 - Khanna 68
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Scale V separately with Factor U
! tgd=Q/I=(CV)/I! V’$V/U
! I’d=(µCOXS/2)((W/S)/(L/S)(Vgs/U-VTH/U)2
! I’d$ S/U2×Id
! C’$ C/S! t’gd$ ((1/(SU))/(S/U2))×tgd
! t’gd$ (U/S2)×tgd
! f’$ (S2/U)×fPenn ESE 370 Fall 2020 - Khanna 69
Ideal scale factors:S=100U=100t=1/100fideal=100
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Preclass 3
! Assuming Vdd=10V in a 10μm process and Vdd=1V in a 100nm process, what are S and U? (assume everything else scales according to ideal scaling.)" S =
" U =
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Scale V separately with Factor U
! tgd=Q/I=(CV)/I! V’$V/U
! I’d=(µCOXS/2)((W/S)/(L/S)(Vgs/U-VTH/U)2
! I’d$ S/U2×Id
! C’$ C/S! t’gd$ ((1/(SU))/(S/U2))×tgd
! t’gd$ (U/S2)×tgd
! f’$ (S2/U)×fPenn ESE 370 Fall 2020 - Khanna 71
Ideal scale factors:S=100U=100t=1/100fideal=100
Cheatingfactors:S=100U=10
How much faster are gates?
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Scale V separately with Factor U
! tgd=Q/I=(CV)/I! V’$V/U
! I’d=(µCOXS/2)((W/S)/(L/S)(Vgs/U-VTH/U)2
! I’d$ S/U2×Id
! C’$ C/S! t’gd$ ((1/(SU))/(S/U2))×tgd
! t’gd$ (U/S2)×tgd
! f’$ (S2/U)×fPenn ESE 370 Fall 2020 - Khanna 72
Ideal scale factors:S=100U=100t=1/100fideal=100
Cheatingfactors:S=100U=10t=1/1000fnew=1000
How much faster are gates?
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Scale V separately with Factor U
! tgd=Q/I=(CV)/I! V’$V/U
! I’d=(µCOXS/2)((W/S)/(L/S)(Vgs/U-VTH/U)2
! I’d$ S/U2×Id
! C’$ C/S! t’gd$ ((1/(SU))/(S/U2))×tgd
! t’gd$ (U/S2)×tgd
! f’$ (S2/U)×fPenn ESE 370 Fall 2020 - Khanna 73
Ideal scale factors:S=100U=100t=1/100fideal=100
Cheatingfactors:S=100U=10t=1/1000fnew=1000
fnew/fideal=10
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Power Density Impact
! P = (1/2)CV2 f! P $ (1/S) (1/U2) (S2/U) = S/U3
! P/A $ (S/U3) / (1/S2) = S3/U3
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Power Density Impact
! P = (1/2)CV2 f! P $ (1/S) (1/U2) (S2/U) = S/U3
! P/A $ (S/U3) / (1/S2) = S3/U3
! U=10 S=100! P/A $ 1000 (P/A)
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Power Density Impact
! P = (1/2)CV2 f! P $ (1/S) (1/U2) (S2/U) = S/U3
! P/A $ (S/U3) / (1/S2) = S3/U3
! U=10 S=100! P/A $ 1000 (P/A)
! Compare with ideal scaling:! P/A $ S3×P (ideal scaling)! P/A $ 1,000,000 (P/A) (ideal scaling)
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Scaling Methods
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42 Years of uP Trend Data
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Conventional Scaling
! Ends in your lifetime! Perhaps already:
" "Basically, this is the end of scaling.”" May 2005, Bernard Meyerson, V.P. and chief technologist for
IBM's systems and technology group
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ITRS 2.0 Report 2015
! “After 2021, the report forecasts, it will no longer be economically desirable for companies to continue traditional transistor miniaturization in microprocessors.”
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BUT…
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Source:https://newsroom.intel.com/newsroom/wp-content/uploads/sites/11/2017/09/mark-bohr-on-continuing-moores-law.pdf
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BUT…
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Source:https://newsroom.intel.com/newsroom/wp-content/uploads/sites/11/2017/09/mark-bohr-on-continuing-moores-law.pdf
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Big Ideas
! Moderately predictable VLSI Scaling" unprecedented capacities/capability growth for
engineered systems" …but not for much longer
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Admin
! Proj 1 Due Monday (no lecture)" I will NOT be extending Proj 1" Study old midterms!" Can only use one late day max
" Everyone on team must have a late day available to use
! Talk to your teammates!!!" Can use Canvas groups discussion" Can use Piazza" Can use email
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