and optimization for digital systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ese370:...

67
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec 23: October 30, 2020 Driving Large Capacitive Loads Penn ESE 370 Fall 2020 - Khanna

Upload: others

Post on 20-Jan-2021

2 views

Category:

Documents


0 download

TRANSCRIPT

Page 1: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems

Lec 23: October 30, 2020Driving Large Capacitive Loads

Penn ESE 370 Fall 2020 - Khanna

Page 2: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Today

! Back to CMOS today! How do we drive a large capacitive load?

" Stages and buffer sizing" Minimum delay

2Penn ESE 370 Fall 2020 - Khanna

Page 3: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Message

! To drive large loads" Scale buffers geometrically" Exponential scale up in buffer size

! Scale factor: 3—4 typically" One origin of FO4 target

! Drains contribute capacitance too (Cdiff)! Can formulate sizing to optimize

3Penn ESE 370 Fall 2020 - Khanna

Page 4: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Call back: Large Fanout Delay

! What is delay if must drive fanout=100?

Penn ESE 370 Fall 2020 - Khanna 4

Page 5: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Call back: …and Again

! Delay here?

Penn ESE 370 Fall 2020 - Khanna 5

Page 6: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Start Cdiff=0

6Penn ESE 370 Fall 2020 - Khanna

Page 7: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

One Stage (Preclass 1)

! How do we size to minimize delay?

7

WN

Penn ESE 370 Fall 2020 - Khanna

Page 8: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

One Stage (Preclass 1)

! Delay equation?

8

WN

Penn ESE 370 Fall 2020 - Khanna

Page 9: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

One Stage (Preclass 1)

! Delay equation?

9

delay = R022WN ⋅C0 +

R0WN

⋅Cload

WN

Penn ESE 370 Fall 2020 - Khanna

Page 10: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Minimize (Preclass 1)

! Differentiate and set to zero

! What’s WN?

10

delay = R0WN ⋅C0 +R0WN

⋅Cload

R0C0 −R0WN

2 ⋅Cload = 0

Penn ESE 370 Fall 2020 - Khanna

Page 11: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Minimize

! Differentiate and set to zero

! What’s WN?

11

delay = R0WN ⋅C0 +R0WN

⋅Cload

R0C0 −R0WN

2 ⋅Cload = 0

WN2 =

Cload

C0WN =

Cload

C0Penn ESE 370 Fall 2020 - Khanna

Page 12: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Concrete?

! What is WN for Cload=4x104C0?

12

WN

WN =Cload

C0

Penn ESE 370 Fall 2020 - Khanna

Page 13: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

k-stage (Preclass 2)

13

WN1 WN2 WNk

Penn ESE 370 Fall 2020 - Khanna

Page 14: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

k-stage Delay (Preclass 2)

14

2τ WN1

2+WN 2

WN1

+WN 3

WN 2

+...+ WNi

WN (i−1)

+WN (i+1)

WNi

+...+ WNk

WN (k−1)

"

#$$

%

&''+

R0WNk

×Cload

WN1 WN2 WNk

Penn ESE 370 Fall 2020 - Khanna

Page 15: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Size WNi to minimize delay (Preclass 2)

! How do we minimize?

15

2τ WN1

2+WN 2

WN1

+WN 3

WN 2

+...+ WNi

WN (i−1)

+WN (i+1)

WNi

+...+ WNk

WN (k−1)

"

#$$

%

&''+

R0WNk

×Cload

Penn ESE 370 Fall 2020 - Khanna

Page 16: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Size WNi to minimize delay (Preclass 2)

! Take partial derivative with respect to WNi and set = 0

16

2τ 0+ 0+ 0+...+ 1WN (i−1)

−WN (i+1)

WNi( )2+...+ 0

"

#$$

%

&''+ 0 = 0

2τ WN1

2+WN 2

WN1

+WN 3

WN 2

+...+ WNi

WN (i−1)

+WN (i+1)

WNi

+...+ WNk

WN (k−1)

"

#$$

%

&''+

R0WNk

×Cload

Penn ESE 370 Fall 2020 - Khanna

Page 17: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Size WNi to minimize delay (Preclass 2)

! Take partial derivative with respect to WNi and set = 0

17

2τ 0+ 0+ 0+...+ 1WN (i−1)

−WN (i+1)

WNi( )2+...+ 0

"

#$$

%

&''+ 0 = 0

2τ WN1

2+WN 2

WN1

+WN 3

WN 2

+...+ WNi

WN (i−1)

+WN (i+1)

WNi

+...+ WNk

WN (k−1)

"

#$$

%

&''+

R0WNk

×Cload

1WN (i−1)

=WN (i+1)

W 2Ni

→WNi

WN (i−1)

=WN (i+1)

WNi

Penn ESE 370 Fall 2020 - Khanna

Page 18: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Delay

! Conclude: at optimal sizing, ratio of stages is same:

18

1WN (i−1)

=WN (i+1)

W 2Ni

→WNi

WN (i−1)

=WN (i+1)

WNi

Penn ESE 370 Fall 2020 - Khanna

Page 19: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Delay

! Call that ratio 𝞺

19

ρ =WNi

WN (i−1)

=WN (i+1)

WNi

Penn ESE 370 Fall 2020 - Khanna

Page 20: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Stage Delay

20

2τ WN1

2+WN 2

WN1

+WN 3

WN 2

+...+ WNi

WN (i−1)

+WN (i+1)

WNi

+...+ WNk

WN (k−1)

"

#$$

%

&''+

R0WNk

×Cload

Penn ESE 370 Fall 2020 - Khanna

Page 21: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Stage Delay

21

2τ WN1

2+WN 2

WN1

+WN 3

WN 2

+...+ WNi

WN (i−1)

+WN (i+1)

WNi

+...+ WNk

WN (k−1)

"

#$$

%

&''+

R0WNk

×Cload

2τ WN1

2+WN 2

WN1

+WN 3

WN 2

+...+ WNi

WN (i−1)

+WN (i+1)

WNi

+...+ WNk

WN (k−1)

+R0

2τ ⋅WNk

×Cload

$

%&&

'

())

Penn ESE 370 Fall 2020 - Khanna

Page 22: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Stage Delay

22

ρ =WN1

2=

WNi

WN (i−1)

=WN (i+1)

WNi

=Cload

WNk 2C0( )

2τ WN1

2+WN 2

WN1

+WN 3

WN 2

+...+ WNi

WN (i−1)

+WN (i+1)

WNi

+...+ WNk

WN (k−1)

"

#$$

%

&''+

R0WNk

×Cload

2τ WN1

2+WN 2

WN1

+WN 3

WN 2

+...+ WNi

WN (i−1)

+WN (i+1)

WNi

+...+ WNk

WN (k−1)

+R0

2τ ⋅WNk

×Cload

$

%&&

'

())

Penn ESE 370 Fall 2020 - Khanna

Page 23: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Stage Delay

23

Two simplifications?1) in terms of r?

2) without r?

ρ =WN1

2=

WNi

WN (i−1)

=WN (i+1)

WNi

=Cload

WNk 2C0( )

Penn ESE 370 Fall 2020 - Khanna

Page 24: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Stage Delay

24

WN1

2!

"#

$

%&WN 2

WN1

!

"#

$

%&WN 3

WN 2

!

"#

$

%&!

WNi

WN (i−1)

!

"##

$

%&&WN (i+1)

WNi

!

"#

$

%&!

WNk

WN (k−1)

!

"##

$

%&&

Cload

WNk 2C0( )= ρ k+1

ρ =WN1

2=

WNi

WN (i−1)

=WN (i+1)

WNi

=Cload

WNk 2C0( )

Penn ESE 370 Fall 2020 - Khanna

Page 25: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Stage Delay

ρ k+1 =Cload

4C0→ ρ =

Cload

4C0k+1

25

ρ =Cload4C0

⎝⎜⎜

⎠⎟⎟

1k+1⎛

⎝⎜

⎠⎟

Penn ESE 370 Fall 2020 - Khanna

Page 26: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Total Delay

26

2τ WN1

2+WN 2

WN1

+WN 3

WN 2

+...+ WNi

WN (i−1)

+WN (i+1)

WNi

+...+ WNk

WN (k−1)

+R0

2τ ⋅WNk

×Cload

$

%&&

'

())

ρ =WN1

2=

WNi

WN (i−1)

=WN (i+1)

WNi

=Cload

WNk 2C0( )

Penn ESE 370 Fall 2020 - Khanna

Page 27: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Total Delay (Preclass 2)

27

TotalDelay = 2τ (k +1)ρ

ρ =WN1

2=

WNi

WN (i−1)

=WN (i+1)

WNi

=Cload

WNk 2C0( )

Penn ESE 370 Fall 2020 - Khanna

2τ WN1

2+WN 2

WN1

+WN 3

WN 2

+...+ WNi

WN (i−1)

+WN (i+1)

WNi

+...+ WNk

WN (k−1)

+R0

2τ ⋅WNk

×Cload

$

%&&

'

())

Page 28: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Total Delay

28

TotalDelay = 2τ (k +1)ρ

TotalDelay = 2τ (k +1) Cload

4C0

!

"#

$

%&

1k+1!

"#

$

%&

Penn ESE 370 Fall 2020 - Khanna

ρ =Cload4C0

⎝⎜⎜

⎠⎟⎟

1k+1⎛

⎝⎜

⎠⎟

Page 29: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Plot Delay vs. k (Cload=4x104C0)

29

0

50

100

150

200

250

300

350

400

450

1 2 3 4 5 6 7 8 9 10 11 12

Del

ay (t

units

)

Stages (k)

Delay vs. Number of Stages

TotalDelay = 2τ (k +1) Cload

4C0

!

"#

$

%&

1k+1!

"#

$

%&

Penn ESE 370 Fall 2020 - Khanna

Page 30: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Zoom: Plot Delay vs. k (Cload=4x104C0)

30

30

40

50

60

70

80

90

100

1 2 3 4 5 6 7 8 9 10 11 12

Del

ay (t

units

)

Stages (k)

Delay vs. Number of Stages

TotalDelay = 2τ (k +1) Cload

4C0

!

"#

$

%&

1k+1!

"#

$

%&

Penn ESE 370 Fall 2020 - Khanna

Page 31: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Minimize (Preclass 3)

31

0 = 2τ Cload

4C0

!

"#

$

%&

1k+1!

"#

$

%&

− (k +1) ⋅ ln Cload

4C0

!

"#

$

%&Cload

4C0

!

"#

$

%&

1k+1!

"#

$

%&

1k +1!

"#

$

%&2)

*

+++

,

-

.

.

.

TotalDelay = 2τ (k +1) Cload

4C0

!

"#

$

%&

1k+1!

"#

$

%&

Penn ESE 370 Fall 2020 - Khanna

d(bx )dx

= ln(b) ⋅bx

d(1 x)dx

= −1x2

Page 32: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Minimize (Preclass 3)

32

0 = 2τ Cload

4C0

!

"#

$

%&

1k+1!

"#

$

%&

− (k +1) ⋅ ln Cload

4C0

!

"#

$

%&Cload

4C0

!

"#

$

%&

1k+1!

"#

$

%&

1k +1!

"#

$

%&2)

*

+++

,

-

.

.

.

TotalDelay = 2τ (k +1) Cload

4C0

!

"#

$

%&

1k+1!

"#

$

%&

0 =1− 1k +1"

#$

%

&'ln

Cload

4C0

"

#$

%

&'

k = ln Cload

4C0

!

"#

$

%&−1

Penn ESE 370 Fall 2020 - Khanna

d(bx )dx

= ln(b) ⋅bx

d(1 x)dx

= −1x2

Page 33: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Concrete (Preclass 3)

! What is optimal k for Cload=4x104C0?

33

k = ln Cload

4C0

!

"#

$

%&−1

Penn ESE 370 Fall 2020 - Khanna

Page 34: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Zoom: Plot Delay vs. k (Cload=4x104C0)

34

30

40

50

60

70

80

90

100

1 2 3 4 5 6 7 8 9 10 11 12

Del

ay (t

units

)

Stages (k)

Delay vs. Number of Stages

TotalDelay = 2τ (k +1) Cload

4C0

!

"#

$

%&

1k+1!

"#

$

%&

Penn ESE 370 Fall 2020 - Khanna

Page 35: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Optimum Scale Up

! For optimum delay

! What is r?

35

k = ln Cload

4C0

!

"#

$

%&−1

ρ =Cload4C0

⎝⎜⎜

⎠⎟⎟

1k+1⎛

⎝⎜

⎠⎟

Penn ESE 370 Fall 2020 - Khanna

Page 36: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Optimum Scale Up

36

ρ =Cload4C0

⎝⎜⎜

⎠⎟⎟

1

lnCload4C0

⎝⎜⎜

⎠⎟⎟

⎜⎜⎜⎜⎜

⎟⎟⎟⎟⎟ = Y( )

1ln Y( )⎛

⎜⎜

⎟⎟

ln(ρ) = 1ln Y( )

ln(Y ) =1

ρ = e

Penn ESE 370 Fall 2020 - Khanna

Page 37: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Optimum Scale Up

37

ρ =Cload4C0

⎝⎜⎜

⎠⎟⎟

1

lnCload4C0

⎝⎜⎜

⎠⎟⎟

⎜⎜⎜⎜⎜

⎟⎟⎟⎟⎟ = Y( )

1ln Y( )⎛

⎜⎜

⎟⎟

ln(ρ) = 1ln Y( )

ln(Y ) =1

ρ = e

Penn ESE 370 Fall 2020 - Khanna

Page 38: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Call Back: Total Delay

38

TotalDelay = 2τ (k +1)ρ

2τ WN1

2+WN 2

WN1

+WN 3

WN 2

+...+ WNi

WN (i−1)

+WN (i+1)

WNi

+...+ WNk

WN (k−1)

"

#$$

%

&''+

R0WNk

×Cload

2τ WN1

2+WN 2

WN1

+WN 3

WN 2

+...+ WNi

WN (i−1)

+WN (i+1)

WNi

+...+ WNk

WN (k−1)

+R0

2τ ⋅WNk

×Cload

$

%&&

'

())

ρ =WN1

2=

WNi

WN (i−1)

=WN (i+1)

WNi

=Cload

WNk 2C0( )

Penn ESE 370 Fall 2020 - Khanna

Page 39: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Delay at Optimum

39

k = ln Cload

4C0

!

"#

$

%&−1 ρ = e

TotalDelay = 2τ (k +1)ρ

Penn ESE 370 Fall 2020 - Khanna

Page 40: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Delay at Optimum (Preclass 3)

40

k = ln Cload

4C0

!

"#

$

%&−1 ρ = e

TotalDelay = 2τ (k +1)ρ

TotalDelay = 2τ ⋅ ln Cload

4C0

"

#$

%

&'⋅e

! What is optimal delay for Cload=4x104C0 in tau units?

Penn ESE 370 Fall 2020 - Khanna

Page 41: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Zoom: Plot Delay vs. k (Cload=4x104C0)

41

30

40

50

60

70

80

90

100

1 2 3 4 5 6 7 8 9 10 11 12

Del

ay (t

units

)

Stages (k)

Delay vs. Number of Stages

TotalDelay = 2τ (k +1) Cload

4C0

!

"#

$

%&

1k+1!

"#

$

%&

Penn ESE 370 Fall 2020 - Khanna

Page 42: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Cdiff=gCgate

42Penn ESE 370 Fall 2020 - Khanna

Page 43: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Diffusion Capacitance (Preclass 4)

! What does this do to t model?" Delay of middle stage cascade?

43Penn ESE 370 Fall 2020 - Khanna

Page 44: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Diffusion Capacitance (Preclass 4)

! What does this do to t model?" Delay of middle stage cascade?

44

delayW1→W 2 =R0W1

"

#$

%

&' 2W1 ⋅Cdiff 0 + 2W2 ⋅C0( )

delayW1→W 2 = 2R0W1

"

#$

%

&' W1 ⋅γC0 +W2 ⋅C0( )

delayW1→W 2 = 2τ γ +W2

W1

"

#$

%

&'

Penn ESE 370 Fall 2020 - Khanna

Page 45: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

k-stage Delay

45

2τ WN1

2+WN 2

WN1

+WN 3

WN 2

+...+ WNi

WN (i−1)

+WN (i+1)

WNi

+...+ WNk

WN (k−1)

"

#$$

%

&''+

R0WNk

×Cload

delayW1→W 2 = 2τ γ +W2

W1

"

#$

%

&'

Penn ESE 370 Fall 2020 - Khanna

Page 46: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

k-stage Delay (Preclass 4)

46

2τ WN1

2+WN 2

WN1

+WN 3

WN 2

+...+ WNi

WN (i−1)

+WN (i+1)

WNi

+...+ WNk

WN (k−1)

"

#$$

%

&''+

R0WNk

×Cload

delayW1→W 2 = 2τ γ +W2

W1

"

#$

%

&'

2τ γ +WN1

2+γ +

WN 2

WN1

+γ +WN 3

WN 2

+...+γ + WNi

WN (i−1)

+γ +WN (i+1)

WNi

+...+γ + WNk

WN (k−1)

"

#$$

%

&''

+R0WNk

(Cload + 2γWNkC0 )Penn ESE 370 Fall 2020 - Khanna

Page 47: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

k-stage Delay

47

2τ γk +WN1

2+WN 2

WN1

+WN 3

WN 2

+...+ WNi

WN (i−1)

+WN (i+1)

WNi

+...+ WNk

WN (k−1)

"

#$$

%

&''+

R0WNk

(Cload + 2γWNkC0 )

2τ γk +WN1

2+WN 2

WN1

+WN 3

WN 2

+...+ WNi

WN (i−1)

+WN (i+1)

WNi

+...+ WNk

WN (k−1)

"

#$$

%

&''+

R0WNk

Cload + 2τγ

2τ γk +WN1

2+WN 2

WN1

+WN 3

WN 2

+...+ WNi

WN (i−1)

+WN (i+1)

WNi

+...+ WNk

WN (k−1)

+R0

2τWNk

Cload +γ"

#$$

%

&''

Penn ESE 370 Fall 2020 - Khanna

2τ γ +WN1

2+γ +

WN 2

WN1

+γ +WN 3

WN 2

+...+γ + WNi

WN (i−1)

+γ +WN (i+1)

WNi

+...+γ + WNk

WN (k−1)

"

#$$

%

&''

+R0WNk

(Cload + 2γWNkC0 )

Page 48: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

k-stage Delay

48

2τ γk +WN1

2+WN 2

WN1

+WN 3

WN 2

+...+ WNi

WN (i−1)

+WN (i+1)

WNi

+...+ WNk

WN (k−1)

"

#$$

%

&''+

R0WNk

(Cload + 2γWNkC0 )

2τ γk +WN1

2+WN 2

WN1

+WN 3

WN 2

+...+ WNi

WN (i−1)

+WN (i+1)

WNi

+...+ WNk

WN (k−1)

"

#$$

%

&''+

R0WNk

Cload + 2τγ

2τ γk +WN1

2+WN 2

WN1

+WN 3

WN 2

+...+ WNi

WN (i−1)

+WN (i+1)

WNi

+...+ WNk

WN (k−1)

+R0

2τWNk

Cload +γ"

#$$

%

&''

Penn ESE 370 Fall 2020 - Khanna

2τ γ +WN1

2+γ +

WN 2

WN1

+γ +WN 3

WN 2

+...+γ + WNi

WN (i−1)

+γ +WN (i+1)

WNi

+...+γ + WNk

WN (k−1)

"

#$$

%

&''

+R0WNk

(Cload + 2γWNkC0 )

Page 49: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

k-stage Delay

49

2τ γk +WN1

2+WN 2

WN1

+WN 3

WN 2

+...+ WNi

WN (i−1)

+WN (i+1)

WNi

+...+ WNk

WN (k−1)

"

#$$

%

&''+

R0WNk

(Cload + 2γWNkC0 )

2τ γk +WN1

2+WN 2

WN1

+WN 3

WN 2

+...+ WNi

WN (i−1)

+WN (i+1)

WNi

+...+ WNk

WN (k−1)

"

#$$

%

&''+

R0WNk

Cload + 2τγ

2τ γk +WN1

2+WN 2

WN1

+WN 3

WN 2

+...+ WNi

WN (i−1)

+WN (i+1)

WNi

+...+ WNk

WN (k−1)

+R0

2τWNk

Cload +γ"

#$$

%

&''

Penn ESE 370 Fall 2020 - Khanna

2τ γ +WN1

2+γ +

WN 2

WN1

+γ +WN 3

WN 2

+...+γ + WNi

WN (i−1)

+γ +WN (i+1)

WNi

+...+γ + WNk

WN (k−1)

"

#$$

%

&''

+R0WNk

(Cload + 2γWNkC0 )

Page 50: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

k-stage Delay

50

2τ γk +WN1

2+WN 2

WN1

+WN 3

WN 2

+...+ WNi

WN (i−1)

+WN (i+1)

WNi

+...+ WNk

WN (k−1)

"

#$$

%

&''+

R0WNk

(Cload + 2γWNkC0 )

2τ γk +WN1

2+WN 2

WN1

+WN 3

WN 2

+...+ WNi

WN (i−1)

+WN (i+1)

WNi

+...+ WNk

WN (k−1)

"

#$$

%

&''+

R0WNk

Cload + 2τγ

2τ γk +WN1

2+WN 2

WN1

+WN 3

WN 2

+...+ WNi

WN (i−1)

+WN (i+1)

WNi

+...+ WNk

WN (k−1)

+R0

2τWNk

Cload +γ"

#$$

%

&''

Penn ESE 370 Fall 2020 - Khanna

2τ γ (k +1)+WN1

2+WN 2

WN1

+WN 3

WN 2

+...+ WNi

WN (i−1)

+WN (i+1)

WNi

+...+ WNk

WN (k−1)

+R0

2τ ⋅WNk

⋅Cload

#

$%%

&

'((

2τ γ +WN1

2+γ +

WN 2

WN1

+γ +WN 3

WN 2

+...+γ + WNi

WN (i−1)

+γ +WN (i+1)

WNi

+...+γ + WNk

WN (k−1)

"

#$$

%

&''

+R0WNk

(Cload + 2γWNkC0 )

Page 51: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Size WNi to minimize delay

! Take partial derivative with respect to WNi = 0

51

2τ 0+ 0+ 0+...+ 1WN (i−1)

−WN (i+1)

WNi( )2+...+ 0

"

#$$

%

&''+ 0 = 0

1WN (i−1)

=WN (i+1)

W 2Ni

→WNi

WN (i−1)

=WN (i+1)

WNi

Penn ESE 370 Fall 2020 - Khanna

2τ γ (k +1)+WN1

2+WN 2

WN1

+WN 3

WN 2

+...+ WNi

WN (i−1)

+WN (i+1)

WNi

+...+ WNk

WN (k−1)

+R0

2τ ⋅WNk

⋅Cload

#

$%%

&

'((

Page 52: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Impact on Minimum WNi ?

! Partial derivative unchanged

52Penn ESE 370 Fall 2020 - Khanna

2τ γ (k +1)+WN1

2+WN 2

WN1

+WN 3

WN 2

+...+ WNi

WN (i−1)

+WN (i+1)

WNi

+...+ WNk

WN (k−1)

+R0

2τ ⋅WNk

⋅Cload

#

$%%

&

'((

Page 53: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Stage Delay: r unchanged (for fixed k)

53

ρ =WN1

2=

WNi

WN (i−1)

=WN (i+1)

WNi

=Cload

WNk 2C0( )

ρ =Cload4C0

⎝⎜⎜

⎠⎟⎟

1k+1⎛

⎝⎜

⎠⎟

Penn ESE 370 Fall 2020 - Khanna

Page 54: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Stage Delay: r unchanged (for fixed k)

54

ρ =WN1

2=

WNi

WN (i−1)

=WN (i+1)

WNi

=Cload

WNk 2C0( )

TotalDelay = 2τ (k +1)(ρ +γ )

TotalDelay = 2τ (k +1) Cload

4C0

!

"#

$

%&

1k+1!

"#

$

%&

!

"

###

$

%

&&&

ρ =Cload4C0

⎝⎜⎜

⎠⎟⎟

1k+1⎛

⎝⎜

⎠⎟

Penn ESE 370 Fall 2020 - Khanna

2τ γ (k +1)+WN1

2+WN 2

WN1

+WN 3

WN 2

+...+ WNi

WN (i−1)

+WN (i+1)

WNi

+...+ WNk

WN (k−1)

+R0

2τ ⋅WNk

⋅Cload

#

$%%

&

'((

Page 55: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Impact of Gamma

55

0

50

100

150

200

250

300

350

400

450

1 2 3 4 5 6 7 8 9 10 11 12

Del

ay (t

uni

ts)

Stages (k)

Delay vs. Number of Stages

g=0g=0.5g=1.0

g=1.5

Penn ESE 370 Fall 2020 - Khanna

Page 56: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Impact of Gamma

56

40

50

60

70

80

90

100

1 2 3 4 5 6 7 8 9 10 11 12

Del

ay (t

uni

ts)

Stages (k)

Delay vs. Number of Stages

g=0g=0.5g=1.0

g=1.5

Penn ESE 370 Fall 2020 - Khanna

Page 57: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Minimize

57

TotalDelay = 2τ (k +1)(ρ +γ )

TotalDelay = 2τ (k +1) Cload

4C0

!

"#

$

%&

1k+1!

"#

$

%&

!

"

###

$

%

&&&

0 = 2τ γ +Cload

4C0

!

"#

$

%&

1k+1!

"#

$

%&

− (k +1) ⋅ ln Cload

4C0

!

"#

$

%&Cload

4C0

!

"#

$

%&

1k+1!

"#

$

%&

1k +1!

"#

$

%&2)

*

+++

,

-

.

.

.

0 = γ + ρ − (k +1) ⋅ ln Cload

4C0

!

"#

$

%&ρ

1k +1!

"#

$

%&2

γ + ρ = ln Cload

4C0

!

"#

$

%&

1k +1!

"#

$

%&ρ

Penn ESE 370 Fall 2020 - Khanna

Page 58: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Solve

58

γ + ρ = lnCload4C0

⎝⎜⎜

⎠⎟⎟1k +1⎛

⎝⎜

⎠⎟ρ

γρ+1= ln

Cload4C0

⎝⎜⎜

⎠⎟⎟1k +1⎛

⎝⎜

⎠⎟

Penn ESE 370 Fall 2020 - Khanna

Page 59: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Solve

59

γ + ρ = lnCload4C0

⎝⎜⎜

⎠⎟⎟1k +1⎛

⎝⎜

⎠⎟ρ

γρ+1= ln

Cload4C0

⎝⎜⎜

⎠⎟⎟1k +1⎛

⎝⎜

⎠⎟

Penn ESE 370 Fall 2020 - Khanna

γρ+1= ln

Cload4C0

⎝⎜⎜

⎠⎟⎟

1k+1

⎜⎜⎜

⎟⎟⎟

γρ+1= ln ρ( )

Page 60: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Optimal Staging Any g

60Penn ESE 370 Fall 2020 - Khanna

𝜌 = 𝑒!"#$

Page 61: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

r and g? (Preclass 4)

! r=4 is optimal for what g?! r=3 is optimal for what g?

61Penn ESE 370 Fall 2020 - Khanna

𝜌 = 𝑒!"#$

ln 𝜌 =𝛾𝜌+ 1

𝜌 ln 𝜌 − 𝜌 = 𝛾

Page 62: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Impact of Gamma

62

40

50

60

70

80

90

100

1 2 3 4 5 6 7 8 9 10 11 12

Del

ay (t

uni

ts)

Stages (k)

Delay vs. Number of Stages

g=0g=0.5g=1.0

g=1.5

Penn ESE 370 Fall 2020 - Khanna

Page 63: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Optimal Fanout

! Clearer why we use r=4 as our benchmark?

63Penn ESE 370 Fall 2020 - Khanna

Page 64: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Idea

! To drive large loads" Scale buffers geometrically" Exponential scale up in buffer size (r = e)

! Scale factor: 3—4 typically" One origin of fanout 4 target

! Drains contribute capacitance too (Cdiff)! Can formulate sizing to optimize

64Penn ESE 370 Fall 2020 - Khanna

Page 65: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Admin

! P/F deadline today! Daylight savings on Sunday (fall back)! Project 2 due Monday 11/2

" Don’t turn it in late. Get it off your plate Monday night.

! Monday 11/2 lecture" Review, old exam problems, no new material

! Wednesday 11/4 lecture cancelled" Will be office hours instead

! Friday 11/6 Midterm (no lecture)! HW 6 posted 11/6

65Penn ESE 370 Fall 2020 – Khanna

Page 66: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Midterm

! Friday 11/6 Midterm " 2 hr window between 12pm EST – 12am EST

" If this window doesn’t work for you, let me know ASAP

" Lectures 1-22" Different exams, random set of questions" Open note, open book" Can’t communicate with anyone else about the exam until

after exam period is over" All old exams online (Look at Midterm 2)

" Study them!

" Zoe Review Session" See Piazza

66Penn ESE 370 Fall 2020 – Khanna

Page 67: and Optimization for Digital Systemsese370/fall2020/handouts/lec... · 2020. 10. 30. · ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec23: October

Admin: Midterm 2 Topics (up to Lec 22)

! Sizing! Tau-model

" Estimation and optimization

! Elmore-delay" Estimation and

optimization

! Energy and power" Estimation and

optimization" Dynamic and static

! Logic" CMOS" Ratioed" Pass transistor

! Transistor" Regions of operation" Parasitic Capacitance

Model

67

“idea” slides

Penn ESE 370 Fall 2020 – Khanna