penn ese370 fall2014 -- dehon 1 ese370: circuit-level modeling, design, and optimization for digital...
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Penn ESE370 Fall2014 -- DeHon1
ESE370:Circuit-Level
Modeling, Design, and Optimization for Digital Systems
Day 8: September 15, 2014
Delay and RC Response
Delay is RC Charging
Strategy• Understand switch
state (zeroth order)• Break into stages• For each stage
– Understand Rdrive
– Understand Cload
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Today
• RC Charging
• RC Step Response
• What is the C?
• What is the R?
• Measuring Delay
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• KCL @ Vmeasure?
• Current across Resistor?
• Current into Capacitor?
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Governing Equations? (KCL)
Equations
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€
Vin −Vmeasure
R=CdVmeasure dt
€
dVmeasuredt =
Vin −Vmeasure
RC
Solve Vmeasure
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€
dVmeasuredt =
Vin −Vmeasure
RC
What’s Vmeasure?
€
Vmeasure =Vin 1 − e−t
RC ⎛
⎝ ⎜
⎞
⎠ ⎟
⎛
⎝ ⎜
⎞
⎠ ⎟
Shape of Curve
x e-x 1-e-x
0
0.1
1
2
2.3
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V (t) = 1 − e−t /(RC )( )V
Fillin onboard
Shape of Curve
x e-x 1-e-x
0 1 0
0.1 0.9 0.1
1 1/e = 0.37 0.66
2 1/e2 = 0.14 0.86
2.3 0.1 0.9
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€
V (t) = 1 − e−t /(RC )( )V
Capacitance
• Wire
• MOSFET gate
• Logical Gate
• Fanout -- Total gate load
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First Order Model
• Switch – Loads input capacitively
• As dig in, understand:– Origin of capacitance– How can we engineer– Tradeoffs
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Resistance
• Wire resistance– Supply to transistor
source– Transistor output gate it
is driving
• Transistor equivalent resistance
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First Order Model
• Switch – Resistive driver
• As dig in, understand:– More sophisticated view– How can we engineer– Tradeoffs
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Equivalent Resistance
• What resistances might transistors contribute?– How many cases?– Assume Ron same all tr,
Resistance of each?
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Equivalent Resistance
• What resistances might transistors contribute?
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Input Rout
00 Ron/2
01 Ron
10 Ron
11 2Ron
Rise/Fall
• Rise and Fall time may differ– Why?– What is ratio?
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Input Rout
00 Ron/2
01 Ron
10 Ron
11 2Ron
Lumped Resistive Source
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€
Rdrive = Rtrnet + Rwii∈wires
∑ + Rpwr
Rtrnet = parallel and series combination of Rtr
Measuring Gate Delay
• Next stage starts to switch before first finishes
• Measure 50%--50%
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67ps
80ps
tdel = 13ps
Characterizing Gate/Technology
• Delay measure will be– Function of load on gate– Function of input rise time
• Which, in turn, may be a function of input loading
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Delay vs. Risetime
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10ps delay 20ps delay
1ps rise 100ps rise
(if didn’t know input rise, wouldn’t know what a 13ps delay meant)
Characterizing Gate/Technology
• Delay measure will be– Function of load on gate– Function of input rise time
• Which, in turn, may be a function of input loading
• Want to understand typical– At least comparable
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Standard Measurement for Characterization
• Drive with a gate – Not an ideal source– Input rise time typically would see in circuit
• Measure loaded gate– Typical loading – FO4
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Measurement for Characterization
• Drive with a gate – Not an ideal source (how change if drive ideal?)– Input rise time typically would see in circuit
• Measure loaded gate– Typical loading – FO4
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Measurement for Characterization
• Drive with a gate – Not an ideal source– Input rise time typically would see in circuit
• Measure loaded gate– Typical loading – FO4 (how change unloaded?)
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