penn ese370 fall2012 -- dehon 1 ese370: circuit-level modeling, design, and optimization for digital...
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Penn ESE370 Fall2012 -- DeHon1
ESE370:Circuit-Level
Modeling, Design, and Optimization for Digital Systems
Day 36: December 7, 2012
Transmission Line Scenarios
Repeaters in Wiring
Previously
• Transmission line (LC wire) reflection
• Unbuffered RC wire delay scales as L2
– 0.5 Rwire Cwire
– 0.5 L2 Ru Cu
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Today
• Transmission Line Scenarios
• RC (on-chip) Interconnect Buffering
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Transmission Line
• Data travels as waves
• Line has Impedance
• May reflect at end of line
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€
ViR − Z0
R + Z0
⎛
⎝ ⎜
⎞
⎠ ⎟=Vr
€
Vi2R
R + Z0
⎛
⎝ ⎜
⎞
⎠ ⎟=Vt
€
w =1
LC=
c0
ε rμ r
€
Z0 =L
C
Impedance Change
• What happens if there is an impedance change in the wire? Z0=75, Z1=50– What reflections and transmission do we get?
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Z0=75, Z1=50
• At junction: – Reflects
• Vr=(50-75)/(50+75)Vi
– Transmits• Vt=(100/(50+75))Vi
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€
ViR − Z0
R + Z0
⎛
⎝ ⎜
⎞
⎠ ⎟=Vr
€
Vi2R
R + Z0
⎛
⎝ ⎜
⎞
⎠ ⎟=Vt
Impedance Change Z0=75, Z1=50
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What happens at branch?
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Branch
• Transmission line sees two Z0 in parallel
– Looks like Z0/2
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Z0=50, Z1=25
• At junction: – Reflects
• Vr=(25-50)/(25+50)Vi
– Transmits• Vt=(50/(25+50))Vi
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€
ViR − Z0
R + Z0
⎛
⎝ ⎜
⎞
⎠ ⎟=Vr
€
Vi2R
R + Z0
⎛
⎝ ⎜
⎞
⎠ ⎟=Vt
End of Branch
• What happens at end?
• If ends in matched, parallel termination– No further reflections
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Branch Simulation
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Branch with Open Circuit?
• What happens if branch open circuit?
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Branch with Open Circuit
• Reflects at end of open-circuit stub
• Reflection returns to branch– …and encounters branch again– Send transmission pulse to both
• Source and other branch
• Sink sees original pulse as multiple smaller pulses spread out over time
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Open Branch Simulation
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Open Branch Simulation
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Bus
• Common to have many modules on a bus– E.g. PCI slots– DIMM slots for memory
• High speed bus lines are trans. lines
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http://en.wikipedia.org/wiki/File:DIMMs.jpg
Multi-drop Bus
• Ideal– Open circuit, no load
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Multi-Drop Bus
• Impact of capacitive load (stub) at drop?– If tight/regular enough, change Z of line
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€
Z0 =L
C
Multi-Drop Bus
• Long wire stub?– Looks like branch
• may produce reflections
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Transmission Line Noise
• Frequency limits
• Imperfect termination
• Mismatched segments/junctions/vias/connectors
• Loss due to resistance in line– Limits length
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Idea
• Transmission lines – high-speed– high throughput– long-distance signaling
• Termination
• Signal quality
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€
w =1
LC=
c0
ε rμ r
€
Z0 =L
C
€
Vr =ViR − Z0
R + Z0
⎛
⎝ ⎜
⎞
⎠ ⎟
Back to RC Wire
(on-chip, no L)
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Delay of Wire
• Long Wire: 1mm
• Rwire = 60K for the 1mm)
• Cwire = 0.16 pF for the 1mm)
• Driven by inverter– R0 = 25K
– C0 = 0.01 fF
– Assume velocity saturated, sized Wp=Wn=1
• Loaded by identical inverter
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Formulate Delay
€
Rbuf × Cself +Cwire +Cload( ) + 0.5Rwire ×Cwire + Rwire ×Cload
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Delay of inverter driving wire?
Should be able to do these calculations on final.
Calculate Delay
• Cload = 2 C0
• Rbuf = R0
• Cself = 2 C0 = 2 C0
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€
Rbuf × Cself +Cwire +Cload( ) + 0.5Rwire ×Cwire + Rwire ×Cload
Buffer Middle
• Delay if add buffer to middle of wire?
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Should be able to do these calculations on final.
Formulate and Calculate Delay
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€
2 Rbuf × Cself +Cwire
2+Cload
⎛
⎝ ⎜
⎞
⎠ ⎟+ 0.5
Rwire2
×Cwire
2
⎛
⎝ ⎜
⎞
⎠ ⎟+Rwire
2×Cload
⎛
⎝ ⎜
⎞
⎠ ⎟
N Buffers
• Delay for N buffers?
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€
N Rbuf × Cself +CwireN
+Cload ⎛
⎝ ⎜
⎞
⎠ ⎟+ 0.5
RwireN
×CwireN
⎛
⎝ ⎜
⎞
⎠ ⎟+RwireN
×Cload ⎛
⎝ ⎜
⎞
⎠ ⎟
€
N × Rbuf × Cself +Cload( ) + Rbuf ×Cwire + 0.5Rwire ×Cwire
N
⎛
⎝ ⎜
⎞
⎠ ⎟+ Rwire ×Cload
Minimize Delay
• How minimize delay?
• Differentiate &Solve for N:
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€
N = 0.5Rwire ×Cwire
Rbuf × Cself +Cload( )
⎛
⎝
⎜ ⎜
⎞
⎠
⎟ ⎟
€
2 0.5Rwire ×Cwire × Rbuf × Cself +Cload( ) + Rbuf ×Cwire + Rwire ×Cload
€
N × Rbuf × Cself +Cload( ) + Rbuf ×Cwire + 0.5Rwire ×Cwire
N
⎛
⎝ ⎜
⎞
⎠ ⎟+ Rwire ×Cload
Equalizes delay in buffer and wire
Calculate: Delay at Optimum Stages for Example
• Rwire = 60K for the 1mm)
• Cwire = 0.16 pF for the 1mm)
• Rbuf=R0 = 25K
• Cself=Cload=2(C0 = 0.01 fF)=0.02fF
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€
2 0.5Rwire ×Cwire × Rbuf × Cself +Cload( ) + Rbuf ×Cwire + Rwire ×Cload
Segment Length
• Rwire = L×Runit
• Cwire = L×Cunit
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€
N = 0.5Rwire ×Cwire
Rbuf × Cself +Cload( )
⎛
⎝
⎜ ⎜
⎞
⎠
⎟ ⎟
€
N = L 0.5Ru ×Cu
Rbuf × Cself +Cload( )
⎛
⎝
⎜ ⎜
⎞
⎠
⎟ ⎟
Optimal Segment Length
• Delay scales linearly with distance once optimally buffered
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€
N = L 0.5Ru ×Cu
Rbuf × Cself +Cload( )
⎛
⎝
⎜ ⎜
⎞
⎠
⎟ ⎟
€
Lseg* =
L
N= 2
Rbuf × Cself +Cload( )
Ru ×Cu
⎛
⎝
⎜ ⎜
⎞
⎠
⎟ ⎟
Buffer Size?
• How big should buffer be?– Rbuf = R0/W
– Cload = 2 W C0 (assuming velocity saturation)
– Cself = 2 W C0
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€
2 0.5Rwire ×Cwire × Rbuf × Cself +Cload( ) + Rbuf ×Cwire + Rwire ×Cload
€
2 0.5Rwire ×Cwire ×R0
W× 1+γ( )2WC0 +
R0
W×Cwire + Rwire × 2WC0
Implication W
• Rwire = L×Runit
• Cwire = L×Cunit
W independent of Length– Depends on technology
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€
W =R0 ×CwireRwire × 2C0
Delay at Optimum W
• With =1, 1+=2
• Same size as first term
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€
2 0.5Rwire ×Cwire × R0 × 1+γ( )2C0 + 2 R0 ×Cwire × Rwire × 2C0
€
4 R0 ×Cwire × Rwire × 2C0
Ideas
• Wire delay linear once buffered
• Optimal buffering matches– Buffer delay– Delay on wire between buffers
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Admin
• Final – Friday 12/14, noon, Moore 212
• Review – Wednesday, 12/12– Evening – time announced on piazza
• Andre out of town until Friday
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