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48 ©2013 IEEE Electromagnetic Compatibility Magazine – Volume 2 – Quarter 4 Title: DESIGN AND MODELING for 3D ICs AND INTERPOSERS Authors: Madhavan Swaminathan and Ki Jin Han Publisher: World Scientific Publishing Co., 2013 ISBN: 978-981-4508-60-5 It appears that 3D integration with through silicon vias (TSV) is finally here! I am referring to the mem- ory-on-logic and logic-on-logic applications where the improvement in performance, transistor density and form factor enables the electronics industry to continue the miniaturization of systems. Because of this, the timing of this book is about right. In six chapters and 358 pages, this book covers diverse topics such as system integration trends, design exchange formats, parasitic extraction, multiple technologies, signal integrity, power distribution and thermal management in the context of 3D ICs and interposers. We hope that this book is useful to readers, either at the basic or expert level. Chapter 1 consists of three parts related to 3D integra- tion namely, 1) an introductory part on system integra- tion trends and miniaturization, 2) the importance of modeling at an early phase and 3) the need for design exchange formats (DEF). System integration and minia- turization require advances in both IC and package integration which are discussed in the context of Moore and More than Moore scaling. The need for 2.5D and 3D integration using TSVs is explained along with three embodiments of its implementation, namely die stacking, package enabled stacking and interposer based solution. Two current interposer technologies being pursued by industry, silicon and glass, have been compared for their electri- cal performance. The section on modeling compares the challenges associated with both full wave electromagnetic modeling and phys- ics based (analytical) modeling, from a user perspective. Finally, the need for DEF is illustrated through two examples related to DC drop and thermal analysis. This part draws on the methods discussed in later chapters and is targeted towards expert readers who work on these kinds of analysis on a regular basis. The objective of this sec- tion is to illustrate the complexity involved in designing 3D ICs when all of the design information is unavailable (as very often it happens in the industrial design flow). The focus of chapter 2 is on parasitic extraction and simulation. This chapter delves deep into numerical modeling for ICs and packages that use interconnections with circular cross section. These struc- tures are very important in 3D integration especially when wirebonds or vias are used to connect between IC stacks or between packages (package on package), respectively. Graduate students will find this chapter useful, since the intricacies related to modeling are covered here. Specifically, new basis functions that approximate current and charge density distributions are introduced to simplify the modeling of these structures, which are then combined with the more tradi- tional methods for analyzing planar interconnections. A natural extension to chapter 2 is chapter 3 where the numerical methods are extended to analyze TSVs. Chapter 3 starts with a discussion on the electrical behavior of TSVs and the reason for such a response. Both physics based and rigorous numerical modeling methods are covered in this chapter to make it useful to both a beginner and an expert reader. The effect of biasing the silicon substrate on the electrical response of TSVs is discussed using full depletion analysis and detailed numerical modeling. The basis functions derived in chapter 2 are extended to cover TSVs to account for polarization current and biasing as well. Book Review Antonio Orlandi, Associate Editor Dear IEEE EMC Society Members, The “Book Review” columns that are published in our EMC Magazine are a great treasure for all of us. They give us the possibility to be informed of the existence and contents of published books that are of interest in the wide range of top- ics covered by our common technical and scientific interest: Electromagnetic Compatibility. The large number of books published on EMC related topics per year makes it impossible for a mortal Associate Editor to be acquainted with all of them. Because of this I wish to ask for your help if you: • Are or have been a reader of a technical book that you con- sider worthy to be read in our community • Have noticed a book that could be of interest to the IEEE EMC Society members • Are an author of a technical book on EMC related issues Please write to me as below indicating the author(s), the title, the publisher, the ISBN and a brief description of the book and/or your comments. This will help me greatly in consider- ing the books for review and will increase the number of titles reviewed for the benefit of our EMC community. I am grateful in advance for your help and time, Antonio Orlandi Book Review Associate Editor [email protected]

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48 ©2013 IEEE Electromagnetic Compatibility Magazine – Volume 2 – Quarter 4

Title: DESIGN AND MODELING for 3D ICs AND INTERPOSERSAuthors: Madhavan Swaminathan and Ki Jin HanPublisher: World Scientific Publishing Co., 2013ISBN: 978-981-4508-60-5

It appears that 3D integration with through silicon vias (TSV) is finally here! I am referring to the mem-ory-on-logic and logic-on-logic applications where the improvement in performance, transistor density and form factor enables the electronics industry to continue the miniaturization of systems. Because of this, the timing of this book is about right.

In six chapters and 358 pages, this book covers diverse topics such as system integration trends, design

exchange formats, parasitic extraction, multiple technologies, signal integrity, power distribution and thermal management in the context

of 3D ICs and interposers. We hope that this book is useful to readers, either at the basic or expert level.

Chapter 1 consists of three parts related to 3D integra-tion namely, 1) an introductory part on system integra-tion trends and miniaturization, 2) the importance of modeling at an early phase and 3) the need for design exchange formats (DEF). System integration and minia-turization require advances in both IC and package integration which are discussed in the context of Moore and More than Moore scaling. The need for 2.5D and 3D integration using TSVs is explained along with three embodiments of its implementation, namely die stacking, package enabled stacking and interposer

based solution. Two current interposer technologies being pursued by industry, silicon and glass, have been compared for their electri-cal performance. The section on modeling compares the challenges associated with both full wave electromagnetic modeling and phys-ics based (analytical) modeling, from a user perspective. Finally, the need for DEF is illustrated through two examples related to DC drop and thermal analysis. This part draws on the methods discussed in later chapters and is targeted towards expert readers who work on these kinds of analysis on a regular basis. The objective of this sec-tion is to illustrate the complexity involved in designing 3D ICs when all of the design information is unavailable (as very often it happens in the industrial design flow).

The focus of chapter 2 is on parasitic extraction and simulation. This chapter delves deep into numerical modeling for ICs and packages that use interconnections with circular cross section. These struc-tures are very important in 3D integration especially when wirebonds or vias are used to connect between IC stacks or between packages (package on package), respectively. Graduate students will find this chapter useful, since the intricacies related to modeling are covered here. Specifically, new basis functions that approximate current and charge density distributions are introduced to simplify the modeling of these structures, which are then combined with the more tradi-tional methods for analyzing planar interconnections.

A natural extension to chapter 2 is chapter 3 where the numerical methods are extended to analyze TSVs. Chapter 3 starts with a discussion on the electrical behavior of TSVs and the reason for such a response. Both physics based and rigorous numerical modeling methods are covered in this chapter to make it useful to both a beginner and an expert reader. The effect of biasing the silicon substrate on the electrical response of TSVs is discussed using full depletion analysis and detailed numerical modeling. The basis functions derived in chapter 2 are extended to cover TSVs to account for polarization current and biasing as well.

Book ReviewAntonio Orlandi, Associate Editor

Dear IEEE EMC Society Members,

The “Book Review” columns that are published in our EMC Magazine are a great treasure for all of us. They give us the possibility to be informed of the existence and contents of published books that are of interest in the wide range of top-ics covered by our common technical and scientific interest: Electromagnetic Compatibility.

The large number of books published on EMC related topics per year makes it impossible for a mortal Associate Editor to be acquainted with all of them.

Because of this I wish to ask for your help if you:

• Are or have been a reader of a technical book that you con-sider worthy to be read in our community

• Have noticed a book that could be of interest to the IEEE EMC Society members

• Are an author of a technical book on EMC related issues

Please write to me as below indicating the author(s), the title, the publisher, the ISBN and a brief description of the book and/or your comments. This will help me greatly in consider-ing the books for review and will increase the number of titles reviewed for the benefit of our EMC community.

I am grateful in advance for your help and time,

Antonio Orlandi Book Review Associate Editor

[email protected]

49©2013 IEEE Electromagnetic Compatibility Magazine – Volume 2 – Quarter 4

The material covered in chapter 4 is quite different as compared to chapters 2 and 3. The chapter begins with a focus on parameter sweeps to illustrate the role of physical and material parameters on the electrical response of TSVs, for both biased and unbiased sub-strates. In chapter 4 TSV arrays are analyzed to assess cross talk and their effect on electrical performance. The criticality of excessive cross talk in silicon interposer designs with no ground plane is illus-trated through time domain waveforms. An important element of this chapter is the comparison between silicon and glass interposers for achieving signal integrity, an area that is of utmost importance in high speed designs. The concept of return path discontinuity (RPD) is intro-duced for the first time in this chapter. Since signal and power integri-ty are related to each other, the response of power and ground planes for both the silicon and glass interposer are compared to determine which one is better, from an electrical performance perspective.

In 3D technology two topics are certainly related: the first is power delivery and the second is thermal management. They are combined in chapter 5. In the interposer and package, one major cause for power supply noise is return path discontinuities (RPD), and therefore this topic is covered in this chapter as well. The difficulty in meeting the target impedance for 3D ICs and the futility in minimizing simulta-neous switching noise are illustrated through two examples. The chapter then covers signaling between ICs through the interposer and package containing voltage and ground planes, to illustrate the occur-rence of RPDs and their effect in corrupting the eye diagrams. As shown in the chapter, this effect can be mitigated using decoupling capacitors. However, systems today use a large number of capacitors

integrated in the chip, embedded in the package and assembled on the board. These components often times increase the cost of a sys-tem due to an increase in layer count and board dimensions. This aspect of the problem is highlighted in this chapter. The last part of the chapter addresses the relationship between DC drop and temper-ature gradient. The numerical aspects of the problem and its applica-tion to both silicon and glass interposer technologies are addressed using conduction, convection and fluidic cooling. The numerical meth-ods described in this chapter are also used in chapter 4 for analyzing the effect of temperature on the electrical response of TSVs.

Finally chapter 6 covers alternate methods for power distribution using power transmission lines. This chapter will be considered by most readers as controversial since it argues that eliminating voltage planes in the package and board can help eliminate RPDs, reduce layer count and reduce the number of decoupling capacitors required. The methods described in chapter 6, in my opinion, are still in their infancy. Nevertheless, it is a different way of looking at the problem and I’m sure that these ideas can energize others in the signal and power integrity community to innovate.

Many examples in the book are developed by using the 3D Path Finder (3DPF), a software tool primarily developed for analyzing structures arising in 3D integration, which can be a useful mate for a better understanding of this topic.

In summary, this is a very good book dealing with a very hot tech-nical and scientific topic. EMC

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