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SEMICON Japan 2001 e-Manufacturing Workshop— Atsuhiko Kato — Slide 1
APC / EES Systems and Applications
APC / EES Systems and ApplicationsDec. 4, 2001
Atsuhiko Kato
SEMICON Japan 2001 e-Manufacturing Workshop— Atsuhiko Kato — Slide 2
APC / EES Systems and Applications
Presentation Overview1. Catalyst APC Framework2. APC Case Studies
In-situ CMP endpoint controlOverlay controlPost-etch CD controlResist CD controlDose & Focus control with SCD
3. APC Implementation4. Integrated Metrology5. Future Challenges
SEMICON Japan 2001 e-Manufacturing Workshop— Atsuhiko Kato — Slide 3
APC / EES Systems and Applications
1. Catalyst APC FrameworkCatalyst is the ONLY SEMI E93 standard compliant APC Framework commercially available
Standard, proven technologyMatlab™, CORBA, Oracle™, C++, Tcl/Tk, Java
MES/MES/EquipmentEquipmentManagerManager Control
JobInterface
Process
Metrology
ControlExecutor
ControlDatabase
ControlHistory
OracleDB
OracleDB
SECS/GEM
Control Script, Control Script, Algorithm Algorithm
DevelopmentDevelopment
ControllerControllerAnalysisAnalysis
SQL
Tcl
MatlabProcessControl
WorkbenchGUI
CORBA IIOPCORBA IIOP
SEMICON Japan 2001 e-Manufacturing Workshop— Atsuhiko Kato — Slide 4
APC / EES Systems and Applications
2. APC Case Studies
2001 2002 2003 2004 2005 2006 2007130 nm 115 nm 100 nm 90 nm 80 nm 70 nm 65 nm
Half pitch (nm) 130 115 100 90 80 70 65Contacts (nm) 150 130 115 100 90 80 70Overlay (nm, mean + 3σ) 45 40 35 31 28 25 23CD control (nm, 3σ) 15.9 11.0 10.0 9.0 8.0 7.0 7.0
Half pitch 150 130 107 90 80 70 65Gate length in resist (nm) 90 75 65 53 45 40 35Post-etch Gate length (nm) 65 53 45 37 32 28 25Contacts in resist (nm) 150 130 115 100 90 80 70CD control (nm, 3σ) 5.3 4.3 3.7 3.0 2.6 2.3 2.0
開始年
DRAM
MPU/ASIC
Year/node
(Source : ITRS 2001)
Due to shrinking error budget, APC is becoming an integral tool for litho process control
SEMICON Japan 2001 e-Manufacturing Workshop— Atsuhiko Kato — Slide 5
APC / EES Systems and Applications
2. APC Case StudiesIn which process areas is R2R Control being applied today?Review case studies of R2R Control applications currently being implemented in device manufacturing
– CMP (Cu, ILD, STI)• In-situ endpoint control (Cu)• Lot mean thickness control (SiO2)• Within wafer non-uniformity control
– Lithography• Overlay alignment control• Resist CD control• Post-etch CD control
– Furnace CVD Deposition / Oxidation– Ion Implant
SEMICON Japan 2001 e-Manufacturing Workshop— Atsuhiko Kato — Slide 6
APC / EES Systems and Applications
CMP : In-situ endpoint control for Cu process
Proximity sensor
Reflectometer
Table rotation (CCW)
Carrier ring
Sensor path
Wafer
Slip ring
Eddy current probe
Acquisitionelectronics
CMP controllerPRECICETM
computer
Optical endpoint
Absolute Cu thickness
PRECICETM
Flexible Window
Multi-angle 800 nm Lasers
Platen
2. APC Case Studies
SEMICON Japan 2001 e-Manufacturing Workshop— Atsuhiko Kato — Slide 7
APC / EES Systems and Applications
CMP : In-situ endpoint control for Cu process
• CMP Controller• PRECICETM endpoint system• Benefits
– 2+ wph throughput improvement– Higher tool OEE
Absolute thickness monitoring enabled stable endpoint detection regardless of initial film thickness fluctuation
Reduced send ahead wafersFaster Cu bulk removal rate
2. APC Case Studies
SEMICON Japan 2001 e-Manufacturing Workshop— Atsuhiko Kato — Slide 8
APC / EES Systems and Applications
Litho : Overlay Control
• Overlay refers to the layer-to-layer alignment of adjacent device features
• Mis-registration can result in excessive device leakage or an open inter-connect
Overlay [nm]
connectivity
good
disconnect
+180-180 0Lo
w p
erfo
rman
ceOL budget
+65-65
Single connection
2. APC Case Studies
SEMICON Japan 2001 e-Manufacturing Workshop— Atsuhiko Kato — Slide 9
APC / EES Systems and Applications
Catalyst APC Framework
CorrectionsOffsetsOverlay Controller
Offsetk+1= Offsetk - Filtered Errork
• Overlay Controller• Catalyst APC Framework• Benefits
– Cpk > 1.0– σOverlay, site basis, by 30%– Rework rate during ramp – Eliminated test wafers & tool quals– Full mix-and-match lithography
Run-to-Run Control
-10
-8
-6
-4
-2
0
2
4
6
8
10
Lot
Err
or
Stage Offset
Translation Error
Uncontrolled
-10
-8
-6
-4
-2
0
2
4
6
8
10
Lot
Err
or
Stage Offset
Translation Error
Bias
Reference: Christopher A. Bode. October, 1999. “Run-to-Run Control of Photolithography Overlay.” Proceedings of SEMATECH AEC/APC Symposium XI.
Litho : Overlay Control2. APC Case Studies
SEMICON Japan 2001 e-Manufacturing Workshop— Atsuhiko Kato — Slide 10
APC / EES Systems and Applications
Post-etch CD
Resist CD
Etch Bias
Source Drain
• CD Controller- Adjust etch time
• Catalyst Framework• Benefits
- MPU MHz 8%, σ 48%- Drive Current 10%, σ 41%- Rework 83%
Etch
Post-etch CD
Catalyst APC Framework
CD ControllerResist CD
Etch time
Litho : Post-etch CD Control
BIAS = ResistCD – PostEtchCD= a*t2+b*t+c
ResistCD - c = PostEtchCD+ a*t2+b*t
2. APC Case Studies
SEMICON Japan 2001 e-Manufacturing Workshop— Atsuhiko Kato — Slide 11
APC / EES Systems and Applications
• CD Controller• Catalyst Framework• Benefits
- Tighter speed distribution- σCD 64%- σLeff 59%- σFmax 53%
Estimated revenue increaseof $2M / wk / 1K starts
CD Control
Catalyst APC Framework
Dose
CD
Litho : Resist CD Control
Dosen= Dosen-1 - B*(CDn-1 - CDtarget)
0
20
40
60
80
100
% F
un
ctio
nin
gD
evic
es
Device Speed
MPU Speed Distribution
Before CD Control After CD Control
2. APC Case Studies
SEMICON Japan 2001 e-Manufacturing Workshop— Atsuhiko Kato — Slide 12
APC / EES Systems and Applications
Linewidth
Etch Lithography
Metrology ExposeWafer/Substrate DevelopPEBEnvironmentCoat
Reflectivity
Flatness
Topography
Resist Soft Bake
Type
Exhaust Flow
Lot #
Viscosity
Sensitivity
Contrast
Thickness
Dispense Volume
Shelf History
Spin Speed
Uniformity
Solvent Vapor
Acceleration Profile
Surface Prep
EBR
Wafer Temperature
ARC
Thickness
Uniformity
Time
Temperature
Time
Temperature
Chill Plate
Reticle Exposure
Chrome
CD
Transmission
Edge Roughness
Defects
OPC
Design Rule Error
CD
Proximity Error
Defects
Shifter
CD
Phase
Defects
Lens Aberrations
Lens Heating
Focus
Vibration
Leveling
Dose
BandwidthTime
Illumination
Energy
Laser Power
Pulses
Scan SpeedSigma
Geometry
AmineConcentration
Humidity
Pressure
PEB-Chill Delay
Expose-PEB Delay
Bake
Time
Temperature
Uniformity
Environment
Time
Exhaust Flow
Developer
Molality
Temperature
Spray
Pattern
Pressure
Flow Rate
Rinse
Profile
Flow Rate
Uniformity
Uniformity
Temperature
Chill Plate
Index ofRefraction
Absorbance
Uniformity
Chill
Time
Temperature
Defects
Defects
Defects Uniformity
Source:
CD Effects - Litho
SEMICON Japan 2001 e-Manufacturing Workshop— Atsuhiko Kato — Slide 13
APC / EES Systems and Applications
Total
Reticl
e
Etch
Focus
Metro
logy
PEB tem
p
Expos
ure
Resist
Lens
Develo
p Tem
p
Lase
rDev
elop
Time
PAB tem
p
PEB time
PAB time
0
2
4
6
8
10
12
14
16
CD
var
iati
on
(n
m)
Adjustable
Fixed
Reticle/Stepper
Wafer
ProcessX
X
X
Stability
Sources of CD VariationQuantifies Contribution From Each Source
Source:
CAUTION! Exposure (dose) changes can mask focus (and other) problems
CAUTION! Exposure (dose) changes can mask focus (and other) problems
SEMICON Japan 2001 e-Manufacturing Workshop— Atsuhiko Kato — Slide 14
APC / EES Systems and Applications
SpectraCDTM
Film Thickness& CD Metrology
Grating
Spectrum matchTo Library
CD, Height,Side-wall angle
High throughput: 70 wph
No side effects with 193nm resists or low K dielectrics
Precision: <1nm (3σ)
Shape of the feature is critical to performance:
Profile information:
CD, sidewall angle, height,(X-Z dimensions)
TCD
MCD
BCD
HT
WA
Dose & Focus control with SCD (scatterometry)2. APC Case Studies
SEMICON Japan 2001 e-Manufacturing Workshop— Atsuhiko Kato — Slide 15
APC / EES Systems and Applications
Realtime in-situ tool control APC-1
Tool Drift Compensation APC-3
Self diag & e-Diag interface
W2W process control
Intra-module feedback APC-2
Intra-module feedforward APC-4
R2R process control
Inter-module feedback APC-2
Inter-module feedforward APC-4
Embedded APC
Process Module APC
Fab wide APC
3. APC Implementation
Process variation adjustment
APC classification proposed by Selete
Adjust target values and/or control models depending on process factors such as:
- Underlying film stack - Pattern density and geometry
Open platform architectureStandardized interface for
- Tool connectivity- Control model sockets- Communicating with existing factory systems
SEMICON Japan 2001 e-Manufacturing Workshop— Atsuhiko Kato — Slide 16
APC / EES Systems and Applications
Resist CD
Post-etch CD
Etch Time
Etch TimeResist CD
Target
Dose(Dose & Focus)
Scanner/Track Etcher
CD MetrologyCD Metrology
APC
APC
APC
SECS/GEM
Group Controller(Local APC)
Sensor IMM
Controller
Embedded APC
3. APC ImplementationProcess Module APC
EE
S
Process information
SEMICON Japan 2001 e-Manufacturing Workshop— Atsuhiko Kato — Slide 17
APC / EES Systems and Applications
4. Integrated Metrology
iCDTM
SEMICON Japan 2001 e-Manufacturing Workshop— Atsuhiko Kato — Slide 18
APC / EES Systems and Applications
• Reducing the total turn-around time, would provide the manufacturer the ability to control high bandwidth process variations.
4. Integrated MetrologyTurn Around Time
Time
Err
or target Compensate for changes faster than:Standalone > 8 LotsIntegrated < 1 Lot
Process Inspection &Measurement
Control
MaterialDelay
DataDelay
ControlDelay
SEMICON Japan 2001 e-Manufacturing Workshop— Atsuhiko Kato — Slide 19
APC / EES Systems and Applications
4. Integrated MetrologyTighter Process Control
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
0 5 10 15 20Metrology Delay (lots)
CD
Std
. Dev
iatio
n
iCD+APC
CDSEM+APC
CDSEM
11% improvement in resist CD distribution w/ lot to lot iCD simulated control
Up to 19% w/ closed loop true lot to lot control
200 210 220 230
0.0
0.2
0.4
0.6
0.8
1.0
Nor
mal
ized
Fre
quen
cy
CD (nm)
Closed LoopOpen Loop
0.0
$$/nm
0 200 400 600 800 1000140
160
180
200
220
240
260
Closed Loop = 4.2nm
Open Loop = 4.7nm
Wafers
Ope
n L
oop
CD
(nm
)
160
180
200
220
240
260
280
Closed L
oop CD
(nm)
SEMICON Japan 2001 e-Manufacturing Workshop— Atsuhiko Kato — Slide 20
APC / EES Systems and Applications
4. Integrated MetrologyProcess Control with Integrated Metrology
Stepper
Rework
Local CtrlLocal Ctrl
RecipeRecipe
DataData
Fab DB
APCSPCAnalysis
Disposition OK
Rework Matching
Matching
Matching
0 100 2000 100 200
OK
Standalone Metrology
In depth analysisIn depth analysis
TrackEtcher
SEMICON Japan 2001 e-Manufacturing Workshop— Atsuhiko Kato — Slide 21
APC / EES Systems and Applications
5. Future ChallengesDevelopment of advanced control models- Lack of qualified control engineers- Motivation and culture of the industry
Distributed APC as opposed to centralized APC- Host system should not go beyond EFEM- Local APC system (tool control, module control)- Need more in-situ sensors and metrology tools
Development of cost effective system design for small lot production fabs
SEMICON Japan 2001 e-Manufacturing Workshop— Atsuhiko Kato — Slide 22
APC / EES Systems and Applications
End