APPLICATIONS OF VHDL TO CIRCUIT DESIGN

APPLICATIONS OF VHDL TO

CIRCUIT DESIGN

edited by

Randolph E. Harr C.A.D.onomist

Alee G. Staneuleseu Fintronic USA, Inc.

~.

" Springer Science+Business Media, LLC

APPLICATIONS OF VHDL TO

CIRCUIT DESIGN

edited by

Randolph E. Harr C.A.D.onomist

Alec G. Stanculescu Fintronic USA, Inc.

~.

" Springer Science+Business Media, LLC

Ubrary 01 CoDaresa Ca,aloalDa-iD-PublicadoD Data

Applieations of VHDL to eircuit design / edited by Randolph E. Harr. Alee G. Staneuleseu.

p. em. Ineludes bibliographieal referenees and index . ISBN 978-1-4613-6770-3 ISBN 978-1-4615-3964-3 (eBook) DOI 10.1007/978-1-4615-3964-3 I. Eleetronie cireuit design-Data processing. 2. VHDL (Computer

hardware deseription language) I. Harr. Randolph E .• 19S9-11. Staneuleseu. Alec G. TK7867.A64 1991 621.381 'S-de20 91-107S6

Chapter 1 is Copyright © by Alee G. Staneulescu. Chapter 2 is Copyright © by Balsha R. Stanisie.

CIP

Chapter 3 is Copyright © by Balsha R. Stanisie and Mark W. Brown. Chapter 4 is Copyright © by Balsha R. Stanisie. Chapter S is Copyright © by Steve Carlson. Chapter 6 is Copyright © by Gabe Moretti . Chapter 7 is Copyright © by Ken Scott.

The material in ehapters 2 through 4 is not sponsored by International Business Maehines (IBM). IBM makes no warranties regarding the eontents nor use.

Copyrlabt © 1991 Springer Science+Business Media New York Originally published by K1uwer Academic Publishers in 1991 Softcover reprint ofthe hardcover Ist edition 1991

All rights reserved. No part of this publieation may be reprodueed. stored in aretrieval system or transmitted in any form or by any means. mechanieal. photoeopying. reeording. or other­wise. without the prior written permission of the publisher. Springer Science+Business Media, LLC.

Printed on acid-free paper.

This printing is a digital duplication ofthe original edition.

Table of FiguresForewordPreface

Contents

XI

xvxvii

I. Swilch-Level Modeling in VHDL 1Dr. Alec G. 5lallCuiescu

1.1 Introduction I1.I.l Overview 21.1.2 Why Switch-level VHDL Descriptions , 21.1.3 A Switch-level Modeling Solution in VHDL 31.1.4 Choice of Algorilhm: Interpretative YS. Compiled. and Global

YS. Distributed 41.2 Advanced Simulator Programming 6

1.2.1 VHDL Simulation Cycle 61.2.2 Variables vs Signals & Predefined Attributes 81.2.3 Concurrent vs. Sequential Statements 91.2.4 User-defined Packages 91.2.5 User-defined Types 101.2.6 Value-System and Resolulion FuncLions 111.2.7 Properties of ResoluLion FuncLions 14

1.3 Switch-Level Package 151.3.1 46-value System 161.3.2 Functional Support for the 46-value System 18

1.4 Distributed Algorithm for Pass-transistor 221.4.1 Modeling Assumptions 221.4.2 Overview of Algorilhm 231.4.3 Completion of Distributed Algorithm 26

1.5 VHDL ImplementaLion of Distributed Algorithm 291.6 Examples of Switch-level Nelworks 33

1.6.1 One-bit RAM 331.6.2 Memory Cell based on two Inverters 341.6.31,2,4 and 6-biladders 351.6.4 Performance of VHDL Switch-level simulation 38

vi Applications of VHDL to Circuit Design

1.7 Future Research , 391.7.1 Transislor-network PaUem Recognition 391.7.2 More Complex Value-System 391.7.3 Hardwired Implementations , 391.7.4 Analog Models in VHDL 40

1.8 Conclusion 401.9 References 40

2. Modeling of Transmission Line Effects in Digital Circuits 43Balsha R. Sianisic

2.1 Introduction 432.2 Underlying Concepts and Structure 44

2.2.1 Superposition 442.2.2 Idemifying and StruclUring Modeling Information 452.2.3 General Model Structure 48

2.3 Behavioral Models ,.,.,., , ,. 492.3.1 Lossless Transmission Line , ,.,.,., , ,.,., , , , 502.3.2 Receiver ,., ,.,.,.,.,., , ,., , ,.,., 552.3.3 Linear Driver , , , , ,. 572.3.4 General Driver ,., ,.,., ,.,., , ,. 60

2.4 Application of Transmission Line Behaviors 632.4.1 FET Modeling with the General Driver Model 632.4.2 Network Example 672.4.3 Simulation Results ,., , , ,., , ,., , 692.4.4 Limitations and Usage .. ,.,.,.,., ,.,., , , , ,.,. 69

2.5 Summary , , , ,.,.,., , ,.'., ,., 71References .. , , , ,.,., ,.,., , , ,., ,.,., ,.,., , 71

3, Behavior Modeling of Mixed Analog·Digital Circuits 73Balsha R. Sianisic and Mark W. Brown

3.1 Introduction ,.,.,., , ,., , ,., , , , 743.2 Simulation Model ,.,., , ,., ,.,., ,., , , 75

3.2.1 Theory 753,2.2 General Model Structure 783.2,3 Application to Circuits 79

3.3 Design Verification Methodology 863.3,1 Step I: Cell Level 863.3.2 Step 2: Chip Level 88

3.4 Application of Analog-Digital Behaviors , 893.4.1 Function Generator Model 89

Contents vii

3.4.2 Receiver Model 913.4.3 Network Example 923.4.4 Simulation Results 933.4.5 Limitations 953.4.6 Model Usage 95

3.5 Summary 96References 97

4. Modeling of Analog-Digital Loops in VHDL .................................................•.... 99BafsJuJ R. Slanisic

4.1 Introduction 994.2 AGe Loop Behavioral Models 100

4.2.1 Variable Gain Amplifier 1014.2.2 Envelope Detector 1034.2.3 Integrating Capacitor 105

4.3 Application of Automatic Gain Control Loops 1064.3.1 Network Example 1064.3.2 Simulation Results 109

4.4 Phase-Locked Loop Behavioral Models 1094.4.1 SingleShol 1104.4.2 Phase I Frequency Deleclor III4.4.3 Charge Pump 1134.4.4 Second-Order Filler 1154.4.5 Voltage Controlled OscillaLOr 117

4.5 Application of Phase-Locked Loop 1194.5.1 Nelwork Example 1194.5.2 Simulation Results 1214.5.3 Limitations and Usage 122

4.6 Summary 122References 122

5. Modeling Style Issues for Synthesis 123Ste...e Carlson

5.1 What is HDL Synthesis? 1245.2 Applying HDL Synthesis Technology 126

5.2.1 The Synthesis Continuum 1265.2.2 Quality I Productivity Design Automation

Acceptance Criteria 1285.2.3 Practical Considerations 130

5.3 An HOL Symhesis Policy 132

viii Applications of VHDL to Circuit Design

5.3.1 Design Methodology 1325.3.2 Design Style 1335.3.3 Supported Language ConslIUclS 134

5.4 Synthesis of Register Transfer Level ConsU'UcLS 136Concurrent VHDL (136), Vector Types (137), NellisLS andPackages (138). Arithmetic and Relational OperaLOrs (139),Vector Indices (140), If-then-else and Case Statements (141),For Statement (142), SublYpes. Slices. Functions (143), WaitStatement (143), Generate Statement (144), Finite StateMachine (146)

5.5 Synthesis Style Issues in VHDL 1475.5.1 Process Independent Modeling Paradigm 1475.5.2 Synchronous Operation Through Implicit Storage ElemenLS .. 1495.5.3 Partially Asynchronous Operation 1515.5.4 Asynchronous Operation 152

5.6 A Complete Example 1535.7 Closing Remarks 160

6. Modeling of Standard Component Libraries 163Gabe Moretti

6.1 Structure of Model Libraries 1656.2 Relevant Issues in Logic Simulation 1686.3 Layers of Abstraction 1696.4 Independence from Physical Packaging 1746.5 Strength I Level Values Set Independence 1816.6 Independence from Timing Parameter Values 1866.7 Toward a Standard 1926.8 Summary t95

7. Anomalies in VHDL and How 10 Address Them 197Ken Scott

7.t Common Misconceptions about VHDL 1987.1.1 VHDL Processes and Drivers 1987.1.2 Initialization of Signals 201

VHDL Sources and Initialization (203). Multiple-DriverSignal Initialization Example (204), Example with Non-Driver Source Signal Initialization (205)

7.1.3 Working Around the Lack of Global Variables in VHDL ...... 206Use Intermediate Signals (207), Use VHDL Registers (209)

ContenlS ix

7.1.4 Use of 'out' and burrer' Mode PorlS 211Signal Propagation in VHDL (212)

7.1.5 Usc of Bus and Register Signals 2147.1.6 Predefined Signal Attributes 217

Signal Attributes in guarded blocks (218), Simulationefficiency of (2 t 9)

7.2 VHDL Language Inconsistencies 2217.2.1 The Textio Package _................................. 2217.2.2 Spaces in Abstract I Physical Literals 2237.2.3 Null Slices _ 2257.2.4 Slices in Case StatemenlS 2257.2.5 Resolution Function Parameters 226

7.3 Summary 2287.4 References 228

INDEX 229

Table of Figures

1.1 Handling of Unknown 131.2 46-Value System 171.3 One-bit RAM .., 331.4 One-bit RAM - Waveform 341.5 Memory Cell based on two Inverters 351.6 NAND gale as a network of bi-directional Switches 361.7 One-bit adder as a network of NAND gates 361.8 Simulation execution time on an Apollo DN3000-6MB 38

2.1 Basic Summing Bus Resolulion Function 452.2 Transmission Line Data Structure 472.3 General VHDL Model Struclure 482.4 Basic Transmission Line Simulation Models 492.5 Transmission Line Algorithm for directional Node A->B Path 502.6 Transmission line Data Path Flow for Node 1-> 2 512.7 Transmission line Model 532.8 Transmission line Propagate Funclion 542.9 Transmit Voltage Function 542.10 Transmission line Update Current Function 542.11 Receiver Transfer Curve and Block Diagram 552.12 Receiver Model 562.13 Linear Driver Transfer Curve, Block Diagram, and 1- V Curve 572.14 Linear Driver Model 582.15 Linear Driver Function 592.16 General Driver Block Diagram and general I-V Curve 602.17 General Driver Melhod 612.18 General Driver Model of Linear Driver 622.19 Drive...,general Function for General Driver Model 632.20 Gcneral Driver Method for FET N-channel Open-drain Driver 642.21 General Driver Model of FET N-Channel Open-drain Driver 652.22 Drive_fet Function for General Drivcr Model 662.23 Square Rool Function 672.24 FET Driver Example 672.25 FET Network Entity , 68

xii Applications of VHDL to Circuit Design

2.26 FET Driver Example Waveforms 70

3.1 Single Pole Filter Transfer Function Example 773.2 General VHDL Model Structure 793.3 Basic Amplifier Circuit 813.4 Basic Amplifier Model 823.5 RC Low Pass Filter Function 833.6 Basic Analog Data Structure 843.7 Basic Bus Resolution Function for Current Summing 853.8 Step I •• Cell Design Verificalion 863.9 Translated SPICE Description for Amplifier 873.10 Step 2 -- Chip Level Design Verification 883.11 Basic Function Generator Model 903.12 Function Generator Sine Function 913.13 Simplified Hysteresis Receiver Model 923.14 Analog Nelwork Example 923.15 Amplifier Network Entity 933.16 Plot Showing Amplifier Driven at ·3dB Frequency 94

4.1 Basic AGC Loop Simulation Models 1004.2 Variable Gain Amplifier Symbol and Transfer Curve 1014.3 Variable Gain Amplifier Model 1024.4 Variable..,.gain Function for Variable Gain Amplifier 1034.5 Envelope Detector Transfer Curve and Block Diagram 1034.6 Envelope Detector Model , , 1044.7 Integrating Capacitor Block Diagram and I-V Relation 1054.8 Integrating Capacitor Model ,., , , 1054.9 Capf Function for Integrating Capacitor 1064.10 AGe Loop Example 1074.11 AGC Network Entity 1074.12 AGC Loop Example Waveforms 1084.13 Basic PLL Loop Simulation Models ,., 1094.14 Single Shot Block and Timing Diagrams 1104.15 Single Shot Model 1104.16 Phase/Frequency Detector Block and Timing Diagrams 1114.17 Phase!Frequency Detector Model 1124.18 Charge Pump Block and Timing Diagrams 1134.19 Charge Pump Model 1144.20 Second-Order Filter Block Diagram and Transfer Function 1144.21 Second-Order Filter Model 1154.22 Vfof Function for Second·Order Filter 1164.23 VCO Block Diagram and Transfer Curve 116

Table of Figures xiii

4.24 Voltage Controlled Oscillator Model 1174.25 Vco_vcap Timing Capacitor Funclion for VCO 1184.26 Vco_vcapfTiming Capacilor Flag Funclion for VCO 1194.21 PL Loop Example 1204.28 PLL Network Entity 1204.29 PLL Example Waveforms 121

5.1 Synlhesis Defined 1245.2 Synthesis Melhodology 1255.3 Digital Design Process 1215,4 Quality/Produclivity Trade-ofCs 1285.5 HDL Synthesis Quality/Productivily 1295.6 Concurrent VHDL 1365.7 Vector Types 1375.8 NeUists and Packages 1385.9 Arithmetic Operators 1395.10 Relational Operators 1395.11 Vector Indices 1405.12 If-Then-Else 1415.13 Case SlaLCment 1415.14 For SLalCmenl 1425.15 Subtypes, Slices, and Functions 1435.16 Wait StalCmenl 1435.17 Generate Slatement 1445.18 Controlling Optimization 1455.19 Finite State Machine 1465.20 Modeling Paradigm Diagram 1485.21 VHDL Code and Generated Schemalic (implicit storage) 1505.22 VHDL Code and GeneraLed Schematic (two phase clock) 1515.23 VHDL Code and Generaled Schematic (asynchronous reset) 1525.24 Subunits of lhe UART 1535.25 Project Package for UART Design 1545.26 Bidirectional Modeling (for UART) 1555.21 Clock Generation Simulalion Code 1565.28 Code and Schematic for Parallel to Serial Conversion 1575.29 Code and Schematic for Serial-to-Parallel Converter 1595.30 Top Level UART Schematic 159

6.1 Model Execution Control with Package 1726.2 Behavioral Architecture Template 1736.3 Logic Symbol and Corresponding Entily 1776,4 SN54LS86A J Package Pinout 179

xiv Applications of VHDL to Circuit Design

6.5 SN54LS86A FK Package PinOlit 1816.6 Conversion Function 1856.7 Usc of Conversion Functions 1866.8 Support of minltyp/max Timing with Types 1876.9 MINIMAX Delays as a Percentage of Typical Delay VaJue 1886. JO Standard Component Entity Declaratioo 1916.11 Standard Component Instantiation 192

7.1 Procedural Full-Adder Model 1997.2 SlrUctural Full-Adder Model 2007.3 Incorrect Model for a 4·bit Register 2027.4 Correct Model for a 4-bil Register 2037.5 Multiple Drivers Driving Signal 2057.6 Single 'Out' Mode Port Driving Signal 2067.7 Illegal Use of Global Variables 2087.8 Using Intermediale Signals instead of Variables 2097.9 ReSOlution Function for Resolving Registers 2107.10 Using VHDL Registers instead of Variables 2117.11 Using a Temporary Signal 10 Read Driving Value 2147.12 Use of Variable lO Store Driving Value 2157.13 Package Defining Resolution Function for type BIT 2157.14 Using Registers 10 Model the Behavior of a Bus 2167.15 4·bit Register with Asynchronous Reset 2207.16 Ascii format used by package Textio 2227.17 Test Bench for Full Adder from Figure 7.1 2237.18 Stimulus File for Full-Adder 2247.19 Simple Case Statement Example 2267.20 Case Statement Using Slices 227

Foreword

Describing and designing complex electronic systems has become an overwhelmingactivit)' for which VHDL is showing increasingly useful and promising support. Althoughcreated as a description language. VHDL is being increasingly used as a simulatable andsynthcsizablcdcsign language. For the first time, here is a book which describes a numberof unique and powerful ways VHDL can be used to solve typical design problems insystems •• ones which must be designed correctly in vcry short periods of lime. Typicallyuseful lcchniquessuch as switch-level modeling, mixed analog and digital modelling, andadvanced synthesis for which VHDL shows greal promise are fully presented. Thesemeth·ods are bOlh immedial.ely applicable. and indicale lIle potential of VHDL in efficientlymodelling Ihe real world of electronic systems.

Since its inception. there has been adesire for ananalogdescription languageconsistentwith (and integrated with) VHDL. Until recently. VHDL could onl)' be applied to digitalcircuits. ootlhedream ofdescribingand simulating mixed analog and digital circuits is nowa reality as described herein. Describing the functionality of analog circuits includingintetoperability with digital circuits using the VHDL paradigm is surprisingly easy andpowerful. The approach outlined by the authors presages a significant advance in thesimulation of mixed systems.

The efficient automatic design ofdigital circuits is becoming increasingly imponant aswell. Such capabilities are rising from the research and being applied to the industrialenvironment. Challenges still exist. but much is known about how to model systems suchthal efficient synthesis can be done. The approach to synthesis modelling as outlined hereis useful for anyone contemplating using VHDL for synthesis.

Applications of VHDL to Circuit Design

A basic premise of YHDL is to describe digital components consistent throughout alllevels of descriptive abstraction - gates (0 systems. Just as hardware components such asstandard cells, chips, boards, or entire systems are considered as standard component partsfor the construction of new assemblies and systems, there mUSl be a synonymous andconsistent way to describe these parts as reusable components in the YHDL environment.A methodology for constructing VHDL component libraries is presented here.

Finally, VHDL is a recent standard and its problems are becoming increasinglyunderstood. A treatise on what the more significant problems are, and how to work aroundthem, is important for every designer to know. Such a treatise is important for all designersand included in this book.

The authors of this book have attempted, with great success, to present modernmethods, capabilities, and extensions to the already well·known abilities of YHDL to servethe electronic systems industry. This is a book to be devoured, followed, and used by everyelectronic system designer.

Dr. Harold W. CarterUniversity of Cincinnati

Cincinnati, Ohio

Preface

VHDL is an industry standard modeling language for the design and description ofelec­tronic systems. Although intended for digital hardware design, VHDL contains featuresfound in modem programming, hardware description, and C.A.E. design and simulationlanguages. This ricll feature set is allowing the language La be adopted by a largerand morediversified audience than for any other hardware design I description language (HDL). Itis for this audience of users that this book is wriuen.

When the initial idea for this book developed in early 1989, it was envisioned to coverthe complete design space from transistor circuit to queueing theory system models. Itquickly became evident that to do any topic justice required mOfe space and time than wasavailable from a single aulhor. Hence,lhe book expanded to contributedchapters in a seriesofbooks entitled"Applications of VHDL to ... ". This initial book, "Applications ofVHDLto Circuit Design", focuses on circuit modeling and timely topics about VHDL's use in theelectronic design process.

The book series intends to bridge lhe gap between electronic design and the VHDLlanguage standard. Concepts difficult to model in the electronic design process areintroduced with solutions in VHDL. Designers familiar with VHDL can start wilh lheexamples and explore rurlher solutions to their unique problems. Those not familiar withYHDL can adapt lhecomplete examples without a detailed understanding of the language.The book series does not attempt to serve as an introduction to the YHDL language butralher concentrates on providing solutions to real-world modeling problems.

There is real irony in Ihat circuit design is Ihe firstlOPic covered in the book series.When designed in the early 1980's, VHDL was targeted for logic and digital functiondescription only. Techniques in VHDL ofdiscrete-event driven simulation and hierarchi­cal modeling were not perceived as applicable 10 analog and physical circuit models. And

xviii Applications of VHDL to Circuit Design

yetdue 10 lhese features and others, VHDL is being easily adapted tocircuitand mixed levelmodeling.

Along with thecircuitdesign focus, the book introduces the reader to VHDL applicationareas such as synthesis and standard partS libraries. In the editors experience, understand·ing the synthesis of gates from VHDL is the best way for a today's hardware designer tolearn the featuresofVHDL. These application areas will beexpandedon in future volumes.

The closing chapter in the book highlights common misunderstandings in the currentlanguage. The 1992 re·standardization effon underway is the opponunity to correct theseideas and coalesce new ones conceived during language use. You are encouraged to injectany developed knowledge into the standardization process so VHDL will remain atechnically useful standard. Contact the IEEE or the VHDL Users' Group to leam how.

ELECTRONIC DISK SUPPORT (Reprint edition)

To further support and promote the application ofVHDL, the authorshave donated their models from the book into the public domain. Notethat donating models into the public domain has not removed thecopyright thereof. See the notices on the electronic material and atthe front of this book concerning any material printed in this book orcontained on the electronic files originally distributed freely withthe book but now available on the Internet. An electronic copy ofallthe donated VHDL code shown or referenced in the chapters has beencompiled. Kluwer Academic Publishers, in wishing to further supportthe VHDL community, graciously agreed to distribute this electroniccopy on a floppy diskette free ofcharge with each copy of theoriginal printing of the book. Luckily, with today's internet age,the material can now be more easily and reliably distributed via anHTIPIFTP server .Retrieve the files fromhup:llwww,eda,on:lm jsc!appcircyHDLzjporftp:/Iftp,eda,ore/mjsclappcjrcVHDL,zjp See the README file in the ziparchive for infonnation on the contents and file formats. KluwerAcademic Publishers is not supporting the electronic copy of material.

Randy Harr, Los Altos Hills, CA (Jan 2001)

Note thai donating models into the public domain has not removed the copyright thereof. Sec.

the notices on the decuonic disk and at the fronl of !his book concerning any materialprinled in this book 01' contained on !he electronic disk disuibUied freely wi!h the book.

Preface

BECOME A CONTRIBUTOR

As mentioned earlier, thcre will be a series of books entitled "Applications of VHDLto ...... Even if you never considered writing before, this becomes a good opportunity todevelop your ideas in detail for the benefit of othcrs. A single chaptcr is much easier andquicker to develop than a full manuscript. Encouraged are submissions from engineers outin the field applying VHDL to real design problems. If you have interesting ideas on usingVHDL in the design process, then submit a draft outline or manuscript as a proposedchaptcr. Send it to the Editor care-of the before listed address.

As a selected author, you will retain copyrightlO any material you contribute and sharein the success of its publication. Authors should expect to eventually develop a final,camera ready copy of their material in the same style and format as this work. Don't delay;submit today!

ACKNOWLEDGEMENTS

Any undertaking of a large amount of written material takes the dedication and help ofmany people. Without their invaluable assistance such projects never come to fruition.Therefore, theeditorand authors wish to recognize the people who played an important rolein bringing this work to print.

Randy Harr wishes to thank the authors for their patience and understanding during lheextended period over which this work developed. Many thanks to Carl Harris of Kluwerwho has been extremely patient and supportive during this process. Personal support fromhis wife Roshan during the many hours of work has been greatly appreciated. Checkingfinal copy on their honeymoon was definitely an early test of "in good times and in bad".Credit is due Alec Stanculescu for helping promote the idea of the book and assisting withthe development. For his additional work he is merited with being listed as Co-editor onthe cover. Many thanks to "Bob" Stanisic who arrived with more chapters just as olherauthors were late with their material! Look for more work from this promising youngauthor in the future.

Alec Stanculescu wishes to thank Andy Tsay, Alex Z3mfirescu, and Doug PelTY whocontributed to [9] and [IOl--the basis for his chapter. Many thanks to Vantage AnalysisSystems for placing the 46-value system and the accompanying package in the publicdomain. Finally, thanks to all the Vantage employees, and to David Coelho and RickLazansky in particular, for their constant support.

Bob Stanisic wishes to thank his wife Margie for the support and patience during thelong hours of work. Bob and Mark wish to thank Larry F. Saunders and RobertL. Hedman

Applications of VHDL to Circuit Design

for reviewing their work.

Steve Carlson writes that ''the development of [his] material was a uue team effort.Many of the ideas and examples presented come from the core of the Synopsys VHDL[synthesis] product development leam. Many thanks to those team members: Bill Krieger,Russ Segal, BrentGregory, Jerry Huth. and Emil Girczyc. Tbediligenceofthe manyothcrsfrom lhe Synopsys team who participated in early reviews is greatly appreciated. Specialthanks areexlCndcd to Janet Greene who proved to be tireless in handling the revisions andlayout of the work."

Gabe Moretii wishes to thank Vantage Analysis Systems, Inc. for providing their VHDLSprcadsheel environment; and to extend thanks to Gary L. Mullin for typesetting themanuscript.

Last. but by no means least. Ken Scou wishes to acknowledge Synopsys for support ofhis work. Also. he extends thanks to Brent Gregory who provided detailed feedback on anear·final draft. Finally, he wishes to acknowledge his wife. Shelly. who has been veryunderstanding and supportive throughout the effort.

Finally, thanks to you the thousands of electronic system developers out there whoconstantly challenge old methods in hopes of expanding the frontiers of the electronicdesign process.

Randolph E. HanSan Francisco. California

APPLICATIONS OF VHDL TO CIRCUIT DESIGN