array-structured memory architecture read-write memories (ram)

1

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Lec 21: April 6, 2017 Memory Overview, Memory Periphery

Penn ESE 570 Spring 2017 – Khanna

Today

!  Review "  Memory core

"  SRAM "  DRAM

!  Periphery !  Serial Access Memories

2 Penn ESE 570 Spring 2017 - Khanna

Array-Structured Memory Architecture

Input-Output(M bits)

Row

Dec

oder

AK

AK+1

AL-1

2L-K

Column Decoder

Bit Line

Word Line

A0

AK-1

Storage Cell

Sense Amplifiers / Drivers

M.2K

Problem: ASPECT RATIO or HEIGHT >> WIDTH

Amplify swing torail-to-rail amplitude

Selects appropriateword

Penn ESE 570 Spring 2017 - Khanna

Read-Write Memories (RAM)

!  Static (SRAM) "  Data stored as long as supply is applied "  Large (6 transistors/cell "  Fast "  Differential

!  Dynamic (DRAM) "  Periodic refresh required "  Small (1-3 transistors/cell) "  Slower "  Single ended


6T SRAM Cell

!  Cell size accounts for most of memory array size !  6T SRAM Cell

"  Used in most commercial chips "  Data stored in cross-coupled inverters

!  Read: "  Precharge BL, BL’ "  Raise WL

!  Write: "  Drive data onto BL, BL’ "  Raise WL

5

bit bit_b

word

BL BL’ WL


6-transistor CMOS SRAM Cell

WL

BL

V DD

M 5 M 6 M 4

M 1

M 2

M 3 BL

Q Q


2

CMOS SRAM Analysis (Read)

VDD

Q = 1Q = 0

M1

M4

M5

BL

WL

BL

M6

VDD VDDVDD

CbitCbit

kn M5,

2---------------

VDD2

------------ VTnVDD

2------------⎝ ⎠⎛ ⎞–⎝ ⎠

⎛ ⎞2

kn M1, VDD VTn–( )VDD

2------------

VDD2

8------------–⎝ ⎠

⎛ ⎞=

(W/L)n,M5 ≤ 10 (W/L)n,M1 (supercedes read constraint)


1

VDD VDD

0

kn,M5 VDD − ΔV −VTn( )2= kn,M1 (VDD −VTn)ΔV −

ΔV 2

2

⎛

⎝⎜⎜

⎞

⎠⎟⎟

VDD


VDD

Q = 1Q = 0

M1

M4

M5

BL

WL

BL

M6

VDD VDDVDD

CbitCbit

kn M5,

2---------------

VDD2

------------ VTnVDD

2------------⎝ ⎠⎛ ⎞–⎝ ⎠

⎛ ⎞2


2------------

VDD2

8------------–⎝ ⎠

⎛ ⎞=

(W/L)n,M5 ≤ 10 (W/L)n,M1 (supercedes read constraint)


1

VDD VDD

0

kn,M5kn,M1

=

WL

⎛

⎝⎜

⎞

⎠⎟5

WL

⎛

⎝⎜

⎞

⎠⎟1

=(VDD −VTn)ΔV −

ΔV 2

2VDD − ΔV −VTn( )

2

WL

⎛

⎝⎜

⎞

⎠⎟5

WL

⎛

⎝⎜

⎞

⎠⎟1

=(VDD −1.5VTn)VTnVDD − 2VTn( )

2

ΔV =VTn

VDD


WL BL

V DD M 5 M 6

M 4

M 1 V DD V DD V DD

BL Q = 1 Q = 0

C bit C bit



0 0

0.2 0.4 0.6 0.8

1 1.2

0.5 1 1.2 1.5 2 Cell Ratio (CR)

2.5 3

Volta

ge R

ise

(V)


CMOS SRAM Analysis (Write)

VDD

Q = 1Q = 0

M1

M4

M5

BL = 1

WL

BL = 0

M6

VDD


2----------- VDD

2

8-----------–⎝ ⎠

⎛ ⎞ kp M4, VDD VTp–( )VDD

2----------- VDD

2

8-----------–⎝ ⎠

⎛ ⎞=

kn M5,

2-------------- VDD

2----------- VTn

VDD

2-----------⎝ ⎠⎛ ⎞–⎝ ⎠

⎛ ⎞2

kn M1, VDD VTn–( )V DD

2----------- VDD

2

8-----------–⎝ ⎠

⎛ ⎞= (W/L)n,M5 ≥ 10 (W/L)n,M1

(W/L)n,M6 ≥ 0.33 (W/L)p,M4


1

0 VDD

0

kn,M6 VDD −VTn( )2= kn,M4 (VDD −VTp)VQ −

VQ2

2

⎛

⎝⎜⎜

⎞

⎠⎟⎟

VDD


VDD

Q = 1Q = 0

M1

M4

M5

BL = 1

WL

BL = 0

M6

VDD


2----------- VDD

2

8-----------–⎝ ⎠

⎛ ⎞ kp M4, VDD VTp–( )VDD

2----------- VDD

2

8-----------–⎝ ⎠

⎛ ⎞=

kn M5,

2-------------- VDD

2----------- VTn

VDD

2-----------⎝ ⎠⎛ ⎞–⎝ ⎠

⎛ ⎞2

kn M1, VDD VTn–( )V DD

2----------- VDD

2

8-----------–⎝ ⎠

⎛ ⎞= (W/L)n,M5 ≥ 10 (W/L)n,M1

(W/L)n,M6 ≥ 0.33 (W/L)p,M4


1

0 VDD

0

kn,M4kn,M6

=VDD −VTn( )

2

(VDD −VTp)VTn −VTn2

2

PR =W4 L4W6 L6

kn,M4kn,M6

=VDD −VTn( )

2

(VDD −VTp)VQ −VQ2

2

VQ =VTn

VDD

3


BL = 1 BL = 0

Q = 0 Q = 1

M 1

M 4 M 5 M 6

V DD

V DD WL

PR =W4 L4W6 L6



PR =W4 L4W6 L6


DRAM

!  Smaller than SRAM !  Require data refresh to compensate for leakage

15 Penn ESE 570 Spring 2017 – Khanna

3-Transistor DRAM Cell

M2M1

BL1

WWL

BL2

M3

RWL

CS

X

WWL

RWL

X

BL1

BL2

VDD-VT

ΔV

VDD

VDD-VT

No constraints on device ratiosReads are non-destructiveValue stored at node X when writing a “1” = VWWL-VTn


1-Transistor DRAM Cell

CSM1

BL

WL

CBL

WL

X

BL

VDD−VT

VDD/2

VDD

GND

Write "1" Read "1"

sensingVDD/2

ΔV VBL VPRE– VBIT VPRE–( )CS

CS CBL+------------------------= =

Write: CS is charged or discharged by asserting WL and BL.Read: Charge redistribution takes places between bit line and storage capacitance

Voltage swing is small; typically around 250 mV.


Memory Periphery


4

Array Architecture

!  2n words of 2m bits each !  Good regularity – easy to design !  Very high density if good cells are

used


Array Architecture


used


Array Architecture


used


Array Architecture


used


Decoders


Decoders

!  n:2n decoder consists of 2n n-input AND gates "  One output needed for each row of memory "  Build AND from NAND or NOR gates

Static CMOS

24

word

A0

A1

11

11

4

8word0

word1

word2

word3

A0A1


5

Large Decoders

!  For n > 4, NAND gates become slow "  Break large gates into multiple smaller gates

25

word0

word1

word2

word3

word15

A0A1A2A3


Predecoding

!  Many of these gates are redundant "  Factor out common

gates into predecoder "  Saves area "  Same path effort

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A0

A1

A2

A3

word1

word2

word3

word15

word0

1 of 4 hotpredecoded lines

predecoders


Row Select: Precharge NAND


Row Select: Precharge NOR


Column Circuitry

& Bit-line Conditioning


Array Architecture


used


6

Column Circuitry

!  Some circuitry is required for each column "  Bitline conditioning

"  Precharging "  Driving input data to bitline

"  Sense amplifiers "  Column multiplexing (AKA Column Decoders)


Bitline Conditioning

!  Precharge bitlines high before reads

32

φbit bit_b


BL BL’



33

φbit bit_b


BL BL’



!  What if pre-charged to Vdd/2? "  Pros: reduces read-upset "  Challenge: generate Vdd/2 voltage on chip

34

φbit bit_b


BL BL’

Voltage Midpoint Reference Generator

!  The inverter with input and output tied together settles to the midpoint of the transfer curve where the input and output are equal

!  The second inverter is driven to the same point. It helps isolate the output from the reference. The pass gate allows you to connect or disconnect this reference voltage to a node.


Sense Amplifiers

!  Bitlines have many cells attached "  Ex: 32-kbit SRAM has 128 rows x 256 cols "  128 cells on each bitline

!  tpd ∝ (C/I) ΔV "  Even with shared diffusion contacts, 64C of diffusion

capacitance (big C) "  Discharged slowly through small transistors in each

memory cell (small I)

!  Sense amplifiers are triggered on small voltage swing (ΔV)


V(0) t

VPRE

V BL

Sense amp activated Word line activated

V(1)

ΔV

7

Differential Pair Amp

!  Differential pair requires no clock !  But always dissipates static power

37

bit bit_bsense_b sense

N1 N2

N3

P1 P2


BL BL’

Clocked Sense Amp

!  Clocked sense amp saves power !  Requires sense_clk after enough bitline swing !  Isolation transistors cut off large bitline capacitance

38

bit_bbit

sense sense_b

sense_clk isolationtransistors

regenerativefeedback


SRAM Read Circuit

39

Kenneth R. Laker, University of Pennsylvania,

updated 02Apr15

MP2

M2 WBWB

MA2

MA4 MA5

MA1 MA3

VNOT-C VC

Differential Sense Amplifier (one per column)

Sense Amp Gain:

Read Select

φS


SRAM Read Circuit

40

Kenneth R. Laker, University of Pennsylvania,

updated 02Apr15

MP2

M2 WBWB

MA2

MA4 MA5

MA1 MA3

VNOT-C VC

Differential Sense Amplifier (one per column)

Sense Amp Gain:

Read Select

φS


SRAM Write Circuit

41

W DATA WB WB OPERATION (M3 ON)

WRITE CKT

(1)

(0)

(0) (0)

(0)


SRAM Write Circuit

42

(1)

(0)

(0)

(1)

(0)

W DATA WB WB OPERATION (M3 ON)

WRITE CKT

(1)


8

Array Architecture Details


Column Drivers: Memory Bank


Tristate Buffer

!  Typically used for signal traveling, e.g. bus !  Ideally all devices connected to a bus should be

disconnected except for active device reading or writing to bus

!  Use high-impedance state to simulate disconnecting

45

Input Output

En Input En Ouptut

0 0 Z

1 0 Z

0 1 0

1 1 1 Active-high buffer


Tristate Buffer

46

Input Output

En

Input Output

En

Output

En

En Input

Vdd

CMOS circuit


Tristate Inverters


Output

En

Input

Output

En

Input

8x4 Memory with column decoder

48

1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit




0

1

2

3

8x4 Memory 2-to-4

Decoder

Row

Decoder

A0

A1

1-to-2 Decoder Column Decoder

D0 D1 D2 D3

Tristate Buffer (read)

0 1

A0

Column Select CS


(A2)

9

Read/Write Memory

49





0

1

2

3

8x4 Memory

2-to-4 Row

Decoder

1-to-2 Column Decoder 0 1

A0

CS

Rd/Wr

D0 D1 D2 D3


A0

A1

Column Select

(A2)

Read/Write Memory

50





0

1

2

3

8x4 Memory

2-to-4 Row

Decoder


A0

CS

Rd/Wr = 0

D0 D1 D2 D3


A0

A1

Column Select

(A2) = 0

Read/Write Memory

51





0

1

2

3

8x4 Memory

2-to-4 Row

Decoder


A0

CS

Rd/Wr = 1

D0 D1 D2 D3


A0

A1

Column Select

(A2) = 1

Serial Access Memories


Serial Access Memories

!  Serial access memories do not use an address "  Shift Registers "  Serial In Parallel Out (SIPO) "  Parallel In Serial Out (PISO) "  Queues (FIFO, LIFO)


Shift Register

!  Shift registers store and delay data !  Simple design: cascade of registers

54

clk

Din Dout8


10

Denser Shift Registers

!  Flip-flops aren’t very area-efficient !  For large shift registers, keep data in SRAM instead !  Move read/write pointers to RAM rather than data

"  Initialize read address to first entry, write to last "  Increment address on each cycle

55

Din

Dout

clk

counter counter

reset

00...00

11...11

readaddr

writeaddr

dual-portedSRAM


Serial In Parallel Out

!  1-bit shift register reads in serial data "  After N steps, presents N-bit parallel output

56

clk

P0 P1 P2 P3

Sin


Parallel In Serial Out

!  Load all N bits in parallel when shift = 0 "  Then shift one bit out per cycle

57

clkshift/load

P0 P1 P2 P3

Sout


Queues

!  Queues allow data to be read and written at different rates.

!  Read and write each use their own clock, data !  Queue indicates whether it is full or empty !  Build with SRAM and read/write counters

(pointers)

58

Queue

WriteClk

WriteData

FULL

ReadClk

ReadData

EMPTY


FIFO, LIFO Queues

!  First In First Out (FIFO) "  Initialize read and write pointers to first element "  Queue is EMPTY "  On write, increment write pointer "  If write almost catches read, Queue is FULL "  On read, increment read pointer

!  Last In First Out (LIFO) "  Also called a stack "  Use a single stack pointer for read and write


Ideas

!  Minimize area of repeated cell !  Compensate with periphery

"  Amplification (regeneration/restoration)

!  Match periphery pitch to cell row/column "  Decoders "  Column Circuitry

"  Bitline Precharge "  Bit Line Drivers (write circuitry) "  Sense Amplifiers

Penn ESE 570 Spring 2017 – Khanna 60

11

Admin

!  HW 7 and HW 7 EC due 4/9

!  Final Project "  Teams of up to 2 people

"  Don’t work alone! Start ASAP! "  Report your teams to me by midnight tonight!

"  Design memory (SRAM) "  EC for best figure of merits (FOM = Area*Power*Delay2)

"  # of points depends on teams reported

"  Can propose extra work for extra credit

"  Due 4/25 (last day of class) "  Everyone gets an extension until 5/3 (day of final exam)

"  Absolutely doable by 2 people by 4/25


Final Project Schedule

!  Posted now !  April 6th – report teams to instructor !  April 18th – extra credit proposals due to instructor !  April 25th – final report due

"  Must be submitted via Canvas

!  May 3rd – extension for reports (also day of final)

!  All deadline times are midnight that day

Penn ESE 570 Spring 2017 – Khanna 62

array-structured memory architecture read-write memories (ram)

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