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A 7 GHz compact transimpedance amplifier TIA in CMOS0.18 lm technology

Jawdat Abu-Taha1 • Metin Yazgi1

Received: 30 June 2015 / Revised: 28 December 2015 / Accepted: 2 January 2016/ Published online: 13 January 2016

Springer Science+Business Media New York 2016

Abstract This paper describes a compact transimpedance

amplifier (TIA). Based on the principle of negative impe-dance (NI) circuit, the proposed TIA provides wide band-

width and low noise. The schematics and characteristics of

NI circuit have been explained. The inductor behavior is

synthesized by gyrator-C circuit. The TIA is implemented

in 180 nm RF MOS transistors in a HV CMOS technology

with 1.8 V supply voltage technology. It reaches -3 dB

bandwidth of 7 GHz and transimpedance gain of 54.3 dBX

in the presence of a 50 fF photodiode capacitance. The

simulated input referred noise current spectral density is

5:9 pA/

ffiffiffiffiffiffiHz

p . The power consumption is 29 mW. The TIA

occupies 230 lm

45 lm of area.

Keywords Transimpedance amplifier (TIA) Negativeimpedance (NI) circuit Active inductor (AI) Input-referred noise I 2in

Bandwidth extension

1 Introduction

In the receiver of optical communication system, the

transimpedance amplifier (TIA) is the first electrical

building block that converts the induced photodiode (PD)

current into a large voltage signal to be used in the digitalprocessing unit.

TIA is required to have high gain and wide bandwidth at

the same time with low power dissipation.It is well known that, the main challenge to implement

wideband TIA lies in the large photodiode parasitic

capacitance at the input node that deteriorate the perfor-

mance of the complete receiver system such as speed,

sensitivity, and signal-to-noise ratio. Hence, it is necessary

for VLSI designers to improve original circuit approach in

order to reduce the input parasitic effects and to better

enhance the performance in bandwidth, gain, noise, and

power consumption [1].

To obtain high gain, cascode amplifier configuration is

not appropriate in low power due to small voltage swings.

Moreover, a multistage amplifiers suffer from stability

issue because of the existence of multiple poles [2].

There are several works that have been reported to

improve the bandwidth of TIA. Inductive peaking has been

extensively used to improve the bandwidth and decrease

parasitic capacitance effects [3, 4]. Moreover to overcome

this drawback, a bandwidth enhan cement technique using

parallel sections of series-peaked stages is described in [5].

However, an extreme size of the inductor makes the chip

large and costly. An inductorless regulated cascode (RGC)

topology reported in [1] decreases the input impedance of

the TIA, therefore improving the bandwidth. Another

approach in [6] used several shunt feedback TIAs in par-

allel in order to enhance the bandwidth. In that method,

there is a strict trade-off between the number of stages and

step-response damping ratio. The effect of the photodiode

capacitance can be more professionally reduced from the

bandwidth limitation by using regulated cascode (RGC) in

[7–9].

Furthermore, a negative capacitance circuit can be used

to decrease critical node capacitance to improve the

bandwidth of the amplifier. In this paper, the design and

& Jawdat Abu-Taha

[email protected]; [email protected]

Metin Yazgi

[email protected]

1 Department of Electrical & Electronics Engineering, Istanbul

Technical University, Maslak, Istanbul, Turkey

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Analog Integr Circ Sig Process (2016) 86:429–438

DOI 10.1007/s10470-016-0689-1

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simulation results of 7 GHz transimpedance amplifier is

presented using 180 nm CMOS technology. A negative

impedance (NI) configuration is used as compensation

circuit to enhance the frequency response of the TIA.

This paper is organized as follows. Section 2 discuss the

basic principle of negative impedance (NI) circuit and

illustrates a technique to improve the bandwidth. An

implementation of CMOS transimpedance amplifier as adesign example follows in Sect. 3. The mathematical

model for illustrating the noise of the proposed TIA is

introduced in Sect. 4. The simulation results are shown in

Sect. 5 and finally conclusions are summarized in Sect. 6.

2 Principle of cegative impedance (Ni) circuit

Merits for using transimpedance amplifier (TIA) comprise

its ability to provide a high transimpedance gain with wide

bandwidth. TIA can be designed as a single ended voltage

amplifier with a feedback resistor RF . Figure 1 demon-strates the block diagram of the proposed transimpedance

amplifier (TIA). Since a photodiode operates as current

source, it can be replaced by a current source I in in parallel

with the photodiode capacitance C pd .

Using Miller effect, if we assume that Rout RF and Rout C out þ C F ð Þ RF C in then, it can be shown easily thatthe simplified expression of transimpedance gain Z T is

given as:

Z T ¼ V out I in

RF 1 þ s RF C in

A 1 þ s Rout C out ð Þð1Þ

where A is the amplifier gain, RF is the feedback resistor,

C in is the total input capacitance that includes the photo-

diode’s capacitance C pd , the input capacitance of the

amplifier C g and feedback parasitic capacitance C F ð1 AÞ.The output capacitance of C out is sum of the amplifier

output capacitance and the feedback parasitic capacitance

C F ð1 1= AÞ.

The transimpedance gain at low frequencies ð Z dcÞ equals RF for high value of A and small value of Rout : As shown inEq. 1, the transimpedance gain function have two real

poles P1 and P2 that are given as:

P1;in ¼ A RF C in

P2;out ¼ 1

Rout C out

ð2Þ

Due to high capacitance of the photodiode capacitance

C pd ; the total input capacitance C in is larger than the total

output capacitance C out . Besides, feedback resistor RF is

larger than the output resistance Rout . Hence, the dominant

pole is suited on the input node and the output pole can be

located at a sufficiently higher frequency than the input pole.

From 2, the bandwidth can be improved by increasing

the gain A ¼ gm Rout ð Þ and by maintaining the same timeconstant at the output pole.

A better gain A can be obtained if the output resistance

Rout is increased. Increasing Rout can be done by placing anegative resistance R IN in parallel with the output resis-

tance Rout . In order to maintain the same time constant at

the output node, a negative capacitance can be used.

Increasing the gain A effectively decreases the input

resistance and hence increase the frequency of the input

pole. As a result, an improvement of the bandwidth can be

obtained.

As shown in Fig. 1, a first-order amplifier with a nega-

tive impedance (NI) circuit is created at the output node.

Both the equivalent output resistance R0out and equivalent

output capacitance C 0out are given as:

R0out ¼ R NIC Rout

R NIC Rout :C 0out ¼ C out C NIC :

ð3Þ

Equation 3 shows that output capacitance C 0out becomes

smaller than C out and the output resistance R0out becomes

greater than Rout . This leads to increase in the voltage gain

A ¼ gm R0out , which reduces the input resistance at the inputnode, while the time constant at the output node remains

approximately the same.

For stability, the pole must be in the left half-plane when

choosing the value of R NI to be larger than Rout andC NI \C out . NI circuit could be realized by adding active

circuit to output node.

From the point of theory, this technique could be applied

at the input node also. When placing the negative impe-

dance components at the input node, the input resistor

increases and the input capacitance decreases. The large

photodiode capacitance still limits the bandwidth because

the value of the negative capacitance does not provide the

effective reduction of the input capacitance to expand the

C F

F

C pd out

I in

R out,C out

Z in

Photo - diode Transimpedance amplifier

Negative Impedance Circuit NIC

CINCRINC

Fig. 1 Block diagram for the traditional resistive feedback TIA with

NIC

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Im Z inf g ¼ x L s 1xC gs1

gm1 RsxC gs1

xC gs2g2m2 þ x2C 2gs2

þ gm1gm2 x C gs1

g2m2 þ x2C 2gs2:

ð9Þ

Assuming that both transistors have identical transcon-

ductance gm1

¼ gm2

ð Þ, x2 L sC gs1

1 and x2C 2gs

g2m, then

Im Z inf g can be simplified as:Im Z inf g 1

xC gs1x L sC gs1 gm1 Rs 1

xC gs1:

ð10ÞFigure 4 shows the plots of the real and the imaginary

components of the negative impedance (NI) circuit. From

the simulation results, we see that the real part represents a

negative resistance that varies with the frequency. The NI

circuit provides an enough negative resistance at frequen-

cies up to 7 GHz. The imaginary component acts as a

negative capacitance. Figure 5 illustrates the variation of

the capacitance value over the frequency capacitance value

at the frequency of 7 GHz as -5 fF.

3 Configuration of the proposed tia with negative

impedance circuit

The simplified diagram of the proposed transimpedance

amplifier (TIA) is shown in Fig. 6. It is a single-ended

design including NMOS transistor M x, feedback resistor RF connecting the output to the input in order to decrease the

dominant effect of the input pole, and negative impedance

(NI) circuit. The output of TIA is taken at the drain of

transistor M x. In the proposed TIA, between the drain

capacitance of M x and the gate capacitance of M 1, a small

series inductor L 1 can improve the bandwidth further.

3.1 Active inductor (AI)

CMOS active inductors (AIs) have become a very popular

research topic recently due to several advantages over

passive inductors. AIs can be realized with circuits that

occupy small chip area. Moreover AIs have a large and

variable inductance and high quality factor. On the other

hand, AIs however have some major drawbacks compared

Fig. 4 The real and the imaginary components of the input

impedance of Z NI

Fig. 5 Variation of NIC capacitance over the frequency

Fig. 6 A proposed circuit digram of the TIA


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to spiral inductors such as poor noise performance, and

small dynamic range, nonlinear behaviour, dc power dis-

sipation, sensitivity to process, and voltage and tempera-

ture variations. The bandwidth extension topologies

commonly use on-chip inductors to compensate the

capacitance effects but their associated hardware cost is

very high. As a result, decreasing the area of required

inductors for a TIA design is very important.Most AIs reported in [12–17] were based on the

knowledge of gyrator-C topology. As we need to design a

floating active inductors to implement the negative

admittance circuit (NI), the architecture of active inductors

in [18, 19] could be used to obtain several nH of inductance

operating at a few GHz region as shown in Fig. 7.

The gyrator is implemented by connection of two dif-

ferential transconductance amplifiers back to back. The

cross coupled NMOS transistors (M7 and M8) provide a

negative resistance to reducing the total series resistance of

the active inductor network which provides a high quality

factor Q of the active inductor. For simplicity, the circuitcan be separated into two identical half-circuit. Fig-

ure 8(a) displays the small-signal equivalent circuit of half-

circuit [20].

The input impedance can by simplified as:

Z AIin

¼ 2 g2 þ sC 2s2C 1C 2 þ s g1C 2 þ sðg1C 2 þ g2C 1ð Þ þ gm1gm2g1g2

ð11Þwhere C1 and C2 are the total capacitance of the drain

nodes, g1 and g2 are the total conductance at the drain

nodes [20].

Figure 8(b) shows the simplified model of the active

inductor. The elements value L, R, G, and C can be cal-

culated thus:

L ¼ 2C 2gm1gm2

; R ¼ 2g2gm1gm2

; G ¼ g12

; C ¼ C 12

: ð12Þ

Equation 12 shows that the desired inductance value can

be obtained by decreasing gm1 and gm2 or increasing C2.

4 Noise analysis of transimpedance amplifier

The proper characterization of noise of the TIA is important

for the receiver due to the small current of the photodiode.

Replacing the passive inductors by active elements produce

some noise in the response of the proposed TIA. So, in order

to operate at high sensitivity, the noise level must be very

small [21]. The main noise sources of the TIA are the thermal

noise of the resistor, the noise of MOS transistor and the

flicker that can be neglected because it is not dominant.

Both the transistor and resistor noise models are shown

in Fig. 9, where v 2 ng ¼ i 2 nd

g 2 m: Both noises sources of the gate

and the source can be modeled by shunt current source with

noise powers of i 2 ng ¼ 4k BT dD f x2C 2gs

.5gd 0

and i 2 nd ¼

4k BT cgd 0D f , respectively, where T is the temperature

(Kelvin), c is the bias dependent factor, k B is the Boltz-

mann’s constant (Joule/ Kelvin), C gs is the gate-source

capacitance, d is the gate noise factor and g d0 is the zerobias of transconductance of the transistor [22, 23].

From the TIA circuit in Fig. 6, the equivalent input

referred current noise of Mx is given as:

i2ngx ¼ 2qk B I Gx þ x2C 2gsxv2ngx: ð13Þwhere q is the electron charge, I Gx is the gate induced

current that can be neglected and v2ngx is given as:

Fig. 7 Circuit schematic of floating active inductor

Fig. 8 a Equivalent small-signal of half-circuit of Floating active

inductor b Simplified model of active inductor

+-

2

nd i

M 2

Ri R

2

ng v

2

ng i

D

S S

G

(a) (b)

Fig. 9 a Noise model of MOS transistor b Noise model of a resistor

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v2ngx ¼i2ngx

g2mx¼ i

2 RF þ i2nx þ i2ngL 1 þ

v2ngv2ngx R

þ i2inL 1g2mx

ð14Þ

where i2inL 1 is the equivalent input noise of active inductor

L1. The simplified expression of the equivalent input noise

of active inductor L1 can be written as:

i2nL 1 ¼ 2i2gn þ 2i2dn þ 2i2dp þ 2g2mpv2gpþ g2mn Z 2gn 2i2gn þ 2i2dn þ 2i2dp þ 2g2mnv2gn þ 2g2mpv2gp

n o¼ 2i2gn 1 þ g2mn Z 2gn

þ 2i2dn 1 þ g2mn Z 2gn

þ 2i2dp 1 þ g2mn Z 2gn

þ 2g4mnv2gn Z 2gn þ 2g2mpv2gp 1 þ g2mn Z 2gn

:

ð15ÞNote that Z 2gn ¼ 1x2C 2gsn [24], then the input noise of serial

active indcuctor ( I 2nLs) is derived as:

i2nL 1 ¼ 8KT D f 1 þ g2

mn

x2C 2gsn

! dnx2C 2gsn

5gd 0n þ cngd 0n

þc pgd 0 p þ d pg2mp

5gdop

8>>>>>>>:9>>>>=>>>>;

þ 8K D f d p g4mn

5gdopx2C 2gsn

:

ð16Þ

then total input noise: ( I 2in;total) becomes:

i2in;total ¼ i2nf þ i2nL 1 þ 1

R2 f þ x2C 2in

!v2ngx: ð17Þ

where i2nf is the thermal noise of diode resistance R f which

is given by:

i2nf ¼ 4k BT

R f : ð18Þ

Substituting Eqs. 14, 15, 16, 18 into Eq. 17, the simplified

expression of total input noise: ( I 2in;total) can be written as:

i2in;total ¼ 4k BT

R f þ 1

g2mx

1

R2 f þx2C 2in

!

4k BT

RF þ k Bcgd 0Df þ 4k BT dDf x2C 2gs

5gd 0(

þ 8k BT Df 1 þ g2mn

x2C 2gsn

!

dnx2C 2gsn

5gd 0þ cngd 0n þ c pgd 0 p þ d p

g2mp

5gd 0f x2C 2gs

5gd 0

!

þ 8k BT d pDf g4mn

5gd 0x2C 2gsn

): ð19Þ

As seen in Eq. 19, the total noise can be minimized by

choosing R f ; gmx to be as large as possible. Improving gmxcan be done by increasing bias current or expanding the

aspect ratio W/L of the transistor. High power consumption

is induced when bias current increases. Moreover, using a

large transistor aspect ratio increases the capacitance

C gs

and C gsn

which generates more noise. As a result, we

have to select the proper ratio W/L and bias current to

optimize the noise performance.

5 Simulation results

In order to evaluate the performance of the proposed TIA

as shown in Fig. 10, the TIA was implemented using

180 nm RF MOS transistors in a HV CMOS process

technology. All post layout simulation results have been

performed by using cadence software tools.

Figure 11 shows the simulated transimpedance gainversus frequency for 50 fF photodiode capacitance for the

proposed TIA with and without the negative impedance

(NI) circuit. The proposed TIA with NI is described as

having a transimpedance gain of 54.3 dB and bandwidth of

7 GHz. The simulation results shows that the bandwidth is

improved by 6 GHz compared to the TIA without negative

impedance (NI) circuit and without scarifying the gain. As

a result, the overall bandwidth of the TIA with NI is

extended seven times more. Simulations resulted in con-

siderable increase of gain bandwidth product (GBP) by a

factor of 5. The TIA consumes 29 mW from 1.8 V supply.

Figure 12 shows the frequency response of the TIA fordifferent photodiode capacitances varying from 50 to

200 fF. For photodiode capacitance 200 fF, the 3 dB

bandwidth is above 2.5 GHz and it is above 3.5 GHz with a

value of photodiode capacitance 100 fF.

Figure 13 illustrates the simulation of input noise cur-

rent spectral density. Simulation results shows an equiva-

lent input noise current spectral density below 5:9 pA/ ffiffiffiffiffiffi

Hzp

within bandwidth of 7 GHz.

Figure 14 shows the group-delay variation with fre-

quency. The TIA has a minimum group delay of 26 ps,

increases to 30 ps within the bandwidth of 7 GHz. The

output signal will suffer less from distortion when thephotodiode capacitance value is 50 fF.

The comparison of the frequency response of both the

schematic and extracted circuit of the TIA are shown in

Fig. 14. For the same gain of 54.25 dB X, the -3 dB

bandwidth of the schematic circuit of TIA is 7 and 6.5 GHz

for the extracted layout circuit (Fig. 15).

To study the impact of the process variations on the

frequency response of the TIA, a set of 100 samples has

been chosen for Monte Carlo simulation [25]. As shown in


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Fig. 16, the frequency response has a small variation due to

process variation and mismatching.

Corner analysis is used to make the design more

realistic by simulating the circuit in different operational

conductions, such as different temperatures and altered

process corners. Figure 17 shows the transient response of

the TIA at different process corners for 10 lA(p–p). As a

result, the merits of proposed TIA shows that the TIA can

work normally at different process corners with a small

input current for wide bandwidth. Figure 18 shows layout

of the TIA. The occupied area of the layout is

230 lm 43 lm.Table 1 shows a comparison of the proposed TIA per-

formance with other works. From Table 1, it can be seen

Fig. 10 TIA realization

Fig. 11 Simulation results

comparison of the frequency

response of TIA with and

without NI


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that the noise of the proposed TIA is smaller than the other

TIA configurations, where the active inductors have been

used. The power consumption is comparatively higher than

the other TIA circuits.

Fig. 12 Frequency response of the proposed TIA for four different

values of C pd

Fig. 13 Spectral density of the input noise current as function of

frequency

Fig. 14 Measured group delay variation of TIA for different values

of C pd

Fig. 15 The frequency response of the TIA (schematic and extracted)

Fig. 16 Monte Carlo simulation results for the frequency response

for 100 samples

Fig. 17 Transient response of the TIA under different corners

Fig. 18 Layout of the TIA


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6 Conclusion

This paper presents a compact transimpedance amplifier

(TIA). The effects of using the negative impedance (NI)

circuit are demonstrated through a proposed tran-

simpedance amplifier. The TIA is implemented in 180 nm

RF MOS transistors in a HV CMOS technology with 1.8 V

supply voltage technology. Cadence tools is used in ana-

lyzing the performance of the TIA. It is observed that the

TIA provides -3 dB bandwidth at 7 GHz, transimpedance

gain of 54.3 dB X in the presence of a 50 fF photodiode

capacitance and input referred noise current spectral den-

sity of 5:9 pA/ ffiffiffiffiffiffi

Hzp

. The power consumption is 29 mW.

The TIA occupies 230 lm 45 lm of area. Simulationresults show that the TIA is very proficient for applications

in optical transceivers.

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comparison of recent CMOS

TIAS

Ref. CPD (F) Gain (dB) BW (GHz) Power (mW) Noise pA= ffiffiffiffiffiffi

Hzp

Area

This work a 50 54.3 7 29 5.9 230 lm 9 45 lm

[26]a 50 54.3 5.35 3.48 8.2 –

[27]b 50 51 30.5 60.1 34.2 1.17 m 9 0.46 m

[28]b – 60 6.9 16.9 – 0.051 m2

[29]b – 50 7.5 4.1 – 0.42 m 9 0.17 m

[30]a – 51.7 8.5 13.97 – –

[31]a 200 64.8 4.5 3.5 13.7 97 lm 9 53 lm

a Simulation resultsb Measurement results


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Jawdat Abu-Taha received the

M.Sc. degree from Lecce

University, Italy in 2000 . He is

currently a Ph.D. student in ITU

and working as a Researcher in

the Electronics and Communi-

cation Engineering Department

of Istanbul Technical Univer-

sity. His research interest

include Analog RF IC design.

Metin Yazgi was born in

Trabzon, Turkey, 1971. Hereceived the B.Sc. degree in

Electronics and Communication

Engineering from the Faculty of

Electrical and Electronics

Engineering, Istanbul Technical

University, Turkey in 1992. He

received the M.Sc. and Ph.D.

degrees in 1996 and 2003 from

the Institute of Science and

Technology of the same uni-

versity. He is currently as an

associate professor in electron-

ics, teaching graduate and

undergraduate courses. His main research interests are microwave

broadband amplifiers and analog signal processing applications.


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