Arun A. Aiyer and Tianheng Wang

Frontier Semiconductor2127 Ringwood AveSan Jose, CA. 95131USA

Introduction

Technology

Results Micro Bumps C4 Bumps Cu Nails 2D Inspection Capability

Summary

In 3D packaging, chip or die stacking: Cu nail, Cu pillar or solder bumps as the interconnection.

Co-planarity inspection: critical for device yield enhancement.

Miniaturization and higher I/O density: inspection and metrology to higher level of measurement capability and throughput.

Therefore, a high throughput, production ready metrology tool that is capable of 100% height inspection will be very valuable:

yield improvement, cost of ownership reduction and tool utilization.

A patent pending technology: simultaneous measurement of individual z-dimension of features in an areal region.

3D Areal Imaging technology: 3D-AI.

Optical imaging: a standard camera and broadband light source.

Unique source-sensor configuration: coherent imaging from which the topography information can be deduced.

Sample measurement: Cu nails, µBumps, C4 bumps, flat bumps.

Broadband white light source

Imaging system

Standard CMOS camera

The inspection FOV: size of the illumination beam and sensor format

A series of images: phase information at each and every point in the FOV.

Intensity in the image plane can be presented as:

 

)()()(

)(2)()(

*2112

1221

tEtE

tItII

The parallel measurement capability of 3D-AI was modeled using ~10µm tall µBumps.

With phase images, height of individual bumps can be determined.

Field of view is scalable. 3D-AI enables simultaneous measurement of individual

z-dimension of features.

Raw Image Processed Image

Showing 120 bumps in the FOV. Height of each bump is acquired simultaneously.

In one approach1, the bumps that are within 2 SDs are considered as good coplanarity.

Average bump height is 26.96 µm with 1 SD of 0.44 µm. 99 bumps are within 2 SD. A few outliers which may cause problem. Coplanarity2 defined as Max-Min is 2.27µm.

1) “Ultra-Thin Ultrafine-pitch Chip-Package Interconnections for Embedded Chip last Approach” by Gaurav Mehrotra, Georgia Tech, Master’s Thesis, p. 90, 20082) “Bump Coplanarity” by Keith Doyle, Solid State Technology, http://electroiq.com/blog/2007/05/bump-coplanarity/

C4 bumps: average height of 80.38µm and 1 SD of 0.9µm. Best fit plane approach: coplanarity is calculated as 3.62µm.

128 nails: average height of 5.49µm and 1 SD of 0.95µm.

±1 SD: outliers 1) short enough to cause an open circuit and 2) long enough to puncture through the interconnect layer.

Flat µBumps

DefectMissing one bump

3D-AI sensor: 2D defect inspection. Both modes of inspection are enabled by the same sensor head.

3D-AI: measure z-height of all features simultaneously within a FOV.

The same sensor head: 2D defect inspection.

Throughput: scalable with number of sensor heads. 200mm wafer with single head; 300mm with multi-heads.

Ready for customer sample measurement / evaluation.

Thank you!