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C U S T O M E R E D U C A T IO N S E R V I CE S

Astro 1 Workshop Lab Guide 20-I-022-SLG-003 Version 2003.09

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Introduction to Astro

IntSyn

1

The purpose of this lab is to familiarize you with the Astro GUI and show you what a design looks like at the floorplanned, placed and routed stages.

During this lab, you will use Astro’s GUI to perform a minimal place and route of a design called RISC_CHIP.

You will execute command files or run scripts (which have already been created for you) to set up the design and perform floorplanning. You will then use the GUI menu commands to perform simplified placement, clock tree synthesis (CTS), and routing steps.

In later labs you will learn how to perform all these steps in detail.

After completing this lab, you should be able to:

• Invoke and exit Astro • Use the Astro GUI to enter commands and read tool messages • Use the cell window to inspect details of the layout of a design • Use Astro’s help and functions commands to get help through

the Documentation Browser • Load command files or scripts to execute pre-written Astro

commands • Perform minimal placement, CTS and routing on a simple design• Create a command script file by editing the cmd log file • Save and open the design at various stages

Learning Objectives

Lab Duration: 70 minutes

roduction to Astro Lab 1-1 opsys 20-I-022-SLG-003

Lab 1

Background

Design A design called RISC_CHIP will be used to illustrate the results of floorplanning, placement, clock tree synthesis (CTS) and routing. RISC_CHIP is a relatively small and simple design that will allow Astro to quickly show the results of floorplanning, placement, CTS and routing.

Flow The design setup, floorplanning and timing setup steps have been purposely automated for you through the use of pre-written command files. These steps prepare the design for placement. Automating the steps shows you graphical design results quickly, which is one of the main purposes of this lab. While you will be manually invoking the commands after the scripted floorplanning, you will be skipping many of the iterative placements, CTS, routing and optimization steps. In Lab 2 – Lab 8 you will be shown how to perform all the necessary steps, in detail, for design setup, floorplanning, timing setup, placement, CTS, routing, optimizations and design for manufacturability (DFM).

Lab 1-2 Introduction to Astro Synopsys Astro 1

Lab 1

Relevant Files and Directories

All files for this lab are located in the lab1 directory under your home directory.

The following directories and files will be used:

lab1/ scripts/ Contains run scripts or command files: design_setup.cmd Prepares design for floorplan, place & route

timing_setup.cmd Performs timing setup and timing constraint

floorplan_1.cmd Defines the core area and pad placement

floorplan_2.cmd Defines P/G grid and macro cell placement

pnr.cmd Will be created by the student –to perform simple placement, CTS & routing

logs/ Will contain the log and command files generated by Astro

The following directories and files will be accessed or created by running the command files:

design_data/ Contains the RISC_CHIP design input data:

RISC_CHIP.sdc Timing constraints

RISC_CHIP.tdf I/O cell data

RISC_CHIP.v Verilog netlist

design_lib_risc/ RISC_CHIP physical design library that will be created by Astro

ref_lib/ Link to I/O, standard cell and macro designs star_rcxt/ Link to parasitic TLU+ model files tech/ Link to physical technology files

Answers/Solutions are available at the end of this lab.

Introduction to Astro Lab 1-3 Synopsys Astro 1

Lab 1

Lab 1 Instructions

Task 1. Invoke, Explore and Exit the Astro GUI

1. Log in to the UNIX environment with the user id and password assigned by your instructor.

From your login or home directory, change your current directory to lab1, which is the working directory for this lab.

unix% cd lab1

2. Preview command line switches available with the Astro command by using the -help switch:

unix% Astro –help

3. Invoke Astro as shown:

unix% Astro –cmdd logs/RISC –logd logs/RISC &

A command log file captures all executed Astro commands. The log file will capture both the executed Astro commands as well as tool messages.

Pull-Down Menu Area

Command History Area

Message/Input Area Accepts user-typed commands and echoes

command status and error messages.


Lab 1

4. Select the Library pull-down menu, then select the Open … command

(Library Open …).

A dialog box labeled Open Library opens, ready for user input.

Notice the Command History Area on the right echoes the command geOpenLib, which is the command executed by the pull-down menu.

5. Cancel the Open Library dialog box.

Question 1. What commands were executed that open and close the library dialog box? .................................................................................................... . ...................................................................................................

6. If you plan to execute several commands from the same menu it is possible to make a menu “stick around”.

Select the Cell menu and select the dashed lines (-------------) at the very top of the menu, above the commands. This opens a new, free-floating Cell menu, which contains the menu items (you may have to move the main Astro window to find it).

You can now execute several commands without selecting the Cell menu every time.

Close the sticky menu (as with any UNIX window: by double-clicking the upper-left icon in the menu banner).

7. The Message/Input Area on the left is used to enter commands interactively. The commands you type will appear in blue. Type, but do not yet [Enter] the word newload in the Message/Input Area. Notice the blue color of the command.

Note: You are purposely typing an incorrect command.

8. Now [Enter] the command.

You will see an ERROR message stating that newload is an “Unbound variable”. Since newload is not a recognized command, Astro assumes it must be a variable. The variable has not been defined so Astro will flag such entries.


Lab 1

The correct command is load.

9. Use the up-arrow key on your keyboard to recall the last command you entered, which should be newload. Correct the command by using the left/right arrow keys and [Backspace] or [Delete]. You can also delete everything to the left of the cursor using [Ctrl] U.

10. [Enter] the load command. You will see a new ERROR message stating that the command has the “Wrong number of arguments”. You did not enter the file to be loaded.

All commands in Astro have a related help page. You can see the help page from the online documentation by typing help “command_name” in the Message/Input Area.

11. Open and read the help page on the load command by enterring the following:

help "load"

12. Close the help page window by double-clicking the icon in upper-left corner or by selecting File Close Browser !

Case sensitive and quotes are required!

13. If you are unsure of the exact Astro command syntax, but know a partial key word, use the command functions “keyword” to get a list of all commands that contain that keyword. Try the following to get a list of all commands containing the string verilog in them:

functions "verilog"

Note: A wildcard character is automatically implied before and after the keyword.

Not case sensitive but quotes are required.

In the steps above you may have noticed that there is no command “prompt” to tell you that the Message/Input Area is ready to accept your input.

Notice the empty square brackets [] in the lower left corner, below the Message/Input Area. During execution the Astro command being executed is displayed in the brackets (for some commands, this may happen too quickly to actually see). When done, the brackets are empty and Astro is ready to accept your entry, another way to verify that Astro is ready and accepting your input is when your entry turns blue.

14. Exit Astro by selecting the following pull-down menu sequence:

Select Tools Quit … Click “OK”

15. Review the log files that were created in the logs/ directory and answer the questions below:


Lab 1

Question 2. What do the Astro command options –cmdd and –logd do? ....................................................................................................

Question 3. Which of the two files can be copied and easily edited to create a command file or script? ....................................................................................................

Task 2. Setting up the Design

1. After exploring the log files, be sure that your current directory is lab1.

2. Invoke Astro from the lab1 directory.

unix% Astro –cmdd logs/RISC –logd logs/RISC &

All data preparation commands that set up the design library, the design cell, and read in the netlist are provided for you in the scripts/design_setup.cmd file. Glance at the file, but do not spend a lot of time looking at the details. All the commands in this command file will be covered in later units.

3. Execute the command file in the Message/Input Area.

During execution you will see several command dialog boxes open and close. DO NOT ATTEMPT TO SELECT any of these dialog boxes during execution:

load "scripts/design_setup.cmd"

After the command file execution completes, you should see a “#t” in the Message/Input Area indicating the last executed command in the command file, astMarkHierAsPreserved, returns a value of “true”. You should see a newly opened graphical window.

This window is called the cell window. The cell window appears empty, but actually contains all the IO, macro and standard cells of the design that have been read in from the Verilog netlist.

In the top banner of the cell window the name of the cell being displayed is shown – RISC_CHIP.CEL. The number after the semicolon represents the version of the cell, in this case version one, since the cell has just been created.

The name of the design library to which this cell belongs is also shown – design_lib_risc. The design library acts as a “container” for the design cell and all the associated data and information required for placing and routing the design.


Lab 1

You will also find that a UNIX directory called design_lib_risc has been created in the lab1 directory.

The topic of design libraries and design cells will be discussed in detail later.

4. Zoom out to see all the IO, macro and standard cells by selecting the fit with margin button

Note: If you hover with your mouse over the various buttons, a short help text will appear.

You will notice that all cells, outlined in yellow, are initially placed on top of each other before the design is floorplanned, placed and routed. You will explore some of the other commands in the Cell Window in the next Task.

It is good practice to save your design after completing key stages of the layout steps. Using a cell name that is descriptive of the stage of the design is useful if you ever want to return to a previous stage to redo a step or experiment with alternative steps.

5. Save the cell view with a cell name of RISC_design_setup.

Select Cell Save As … Enter RISC_design_setup as Cell Name Click “OK”

Task 3. Floorplan Generation

During this task, you will generate a floorplan for the design. The floorplan defines the dimensions of the chip and core area, the location of the pad cells, macro cells and standard cell placement rows, as well as the power grid. The command files to perform the floorplanning steps provided for you. Floorplanning will be discussed in detail in a later unit. For illustration and exploration purposes the floorplanning steps have been divided into two parts: core definition and pad cell placement, followed by macro cell placement and power grid definition. This allows you to view some intermediate results for easier understanding.

1. Execute the first of the two floorplanning command files.

Warning: DO NOT ATTEMPT TO SELECT any of the dialog boxes during execution:

load "scripts/floorplan_1.cmd"


Lab 1

After the command file execution completes, you should see the messages “Planner run through successfully” followed by #t.

The full view in the cell window now contains a chip outline. In the center is the core area containing the standard cell placement rows. The narrow rectangles surrounding the core area are the pad cells. On the right of the chip is the stack of unplaced standard cells referenced by the netlist, which will later be placed in the placement rows. The macro cells are sitting on top of the chip, which will be placed during the next part of the floorplanning steps.

Unplaced standard cells

Pad cells

Chip outline

core area

Macro cells

2. Practice using the zoom and pan commands. See detailed explanation in the following steps.

3. The green rectangle in the context window represents the outline around all the cells (standards, pads, macros). The red rectangle represents the current view. As you zoom and pan around, the red rectangle will change accordingly.

(Red) Area of the current cell view

(Green) Area fully enclosed all cells

Context window

Pan and center commands

Zoom to area


Lab 1

4. To zoom into a specific area select the zoom to area button with the left mouse. A “crosshair” appears at the tip of the cursor arrow.

Place the crosshair at one corner of the rectangular area you want to zoom into, then click and RELEASE the left mouse button. Move the crosshair to the diagonally opposed corner of the zoom area, click and release the left mouse button again. The view zooms in. Notice that the crosshair remains allowing you to zoom in further if you like.

When you are finished zooming in either select another view button, example: pan, or fit with margin, press the [Esc] key, or click the right mouse button to end the zoom command.

5. Zoom into the left edge of the placement rows and confirm that the rows are abutted and flipped.

You should see that the “orientation triangle” on the left corner of every other row was flipped along the x-axis.

Notice a small red rectangle in the lower part of the green rectangle in the context window. The red rectangle displays the area that you are currently zoomed in on or the current view of the cell window.

6. Zoom into the macro cells in the upper left area at the top of the chip outline.

Question 4. Judging by their FRAM view name, what is the memory array size of the RAM macro cells? ....................................................................................................

Notice in the lower left corner of each macro cell there is an orientation mark that looks like the letter “P”, with a slanted “A” inside of it. The macro cells are currently placed with their original orientation. When the macro is flipped/rotated, the orientation mark changes.

7. Many functions can be accessed via keyboard shortcuts or bind keys.

To get a full list of all the key bindings, select the menu Query Bind Keys! (Bind Keys! is at the bottom of the Query menu).

You will see a listing of bind keys and corresponding Astro commands in the Message/Input Area. Notice for example that you can press “z” (“zoomTo”) to zoom to an area, instead of clicking on the zoom-to-area button.

Question 5. What is the instance name of the bottom pad cell on the left side? ....................................................................................................


Lab 1

Hint: To help answer the question, find and use the bind key for the command geQueryObject. Place your cursor in the cell window; press the bind key, then click the object you want to query with the left mouse button.

The instance name, along with additional information about the object, will be displayed in the Message/Input Area.

If multiple objects are stacked on top of one another, use the F1 key to cycle through them.

To end the execution of the command, press the [ESC] key or click the right mouse button.

Question 6. What is the orientation of the pad cell? ......................................

Note: Observe how the rotation mark is changed.

8. Save the cell as RISC_floorplan_1.

Select Cell Save As … Enter RISC_floorplan_1 as Cell Name Click “OK”

9. Execute the floorplan_2.cmd command file to place the RAM macro cells in the core area, and create the power and ground metal routes, also called the “P/G grid”.

load "scripts/floorplan_2.cmd"

Hint: Use the up arrow key to recall previous commands.

After the script finishes executing, look at the layout in the cell window. You should see the two macro-cells placed at the bottom of the core. You should also see power and ground rings around the core area, as well as vertical and horizontal P/G straps running through the core.

Note: You may need to “zoom out” or “zoom fit” the display.

Use the query-objects command (bound to ‘q’ key) to explore these objects.

Question 7. Is the outer ring power or ground?

..................................................................................................... What is its net name?

.......................................................................................................


Lab 1

You may be wondering what happened to the orange placement rows? They are actually still there. The script turned off their “visibility”, so that you can see the core area more clearly.

10. To make the placement rows visible again, select the Window option button on the left banner of the cell window.

On the dialog box that pops up, notice that the top row of buttons is labeled Visible Objects, and that the button for row is unselected.

Turn the row button ON, select the Apply button on the top of the dialog box, followed by Redraw.

The rows now appear in the core area.

Click OK to close the dialog box.

This completes the floorplanning step for RISC_CHIP. In the next task you will set up the design for timing.

11. Save the cell as RISC_floorplan_2.

Task 4. Timing Setup

Before the design can be placed in the next step, you have to communicate to Astro the timing intentions, or constraints for the design. This is done by applying an SDC (Synopsys Design Constraints) file. There are also other timing related settings that have to be applied before placement, example, setting the correct parasitic extraction model. Settings may change at each stage of the design, after placement, after CTS, and at the routing stage. Here you will only apply timing settings once.

1. Execute the timing setup script:

load "scripts/timing_setup.cmd"

This script loads the SDC file and sets the correct capacitance model.

2. Analyze the desgin for timing by execute the following command:

ataReportSummary

This command shows a summary of the design’s timing. Looking at the left-most column, you will see that the design has a worst negative slack (WNS) of ≈ 2.3 ns.

3. Save the cell as RISC_timing_setup.


Lab 1

4. Exit out of Astro. Do not save RISC_CHIP.

Select Tools Quit Select “Discard All” when prompted to Save Cells Click “OK”

Note: It is not customary nor required to quit Astro after floorplanning. You are being asked to do this so you can be shown in the next Task how to open a previously saved cell.

Task 5. Standard Cell Placement and CTS

The placement stage typically involves many different steps. Besides standard cell placement, HFN (High Fanout Net) collapse/resynthesis and numerous placement related optimizations might be performed. Similarly, clock tree synthesis (CTS) involves many steps, including CTS, incremental CTS and optimization (CTO). In this task you will perform only a standard cell placement step followed by one CTS step on RISC_CHIP, which is a relatively simple design with few design challenges. The main purpose of this task is to illustrate what a placed design looks like. You will not see a big difference after CTS – you are performing CTS for completeness. In later units you will learn to use all of the recommended placement and CTS steps.


Log the session in logs/RISC with the date and time and save the command file to logs/RISC with the date and time.

2. Open the design library design_lib_risc.

Select Library Open … Enter design_lib_risc for Library Name Click “OK” Note: You can also use the Browse … button for selection.

3. Open the design cell that was saved at the end of previous task.

Select Cell Open … Click “Browse …” to open the Browse dialog box Select RISC_timing_setup cell Click “Hide” to close Browse dialog box Click “OK” to open RISC_timing_setup cell. You should see the RISC_CHIP design saved previously, with the floorplanned macro cells and P/G grid. You will now place the standard cells that are still “waiting” outside the chip.


Lab 1

4. Invoke default Design Placement:

Select InPlace Design Placement … Click on “Default” Click “OK” After you see the message “AstroPlace completed successfully” in the Message/Input Area, examine the RISC_CHIP cell. You will see that the standard cells that were piled up vertically outside the design are now placed in the core area, on the placement rows.

Question 8. Is this a pad-limited or a core-limited design? ....................................................................................................

The bars that you see below and to the left of the design are congestion indicators. These will be discussed in more detail in later Units.

5. Save the cell as RISC_placed.

6. Invoke default clock tree synthesis:

Select Clock Clock Tree Synthesis: Clock Tree Synthesis … Click “Default” Click “OK”

After CTS has completed you will see the message “CTS: Clock tree optimization completed successfully”, followed by a “Clock Tree Optimization Summary”.

Question 9. From the summary report, how many buffers were inserted in the clock net clk? ....................................................................................................

7. Save the cell as RISC_cts.


Lab 1

Task 6. Auto Routing

Just like placement and CTS, routing consists of many steps, which can take a long time to complete. Here you will perform a simple auto-route in order to quickly illustrate what a routed design looks like.

1. Execute default AutoRoute, which will automatically route the placed design:

Select Route Auto Route … Click “Default” Click “OK”

When you see the message “Updating the database …”, the routing has completed.

2. Use the zoom and query-objects commands to answer the following questions.

If you have not already done so, you may want to turn off the placement row visibility in order to see the metal routes more clearly.

Question 10. How many metal layers were used to route this design? ....................................................................................................

Question 11. What are the preferred vertical and horizontal routing layers? ....................................................................................................

3. To see the pins of the cells (the standard cell connection points that the metal routes connect to), you will have to enable their visibility by:

Click the Window option button in the cell window Turn Visible Pin Instances to ON for “std / module cell” Click “Apply” Click “Redraw” Click “OK”

Question 12. By visual inspection, what metal layers are the standard cell pins on? ....................................................................................................

4. Generate a timing summary again using the command learned in task 4.

Question 13. How large is the negative slack now? ....................................................................................................


Lab 1

5. Save the cell as RISC_routed.

6. Quit Astro and discard all cells.

Congratulations! You have taken a design through all of the major Astro steps, including design setup, floorplanning, timing setup, placement, CTS and routing.

Task 7. OPTIONAL: Create a Command File

If you have completed Task 6 ahead of schedule and you have at least 10 minutes of additional lab time available, try this optional task. Here you will make use of the command history that is recorded in the command log file to create your own command file. The command file that you will create will execute all the steps in Task 5 and 6, including:

• Opening the starting Library and Cell

• Performing Design Placement

• Saving the cell

• Performing CTS

• Saving the cell

• Performing AutoRoute

• Saving the cell

1. From the logs/ directory copy the most recent RISC.cmd.mm_dd_hh_mm command file into your scripts/ directory and call it pnr.cmd.

unix% cd logs

unix% ls -l ;find the most recent cmd file

unix% cp RISC.cmd.mm_dd_hh_mm ../scripts/pnr.cmd

unix% cd ../scripts

2. From the scripts/ directory, use a UNIX editor to open the pnr.cmd file.

3. Edit and delete the Astro commands as needed to create a command file that executes the seven steps listed above.

If you want to see the results immediately after running the command file, do not quit Astro at the end of your command file.


Lab 1

Note: If you need some help refer to the Astro commands shown in the Answers/Solutions section of Task 5 and Task 6. If you are really stuck there is a solution command file in the .solution/ directory, called task7.cmd.

4. When your command file is ready, invoke Astro (make sure you change back to the lab1 directory!) and execute your command file. Good luck!

unix% cd ~/lab1

unix% Astro –cmdd logs/PNR –logd logs/PNR &

load "scripts/pnr.cmd"

After your command file finishes execution, look at the design in the cell window – it should look exactly the same as the RISC_CHIP design that you placed and routed in Tasks 5 and 6.

5. Check the Message/Input Area or the more extensive log file for any ERRORS. There should not be any.

Note: You can ignore the following WARNING messages: **** WARNING:illegal grid layer(30) for cell (unitTile) **** WARNING:Ignore 34 top-cell ports with no pins! **** WARNING:Layer (METAL3) pitch (0.515) may be TOO SMALL.

If you need help debugging a problem ask your instructor. If your command file executed correctly, you are done - CONGRATULATIONS!

6. Quit Astro. Do not save any cell.

Congratulations! You have completed Lab 1 and created the command file.


Lab 1 Answers / Solutions

Answers / Solutions

Question 1. What commands were executed that open and close the library dialog box? geOpenLib formCancel "Open Library"

Question 2. What do the Astro command options –cmdd and –logd do?

These options allow you to specify log and command file names and locations. By default Astro places the files in the current working directory and gives them a default name beginning with Astro. The –cmdd option captures the executed Astro commands in a file named RISC.cmd followed by a date/time stamp. The –logd option captures the executed commands as well as the tool messages, essentially what you see in the Message/Input window, in a file named RISC.log.mm_dd_hr_min.

Question 3. Which of the two files can be copied and easily edited to create a command file or script?

The RISC.cmd file can be copied, renamed and edited as needed to add comments, remove extra or incorrect commands, etc. The resulting command file can then be automatically executed using the load command. This is the technique that was used to create the command files that you will be executing in the following tasks. You will create your own command file in the optional Task 7.

Question 4. Judging by their FRAM view name, what is the memory array size of the RAM macro cells?

From the name of the abstract (FRAM) view, ram16x128, the RAM contains a 16 by 128 bit memory array.

Question 5. What is the instance name of the bottom pad cell on the left side? Use the “q” bind key to query the specific IO-PAD object. From the Message/Input Area you see its INSTANCE NAME: Instrn_iopad_0


Answers / Solutions Lab 1

Question 6. What is the orientation of the pad cell? The orientation mark “P” is rotated 90 degrees clockwise, or 270 degrees counter-clockwise. In the output of the query object command you will also see ORIENTATION: rotate 270. Astro uses a counter-clockwise definition for rotation.

Question 7. Is the outer ring power or ground? What is its net name? Using the query-objects command, [q], the NET TYPE is ground, and the NET NAME is VSS. The ROUTE TYPE confirms that this is a P/G Ring, as opposed to a Strap.

Task 5. Standard Cell Placement and CTS

2. Library Open … Browse design_lib_risc OK

The equivalent Astro commands are listed below. You can type these commands in the Message/Input Area instead of using the menu sequence above. Refer back to these commands if you perform the optional Task 7.

geOpenLib

setFormField "Open Library" "Library Name" "design_lib_risc"

formOK "Open Library"

3. Cell Open … Browse RISC_timing_setup OK

geOpenCell

setFormField "Open Cell" "Cell Name" "RISC_timing_setup"

formOK "Open Cell"

4. InPlace AstroPlace: Design Placement … Default OK

astPlaceDesign formDefault "AstroPlace – Design" formOK "AstroPlace – Design"

Question 8. Is this a pad-limited or a core-limited design?

You will notice that the cells are very sparsely placed in the core area and that all pads abut. This is a pad-limited design.



5. Cell Save As … RISC_placed OK

geSaveAs setFormField "Save As" "Cell Name" "RISC_placed" formOK "Save As"

6. Clock Clock Tree Synthesis: Clock Tree Synthesis … Default OK

astCTS formDefault "Clock Tree Synthesis" formOK "Clock Tree Synthesis"

Question 9. From the summary report, how many buffers were inserted in the clock net clk?

The summary report indicates that 14 buffers were used.

7. Cell Save As … RISC_cts OK

geSaveAs setFormField "Save As" "Cell Name" "RISC_cts" formOK "Save As"

Task 6. Auto Routing

1. Route Auto Route … Default OK

axgAutoRoute formDefault "Auto Route" formOK "Auto Route"

Question 10. How many metal layers were used to route this design?

The routed design uses four metal layers. They are colored yellow, green, red and blue. These metal layers, along with other technology specific information, are defined in the “technology file”, which is discussed later.

Question 11. What are the preferred vertical and horizontal routing layers?

Using the query-objects command you can determine that the LAYER of the yellow and the green vertical route is METAL2 and METAL4, respectively. The LAYER of the blue and the red horizontal route is METAL (METAL 1) and METAL3, respectively.



Question 12. By visual inspection, what metal layers are the standard cell pins on? METAL (Metal 1)

4. Generate a timing summary again using the command learned in task 4.

ataReportSummary

Question 13. How large is the negative slack now?

There is no negative slack, the slack is now positive. Do not worry about the hold time negative slack; fixing hold time will be addressed in later units.

5. Cell Save As … RISC_routed OK

geSaveAs setFormField "Save As" "Cell Name" "RISC_routed" formOK "Save As"



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Timing Setup

TimSyno

2

Learning Objectives


During this lab you will load a design, which has already gone through the design setup steps and has been floorplanned. You will perform all timing setup steps, which are required to constrain the design during placement and CTS (i.e. pre-CTS). You will be given a Job Aid that summarizes all the timing setup steps, including how to reconfigure timing setup for post-CTS.

You will also verify that the timing goals are achievable before beginning placement.


• Open an existing design library and cell

• Load appropriate parasitic model (TLU/TLU+)

• Load a timing constraints file (SDC file)

• Verify that the timing constraints file contains necessary key constraints

• Configure the timing setup panel for a pre-CTS stage

• Perform a PrePlace “timing sanity check” to verify that timing goals are achievable post-route

ing Setup Lab 2-1 psys 20-I-022-SLG-003

Lab 2

Background Part A: Timing Setup with TLU models

A design called ORCA will be used to illustrate the concepts of design setup, timing setup, floorplan, optimization, placement, clock tree synthesis (CTS), and routing during this entire workshop. The technology used to implement ORCA is a 0.13 µm, 4-metal-layer process.

In this lab, you will open an ORCA design cell that has already been created for you and has gone through all design setup steps as well as floorplanning (discussed later in the workshop). The design cell is called floorplanned, and it is saved in the design library called design_lib_orca.

You will perform all the necessary timing setup steps which include: verifying that the TLU models are attached to the library; loading and checking the SDC timing constraints file; performing a ‘timing sanity check’ on that cell to verify that the design will be able to meet timing after place & route; and finally, configuring the timing setup panel for pre-CTS analysis and runs.

During this lab, mistakes were purposely introduced to enhance the learning. The mistakes will include performing steps in the wrong sequence, skipping steps, files with missing or incorrect data, etc. It is therefore very important to follow the lab instructions exactly as detailed below. If you circumvent some of the steps to do things “the right way” you may miss some very important lessons.

A Job-Aid is also provided which summarizes all the key steps involved in performing timing setup. You will use Job Aid “C” in this lab. It is also intended to be a useful reference tool, once you return to work.

Lab 2-2 Timing Setup Synopsys Astro 1

Lab 2




lab2/

design_data/ Contains the ORCA design input data:

con1.sdc Timing constraints file (incorrect) con2.sdc Timing constraints file (correct)

design_lib_orca/ ORCA physical design library that contains Floorplanned cell to be used by this lab


The following directories and files will be accessed during this lab:

ref_lib/ Link to I/O, standard cell and macro designs

star_rcxt/ Link to parasitic TLU+ model files

tech/ Link to physical technology files


Timing Setup Lab 2-3 Synopsys Astro 1

Lab 2

Lab 2A Instructions

Task 1. Verify TLU Models are Loaded

1. Invoke Astro from the lab2 directory:

unix% cd lab2

unix% Astro –log logs/timing_setup.log &

2. Open the existing design library called design_lib_orca:

Select Library Open … Enter design_lib_orca for Library Name Note: You can also use the Browse … button to select the

available libraries.

Click “OK” For now, the design library is a “container” that contains the design netlist, the cells, and additional necessary data. This container also links to the reference libraries, which in turn contain the frames, or abstracts, of all standard cells and macros. You will learn all the details of what a design library is in later units.

3. Open the existing cell called Floorplanned:

Select Cell Open … Enter Floorplanned for Cell Name Click “OK”

The floorplanned ORCA design is opened. It has placed IO pads and macro cells, as well as P/G rings and straps.

The next step would be to perform a timing sanity check. Answer the next question but do not perform these steps.

Question 1. From what you learned during lecture, what steps should be performed before running a timing sanity check? .................................................................................................... ....................................................................................................

To enhance the learning experience of this lab you will skip the steps necessary to perform a timing sanity check for now.


Lab 2

4. Generate a default timing report:

Select Timing AstroTime: Timing Report … Click on “Default” Click “OK”

You will notice that no timing report is generated! If you move the Timing Report dialog box out of the way, you will see the following message in the Message/Input Area: ERROR: no TLU cap table exists in the library Error in creating TLU models ERROR: Fail to get delay/trans thresholds Timing Report failed. Fail to execute command

The error “no TLU cap table exists in the library” indicates that the library is missing a TLU model for the parasitic interconnects. A library must contain a parasitic capacitance model (either TLU or TLU+) before any timing analysis can be performed on a cell from that library.

5. Close the Timing Report dialog box by clicking Cancel.

TLU models are included in the technology file, which is then attached to the design library.

It is possible to “dump” the technology file of an existing design library. You will do that next to verify that the TLU models are indeed missing.

You will search for the key words CapTable and CapModel. If they are missing from the dumped file, you will need to attach a different technology file with the TLU models library.

6. Dump the technology file of the library design_lib_orca into a file called tech_file.dump:

Select Library Dump Tech File … Enter tech_file.dump for Technology File Name Enter design_lib_orca for Library Name Click “OK”

The file appears in the lab2 directory.

7. Open tech_file.dump using your favorite text editor and search for key words: CapTable and CapModel.

The technology file contains electrical parameters and layer definitions for a specific technology, among other things. You will find that this file does not contain the key words above. This confirms that the library does not have an attached TLU model.


Lab 2

8. Look at the tech/ cb13_4m_tlu.tf. file and verify that there are capacitance tables and models in this technology file.

9. Next, you will replace the technology file that is currently attached to the library with the one that contains the TLU models:

Select Library Replace Tech File … Enter tech/cb13_4m_tlu.tf for Technology File Name Enter design_lib_orca for Library Name Click “OK”

Note: TLU+ models are NOT included in the technology file. You will deal with TLU+ models in Part B of this lab.

10. Now that the correct tech file with TLU models is loaded, try to generate a timing report for the sanity check again:

Note that you have not applied SDC constraints yet!

Select Timing AstroTime: Timing Report … Click on “Default” Click “OK”

Notice: No TLU errors this time! A window opens and displays a timing report. The timing report contains a lot more information than you currently need – all you care about when doing a timing sanity check is the worst-case setup violation. This number is summarized in the Message/Input Area. By default, the timing report lists the worst setup and hold time for each clock domain. Since ORCA has four clocks, PCI_CLK, SDRAM_CLK, SYS_CLK and SYS_2x_CLK, a total of eight paths are shown. The Message/Input Area lists only the worst setup and hold value.

11. Close the Astro Timing Report window by selecting the Close button.

12. Instead of generating a full timing report each time, you can use the following function to get just the timing summary in the Message/Input Area.

ataReportSummary

Question 2. What is the worst setup slack that is reported in the Message/Input Area? ....................................................................................................

This is a relatively large violation, considering the largest clock period for this design is 15 ns! Recall, that during a timing sanity check you are expecting either relatively small, or no violations.


Lab 2

Besides the large violation, something else is not right. Even without loading SDC constraints, this design is already constrained! Since you are not sure where the existing constraints came from, or if they are the correct ones, you should remove the existing constraints and load the correct file.

Task 2. Loading SDC Constraints

For the reason you discovered above, it is a good idea to remove the existing constraints from a design before loading the intended constraints file.

1. Enter the command below in the Message/Input Area to remove existing timing constraints:

ataRemoveTC

2. Load the SDC file design_data/con1.sdc:

Select Timing Constraints: Load SDC … Enter design_data/con1.sdc for SDC File Name Click “OK”

3. Generate another timing summary.

Use the up-arrow to recall the command ataReportSummary.

Note: You may safely ignore the warnings about creating clocks on mux pins.

Question 3. What is the worst slack after loading the SDC file? ....................................................................................................

Notice that the timing slack is different compared to the slack that you saw before loading the SDC constraints file.

Conclusion: Constraints are saved with the design cell. Do not trust the constraints that may already exist on a design. It is a good idea to remove all constraints before loading the SDC file. (Someone else may have been experimenting with timing constraints before handing off the floorplanned design to you for the “official” timing setup.)

Since the negative slack is still large, there may be problems with the SDC constraints that you loaded.

4. Perform a “Timing Data Check” to verify that the constraints are correct and complete:

Select Timing Astro Time: Timing Data Check … Click “OK”


Lab 2

A new Astro Timing Data Check window opens.

Near the top, it reports “2934 Unconstrained Endpoints”. These are paths with endpoints that are missing an “arrival time” constraint. An “endpoint” is an output port or a register input pin (data, scan-in, set/reset, enable, etc).

If you scroll down past the 2934 endpoints you will find “51 Ports With No Input Delay”. These are input ports that are also missing an “arrival time” constraint.

Scroll past the 51 input ports and you will find “739 Clock pins with no driving clock”. There are many missing clocks, and some clock pins with multiple clock definitions.

It is clear that the constraints file that you loaded, con1.sdc, is not complete or correct. You will be given another, correct and complete constraints file.

5. Close the Astro Timing Data Check window by clicking on close button.

6. The corrected constraints file is con2.sdc; compare it with the one you loaded:

unix% diff design_data/con1.sdc design_data/con2.sdc

Below are some of the differences:

The sys_clk as well as the pclk ports in con1.sdc have two clock definitions (create_clock commands). They should only have one: 8 & 15 ns respectively.

•

•

•

The con1.sdc file is missing a clock definition for the internally generated clocks SYS_CLK and SYS_2x_CLK, which explains the large number of unconstrained endpoints observed earlier. con2.sdc has many set_input_delay and set_output_delay commands, which are missing in con1.sdc.

Note: Errors like these are not uncommon if the constraints are generated or edited manually. The Timing Data Check can detect many problems, but not all. It is the responsibility of the synthesis or the full-chip timing analysis engineer to provide correct constraints for Place & Route.

7. Do you remember how to do the following, without any help?

a. Load the new con2.sdc constraints file

b. Perform another timing data check to make sure all timing paths are constrainted.

c. Generate a timing summary.


Lab 2

8. If you see a worst slack of ~ –11.2 ns, CONGRATULATIONS, you “clearly” remembered an important lesson shown earlier (namely to clear or remove the old constraints before applying new ones). Go to Task 3.

9. If you see a worst slack other than ~ –11.2, you forgot a step…

Question 4. What is the recommended step before loading an SDC constraints file? ....................................................................................................

Even though the new SDC constraints file does not contain multiple clocks, the multiple clocks from the con1.sdc file are still lingering on the design.

10. Clear the constraints using ataRemoveTC, reload the con2.sdc file and perform a timing data check.

This time you should get a clean report.

Task 3. Configuring the Timing Setup Panel

Review what you have done so far:

In Task 1, you confirmed that the library was missing TLU models by dumping the technology file, and you replaced the tech file with one that has the TLU models.

In Task 2, you cleared old constraints from the design. You discovered the SDC constraints had incorrect and incomplete constraints by doing a timing data check. You then loaded and verified a new constraints file. You still have not completed what you started to do at the beginning of this lab, namely to perform a timing sanity check! The next task is to set up the design for all pre-CTS optimization stages then perform a timing sanity check.

1. Generate a Timing Report.

2. In the Timing Report window look at the section near the top, titled Design Setup. This section lists the status of several parameters that Astro uses to perform static timing analysis (STA). Notice that the 5th parameter from the top, Wire Delay, is set to AWE.

Question 5. Which wire delay model should be used pre-CTS, Elmore or AWE? Why? ....................................................................................................


Lab 2

Question 6. Which wire delay model should be used to perform a Timing Sanity Check? ....................................................................................................

3. Notice that the 7th parameter from the bottom, Ignore Propagated Clock, is disabled. Translation: Propagated clocks are enabled.

Question 7. Should Astro use Propagated or Ideal clocks pre-CTS? Why? ....................................................................................................

Conclusion: In addition to loading correct timing constraints, Astro’s timing parameters must be configured to use the appropriate constraints and models for the given design phase (e.g. timing sanity check, pre-CTS or post-CTS). You will do this next, by configuring Astro’s Timing Setup Panel.

4. Close the Astro Timing Report window by clicking on close button.

5. Bring up and configuring Astro’s Timing Setup Panel:

Select Timing AstroTime: Timing Setup …

Notice that there are six “tabs” at the top of the panel. The tabs that are most often used are the Environment, Parasitics and Model tabs.

Select the “Model” tab.

Notice at the bottom of the panel the Net Delay Model is set to AWE. Change it to Elmore, click on the Apply button, to apply the change. This will have no effect on the timing sanity check; it is, however, a recommended setting for pre-CTS optimization.

Select the Parasitics tab.

Verify that the Capacitance Model is set to TLU. If it is not, select TLU and Apply the change.


Lab 2

Select the Environment tab.

Notice that the Ignore Interconnect option is OFF (disabled). Since you want to perform a timing sanity check, it is important to ignore the interconnect parasitics. Turn the Ignore Interconnect option ON (enabled) to direct Astro to ignore the net delay models and parasitic capacitance that you specified above.

Note: After running the timing sanity check report, this option should be turned OFF and remain OFF.

Next notice that the Ignore Propagated Clock button is OFF (disabled). This “double-negative” (ignore = off) is somewhat confusing, but it means that propagated clocks are enabled. Since this is pre-CTS, you do not want Astro to calculate propagated clock delays.

Turn the Ignore Propagated Clock option ON.

Turning this option ON directs Astro to use the estimated “ideal” clock latencies and skews.

Use the job aid “c” to verify the other options on the Environment tab are set correctly for the pre-CTS phase. The screen-shot on the back of the job aid shows the recommended settings (except for “Ignored Interconnect”).

Apply the Environment settings and click on the Hide button in the upper-left corner to close the Timing Setup Panel.

You are finally ready to perform the Timing Sanity Check!

6. Generate a Timing Summary Report using the ataReportSummary command.

Question 8. What is the reported slack after setting up the Timing Setup panel for a pre-CTS timing sanity check? ....................................................................................................

This positive slack result is exactly what you are looking for at the timing sanity check point: This implies that there is a good chance that the design can meet its timing constraints after placement, CTS and routing have been completed. Do not pay much attention to the negative hold slack. Hold is addressed after clock tree synthesis, and will be discussed later.

Note: If your slack is different than the answer, go back to the Timing Setup Panel and check the parameters. Remember that each tab must be individually applied by selecting the Apply button before choosing the next tab!

Conclusion: The Timing Setup Panel parameters direct Astro on how to interpret the SDC constraints, which are applied to the design, possibly ignoring some of them.


Lab 2

The Timing Setup parameters also direct Astro as to what timing models, parasitic models and operating conditions should be used, and much more.

Making entries on the Timing Setup Panel sets the Timing Setup parameters. All panel settings, with the exception of one, Ignore Interconnect, are saved when you save the design. This means that once they are set they do not need to be modified until your design reaches a different phase that warrants new settings (e.g. post-CTS).

Note: The Ignore Interconnect option automatically reverts back to the disabled or OFF position once the design is closed.

7. Save the cell as Floorplanned_tlu:

Select Cell Save As … Enter Floorplanned_tlu for Cell Name Click “OK”

8. Exit Astro without saving:



Lab 2

Background Part B: Timing Setup with TLU+ models

In Part A, you executed the steps required to perform Timing Setup for a design in a pre-CTS stage, using TLU models.

In Part B, you will perform Timing Setup on the same design as in Part A, using the same constraints, but using TLU+ models instead. Astro handles TLU+ models differently than TLU models.


Lab 2




lab2/


con2.sdc Timing constraints file

design_lib_tlup/ ORCA physical design library w/ TLU+ models that contains a Floorplanned cell to be used by this lab



ref_lib/ Link to I/O, core and macro reference libraries

star_rcxt/ Contains parasitic TLU+ model files:

cb13_4m_*.tluplus TLU+ models for three operating

corners (* = min, typ and max)

cb13_4m_*.itf Interconnect technology files

cb13_4m.map Layer mapping file


Lab 2

Lab 2B Instructions

Task 1. Open Library and Cell


unix% cd lab2

unix% Astro –log logs/timing_setup_tlup.log &

2. Open the existing design library called design_lib_tlup:

Select Library Open … Enter design_lib_tlup for Library Name Click “OK”

3. Open the existing cell Floorplanned:

Select Cell Open … Enter Floorplanned for Cell Name Click “OK”

Task 2. Perform timing setup with TLU+ models

TLU models are included in the technology file. When a library is created the technology file is read in and the TLU models are attached to the library. TLU+ models are NOT part of the technology file. The TLU+ models are generated by the parasitic extraction tool StarRCXT (or more precisely: grdgenxo), and reside in a binary .tluplus file. This file, along with an Interconnect Technology (.itf) and a Layer Mapping (.map) file are read into Astro and attached to the library using the cmItfToTLUPlus command.

Note: This lab will not cover how to create the TLU+ models. If interested, refer to the lecture notes and the job aid to see how this is done.

Use Job Aid “C” to perform the following steps:

1. Attach TLU+ models (min, typ, max) to the design_lib_tlup library. The models have been generated for you; there is no need to regenerate them.

Note: The file locations are listed on the previous page. Remember to include the star_rcxt directory path.


Lab 2

Normally both MIN and MAX are applied. For this step, use only NOM (typ) since TLU+ is ignored anyway during timing sanity check.

Attention: You will be using a different set of menus in the Astro GUI. Using the menu command “Tools Data Prep” you activate a second set of menus, which include, among others, the TLU+ attach function.

2. Load the design_data/con2.sdc constraints file.

Note that to get back to the original Astro menus and being able to access the “Timing” menu, you have to use “Tools Astro”.

3. Apply timing setup options.

Make sure Model tab has Operating Condition set to “MAX”.

4. Verify that the constraints are complete.

5. Perform a timing sanity check.

Question 9. What is the resulting slack? ....................................................................................................

Note: You should get a positive slack at this point. If you did not, verify that your Timing Setup Panel settings have been applied correctly, (i.e.. Ignore Interconnect = ON).

Question 10. Can you explain why the TLU+ timing sanity slack is exactly the same slack as with TLU models? ....................................................................................................

6. Save the cell as Floorplanned_tluPLUS:

Select Cell Save As … Enter Floorplanned_tluPLUS for Cell Name Click “OK”



Congratulations! You have completed Lab 2. The design is now ready for Placement.



Answers / Solutions

Question 1. From what you learned during lecture, what steps should be performed before running a timing sanity check?

Apply the SDC, ensure the correct Table lookup model is loaded, set “Ignore Interconnect” in the timing setup panel, set the correct pre-CTS options.

Question 2. What is the worst setup slack that is reported in the Message/Input Area?

~ -16.7 ns

Question 3. What is the worst slack after loading the sdc file?

~ -14.16 ns

Question 4. What is the recommended step to be performed before loading an sdc constraints file?

Clear the old constraints – ataRemoveTC

Question 5. Which wire delay model should be used pre-CTS, Elmore or AWE? Why?

Elmore. Before routing, there is no actual interconnect between cells. The interconnect lengths are estimated using a Steiner orthogonal route. The AWE model is a very accurate, but a more CPU-intensive timing model compared to Elmore. Before route, it is therefore recommended to use the faster Elmore model. AWE should be enabled after routing is performed.

Question 6. Which wire delay model should be used to perform a Timing Sanity Check?

This is a trick question. The answer is “it doesn’t matter!” During a timing sanity check, you ignore the effects of the parasitic interconnect by setting Rnet and Cnet to zero. The wire delay model should be ignored for the timing sanity check analysis.



Question 7. Should Astro use Propagated or Ideal clocks pre-CTS? Why?

Ideal. Propagated clocks should be ignored pre-CTS because there are no clock tree buffers in place yet. The clock tree latencies and skews are estimated by the sdc constraints pre-CTS. After CTS, the constraints should be ignored and Astro should be directed to calculate the actual propagated clock delays.

Question 8. What is the slack reported after setting up the Timing Setup panel for a pre-CTS timing sanity check?

~1.98 ns

Question 9. What is the resulting slack?

~1.98 ns

Question 10. Can you explain why the TLU+ timing sanity slack is exactly the same slack as with TLU models?

A timing sanity check is performed while ignoring the interconnect parasitic effects from the TLU/TLU+ models.


Placement

PlaSyn

3

Learning Objectives


During this lab, you will perform standard cell placement and congestion optimization. Reports will be generated to monitor and track the progress of the design.


• Set options for running automatic placement

• Perform Pre Placment optimization

• Place standard cell instances

• Perform Post Placement optimization

• Analyze and resolve placement congestion

• Generate timing analysis reports

cement Lab 3-1 opsys 20-I-022-SLG-003

Lab 3

Background

The purpose of this lab is to familiarize you with the fundamental placement steps, which outline the recommended flow through Astro. The lab is divided into a series of tasks where various optimizations along with analysis and observations will be performed. This lab uses a suboptimal floorplan to show congestion problem.

Lab 3-2 Placement Synopsys Astro 1

Lab 3




lab3/ .avntrc User defined settings/functions design_data/ Contains the ORCA design input data:

trace_scan.cmd Command file to trace ORCA scan chain

design_lib_orca/ ORCA physical design library that contains the Timing_Setup cell to be used by this lab

reports/ Astro report files generated during this lab


The following directories and files will be

accessed during this lab: ref_lib/ Link to I/O, standard cell and macro designs star_rcxt/ Link to parasitic TLU+ model files



Placement Lab 3-3 Synopsys Astro 1

Lab 3

Lab 3 Instructions

Task 1. Open Cell


unix% cd lab3 unix% Astro –cmdd logs/ORCA –logd logs/ORCA &

2. Examine the file .avntrc file located in the current directory, lab3.

Starting with this lab, a personal “.avntrc” file was added to the directory structure. Astro automatically reads this file upon invocation. The file can contain configuration options, user-defined functions, etc. A number of timesaving functions were added to .avntrc file, which are going to be used during this and upcoming labs.

The Message/Input Area indicates what exactly was configured, and what functions were added.

3. Open the library named design_lib_orca.

Select Library Open … Enter design_lib_orca for Library Name Click “OK”

4. Open the cell named Timing_Setup.

Select Cell Open … Enter Timing_Setup for Cell Name Click “OK” Note: This design has already gone through design setup,

floorplanning and timing setup steps and is ready for standard cell placement.

Observe where the macros are placed and the straps are built. There are also placement blockages over the macros to prevent Astro from placing standard cells there. (Indicated by the yellow X symbols)


Lab 3

Question 1. Are the straps defined to match their preferred routing direction? (Hint: M1 preferred routing direction is horizontal) .................................................................................................... ....................................................................................................

Note: The floorplan is purposely designed this way in order to see the impact of poor floorplanning and /or poor Power/Ground grid planning.

Task 2. Trace and Detach Scan Chains

As discussed in lecture, scan chains in the design can make placement and routing harder, because poor scan chain connections lead to higher congestion. This is why scan chains should be disconnected before placement, then optimized and reconnected after clock tree synthesis. Before disconnecting the scan chains, they first need to be identified by Astro. Astro will need to be told where the scan chains start and end; this is called “tracing” a scan chain.

1. To trace the scan chains, execute the provided script:

load "design_data/trace_scan.cmd"

Note: This script was generated by Design Compiler and would typically be provided along with the gate-level netlist from synthesis.

The script contains the command axgScanTrace (PrePlace Scan Chain: Trace Scan Chain…), which is used to identify each scan chain.

2. Delete the scan chains:

Select PrePlace Scan Chain: Optimize/Delete Scan Chain … Click on “Default” Click on “Delete only” mode Click “OK”


Lab 3

Task 3. Set Automatic Placement Options

Astro can place cells in many different ways. Before running optimization or cell placement, specify the options Astro should use when placing cells.

1. Configure Astro to perform congestion and timing-driven placement:

Select InPlace Placement Common Options … Click on “Default” Click on “Timing” under Optimization Mode Click “OK”

Remember to also verify the correct pre-CTS settings on the “Enviroment” tab of the Timing Setup Panel as done in lab 2 (Timing Setup).

Task 4. Perform Pre-Placement Optimization

Pre-placement optimization is done for overall timing improvement. It addresses high-fanout nets, area recovery, and some optimization. The goal here is to generate a “seed” netlist for placement.

1. Perform default Pre-Placement Optimization with Remove Buffers option:

Select PrePlace Pre-Placement Optimization … Click on “Default” Select “Remove Buffers” under Design Cleanup:Area Recovery Click “OK”

Note: Enabling “Remove Buffers” may lead to a better result.

Scan the log for WARNING and ERROR messages then watch for the completion string: “done pre-placement netlist optimization”. The run time is approximately 1½ minute.

2. Save the cell as PrePlaced.

3. Generate and review a “check design” report with the following command:

astCheckDesign

Save the report to “reports/PrePlaced.chkdsn”.

Open the report and record Ideal (Ignore Interconnect Timing) and PrePlaced (Include Interconnect Timing) slacks in Table 1 on page 3-11.


Lab 3

Question 2. Does this design pass the “timing sanity check”? .................................................................................................... . ...................................................................................................

Question 3. Did high-fanout net synthesis buffer the clock nets? Hint: Read carefully and think about what HFN synthesis does). ....................................................................................................

Task 5. Place the Standard Cell Instances

Unlike PrePlace, which places cells based on congestion mode only, this placement step will use all selected optimizations and placement modes.

1. Perform standard cell placement with the following settings:

Select InPlace AstroPlace: Design Placement … Click on “Default”

Verifying that the placement Mode is set to “congestion + timing” driven as set in the Placement Common Options (Task 3)

Enable “In-Placement Optimization” This option improves the total negative setup slack (TNS) and resynthesize high fanout nets (HFN)

Click “OK”

Scan the log for WARNING and ERROR (there should not be any) messages then watch for the completion string: “AstroPlace completed successfully”. The run time is approximately 2 minutes.

2. Save the cell as Placed.

3. Generate and review a design check report named reports/Placed.chkdsn.

Record the results on the Placed row in Table 1.

Question 4. Will In-Place Optimization optimize hold time? ....................................................................................................


Lab 3

Task 6. Analyze Congestion

After placing the design, you should analyze the congestion. By default, a placement congestion map is generated along with the critical path information in the cell window. The congestion map analysis will give hints on what steps to perform next.

1. Turn off critical path information:

Select InPlace Placement Maps: Display Timing Map … Click on “Clear” Click “Cancel”

It is still difficult to analyze the congestion map due to all the elements being displayed. You could configure the “Window option” panel and disable the visibility of cells, rows, rails, etc.

Instead, use a function that was defined in the .avntrc file that turns off the visibility of cells, rows, and rails.

2. Enter the following function in the Message/Input Area:

set_congestion_view

3. Analyze the congestion by zooming in to hot spot areas and notice the overflows information.

Notice that the colors do not correspond to a classical “heat map”; another function was created for you to change that.

4. Enter the following function in the Message/Input Area:

pl_congestion_map

The above function assigns different colors to the various overflows. Analyzing the map should be easier now.

Question 5. Is the congestion acceptable? Can the design be easily routed? ....................................................................................................


Lab 3

Task 7. Search & Refine

1. Try to reduce congestion with the Search and Refine:

Select InPlace AstroPlace: Search and Refine … Click on “Default”

Click “OK”

2. Save the cell as PlacedandRefined.

3. Reevaluate the placement congestion map.

Question 6. Has the congestion been relieved; can the router route without problems? Explain a possible root cause for each of the congestion hot spots. .................................................................................................... .................................................................................................... ....................................................................................................

Question 7. What is the chip utilization (Cell/Core Ratio) of the design? (Hint: Use Query List PR Summary !). ....................................................................................................

At this point it might be useful to generate a more accurate, global routing congestion map.

A function was created to perform this step and assigns the preferred heat-map colors to the global routing congestion map.

4. In the Message/Input Area type:

gr_congestion_map

Note: gr_congestion_map was defined using Route Global Route: Estimate Global Route Congestion! to generate estimate GR congestion map and Route Global Route: Display Congestion Map to display and assign the preferred heat-map colors.

Question 8. How does the global route congestion map compare to the placement congestion map? .................................................................................................... ....................................................................................................


Lab 3

5. Turn on visibility for cells, straps etc again, execute the following user-defined function in the Message/Input Area:

unset_congestion_view

6. Generate and review a design check report named reports/Refined.chkdsn. Record results on the Refined row in Table 1.

Task 8. Perform Post-Placement Optimization Phase 1

Even though the design has shown congestion problems, you should complete all placement steps. The post-placement phase 1 optimization will perform further setup optimization and fix max transition and max capacitance violations. Since this optimization step can use global routing information during optimizations, it is possible that congestion is further reduced.

1. Execute a Default PPO 1 with "Use Global Routing" for better accuracy.

Select PostPlace Optimization: Post-Place Optimization Phase 1 … Click on “Default” Select “Use Global Routing” for better accuracy Note: Do not redo HFN synthesis since this was run during

Placement with IPO option enabled. Running it again will not provide any more benefit but will increase runtime.

Click “OK” The run time for PPO 1 is approximately 2½ minutes.

2. Save the cell as PPO1.

3. Generate and review a design check report named reports/PPO1.chkdsn. Record results on PPO1 row in Table 1.

Question 9. Have setup time, max transition and max capacitance improved? ....................................................................................................

4. Generate a timing report for detailed timing analysis:

Select Timing AstroTime: Timing Report … Click on “Default” Select “Max Trans” & “Max Cap” options to show those violations too Select “Show Histogram” Click “OK”


Lab 3

Question 10. Other than the timing violations, are there any other violations? ....................................................................................................

Question 11. Why is it better to fix as many of the transition and capacitance violations as possible now, as opposed to later? .................................................................................................... ....................................................................................................

5. Analyze Congestion again.

Use the user-defined function “gr_congestion_map” to update the Global Route congestion map since it is not up dated automatically.

Do not forget to make the congestion map visible by using the function set_congestion_view.

6. Close and discard the current CEL as its floorplan causes congestion problems that cannot be fixed with Search and Refine.

You will use a different floorplan to implement ORCA design in the next lab.


Select Tools Quit Click “OK” Select “Discard All” when prompted to Save Cells Click “OK”

The design is now ready for CTS!

Table for recording the optimization progress Record the delays and the number of timing, transition and capacitance violations for each step. The expected values can be found in the back for comparison.

Setup Slack / # viol

Hold Slack / # viol

Num Trans

Num MaxCap

Ideal

PrePlace

Placed

Refined

PPO1

Table 1



Answers / Solutions

Question 1. Are the straps defined to match their preferred routing direction? (Hint: M1 preferred routing direction is horizontal)

The preferred routing directions are M2:vertical, M3:horizontal and M4:vertical. The vertical straps are on M3 and the horizontal strap is on M4. They do not match their preferred routing direction. For a technology with few routing metal layers, this could be a problem. The problem with these straps is that they will prevent Astro from routing across the straps on M3 and M4. Astro must cross the straps using the available M1 and M2. For more detail discussion on this issue, take a look at the Appendix B at the end of Floorplanning lecture Unit 6.

Question 2. Does this design pass the “timing sanity check”?

No, the ideal slack is a small negative. It is possible that later optimizations will overcome a small negative slack.

Question 3. Did high-fanout net synthesis buffer the clock nets? No, high-fanout net synthesis buffers data nets only. Clock nets are buffered during clock tree synthesis (CTS).

Question 4. Will In-Place Optimization optimize hold time?

No, hold time fixing is done later during Post Placement Optimization phase 2 (PPO 2) discussed in lecture/lab 4.



Question 5. Is the congestion acceptable? Can the design be easily routed?

The floorplan is not optimal, but possibly workable if congestions can be reduced. The congestion between the RAM macros on the bottom suggests that they should be spread apart to lessen the routing congestion in the channels. There is also very bad congestion along the vertical straps that are definitely a problem if not resolved. One way to reduce the congestion under the vertical straps is not to place standard cells there. The Search and Refine function can also be tried to remove congestion.

Question 6. Has the congestion been relieved; can the router route without problems? Explain a possible root cause for each of the congestion spots.

Congestion has improved a little but not enough that this placement can be routed successfully. The channels between the RAMs still have congestion even though no standard cells were placed there. Congestion along the vertical straps will cause nets to make many detours as they try to run horizontally. With the existing congestion conditions, this design with its current floorplan will experience difficulty and may not route successfully. The floorplan should be modified so that congestion is reduced or eliminated at the end of Search and Refine. One way to modify the floorplan is to give the channels between the RAMs more room and not to place standard cells in the channels. The other flaw that should be corrected is to change the vertical straps to M4 and the horizontal strap to M3 so they match the preferred routing directions. More detail on the topic of floorplanning will be discussed in a later unit.

Question 7. What is the chip utilization (Cell/Core Ratio) of the design? (Hint: Use PR Summary).

The utilization of the design for Cell/Core Ratio is approximately 56%. This indicates that there are enough room placement blockages to be added (not having standard cells placed there) in the new floorplan to remove congestion.

Question 8. How does the global route congestion map compare to the placement congestion map?

The global congestion map looks somewhat worse than the placement congestion map. It is more accurate though, and should be taken seriously. All the problems you saw earlier are more pronounced now.



Question 9. Have setup time, max transition and max capacitance improved?

Yes, a little bit, possibly because of the congestion issues.

Question 10. Other than the timing violations, are there any other violations?

Yes, there are a large number of max transition and max capacitance violations. Most of these are prefixed with a “NDT’ attribute, which means “Don’t touch net” according to the legend at the top of the timing report. These nets are “don’t touch” since they represent the “logical” connection between the pad pin of the IO Pads and the design Input/Output ports. In the physical domain, there is no such net. The IO pads can drive capacitance well in the 100 pf range, you can therefore disregard the violations on the NDT nets. Astro marks them as violations, because by default the maximum allowed transition and capacitance is 2 ns and 2 pf respectively. (See the Optimization tab of the Timing Setup Panel) There are a few nets that exhibit violations that are not NDT. Due to the small number of real violations, these can be addressed during PPO2.

Question 11. Why is it better to fix as many of the transition and capacitance violations as possible now, as opposed to later? Fixing transition and capacitance violations before CTS ensures that clock tree synthesis is based on a netlist that will not see drastic changes later, which would mean that clock tree optimization needs to be rerun later.

Table for recording the optimization progress

Setup Slack / # viol

Hold Slack / # viol.

# Tran viol.

# Cap viol.

Ideal 0.400 0 -1.021 58 50 115

PrePlaced -2.327 178 -0.934 30 412 127

Placed -0.125 29 -0.986 30 260 123

Refined -0.124 33 -0.986 30 232 123

PPO1 0.062 1 -0.986 30 60 115

Table 1


CTS and Post Place

Optimizations

CTSSyno

4

Learning Objectives


During this lab, you will perform standard cell placement and clock tree synthesis along with optimizations. Reports will be generated to monitor and track the progress of the design.


• Set options for post placement optimizations and clock tree synthesis

• Perform Post placement optimization steps

• Synthesize the clock trees

• Generate and analyze design, timing and clock skew reports

and Post Place Optimizations Lab 4-1 psys 20-I-022-SLG-003

Lab 4

Background

The purpose of this lab is to complete the fundamental Placement + CTS step that was started in the previous lab. In the previous floorplan (lab 3), the routing congestion has not improved enough and would make it difficult to route later on. This lab uses the modified and improved floorplan to resolve problems found in a previous lab. The new floorplan has the same chip area but the RAMs are moved apart to remove congestion in the narrow channels. The vertical and horizontal straps are changed to M2 and M3 respectively to match the preferred routing direction. There is also a soft placement blockage located between the Register File RAMs and the SD RAMs near the lower left area.

Do not worry about how to modify the floorplan; the details will be covered in the Floorplanning unit. The important thing to notice is how the changes will effect the congestion.

At the end of the placement step using the new floorplan, you will continue on to build the clock tree for the ORCA design. There are also preparation steps that need to be completed before the clock trees can be built correctly.

There are two optional tasks (Task 1 and Task 8). Each takes about 15 min to complete. You will need a total of 120 min to complete the entire lab including the optional parts.

Lab 4-2 CTS and Post Place Optimizations Synopsys Astro 1

Lab 4




Lab4/ .avntrc User defined settings/functions scripts/ clock_sync.cmd Clock tree exceptions


trace_scan.cmd Command file to trace ORCA scan chain

design_lib_orca/ ORCA physical design library that contains Timing_Setup and Ready_for_PPO1 cells to be used by this lab

reports/ Astro report files generate during this lab






CTS and Post Place Optimizations Lab 4-3 Synopsys Astro 1

Lab 4

Lab 4 Instructions

To reinforce Placement and Optimization steps learned in a previous lab, you will repeat the steps in Task 1 of this lab. To assist you use job aid “D” which has been provided for you.

Note: If you are not interested in repeating the Placement steps, you can start this lab from Task 2 below.

Task 1. Optional: Perform Placement on the Improved Floorplan

Use job aid “D” to perform the following steps in this task. If you get stuck, you can refer to the detailed instructions in lab 3.

1. Start Astro from the lab4 directory.

Make sure you log the output and the commands.

2. Open the library design_lib_orca.

3. Open the cell named Timing_Setup.

This design is ready for placement.

4. Trace all scan chains using provided design_data/trace_scan.cmd file.

5. Delete all scan chains.

6. Set placement options to Default and enable the Timing option.

To further reduce congestion under the straps, instruct Astro not to place standard cells under any preroute straps (M1, M2 and M3).

To add a placement constraint for not placing cells under the vertical and horizontal straps (M3, M4): click on InPlace Placement Common Options and select M3 and M4 under “No Cells under Preroute of”, then click OK to accept the settings.

7. Perform PrePlace Optimization using Default settings with Remove Buffers option.

8. Save the cell as PrePlaced.


Lab 4

9. Generate and save a check design report to reports/PrePlaced.chkdsn.

Note: Instead of astCheckDesign, you can use the following user-defined function check_design defined in your .avntrc file.

check_design "reports/PrePlaced.chkdsn"

check_design will create an astCheckDesign report saving it to the given file. A similar user-defined function is called report_timing with the same syntax as above.

Record Ideal (Ignore Interconnect Timing) and PrePlaced (Include Interconnect Timing) slacks in Table 1 on page 4-12.

10. Perform Standard Cell Placement using Default settings with the In-Placement Optimization option.

11. Save the cell as Placed.

12. Generate a summary report and record Placed results in Table 1.

ataReportSummary

13. Analyze the design using a global route congestion map.

Use the provided user-defined functions “gr_congestion_map”, followed by “set_congestion_view” to see the congestion map.

14. Try to reduce congestion with the “Search and Refine” function using Default settings.

15. Save the cell as “Refined”.

16. Generate a summary report and record the Refined results in Table 1 on page 4-12.

Note: S&R attempts to improve the congestion but stops quickly since improvements cannot be found for the current placement.

Question 1. Has the congestion improved and is timing the same or better compared to the floorplan used in lab 3? Has run-time improved for both placement and S&R? .................................................................................................... ....................................................................................................


Lab 4

Task 2. Load the Refernce “Placed” CEL

If you performed the optional Task 1 above then skip this task and continue with Task 3 below. The following steps will load a reference design that has already been completed using instructions from Task 1 above.


Make sure you log the output and the commands.


3. Open the cell named Ready_for_PPO1.

This cell is the equivalent to “Refined” cell saved in the optional Task 1 above.

Task 3. Perform PPO1

1. Execute a default PPO1 with the “Use Global Routing” option.


3. Generate a summary report and record PPO1 results in Table 1 on page 4-12.

Question 2. Explain how the new floorplan makes it possible to eventually eliminate congestion while improving timing at the same time? .................................................................................................... ....................................................................................................

.....................................................................................................

.....................................................................................................


Lab 4

Task 4. Preparing for Clock Tree Synthesis

CTS is the process of buffering all the endpoints connected to the clock source point or root, and balancing the skew between the endpoints. Running the default CTS is not sufficient; every design has special requirements for the clock tree.

Before synthesizing the clock tree, Astro needs to know all the endpoints of this tree, which by default are register clock pins. If there are additional pins that need to be balanced along with the register clock pins, Astro needs to be explicitly told about them. One example is shown in Figure 1.

Figure 1. PLL hook up

The clock tree drives the register clock pin, as well as the FB (feedback) pin of the PLL (Phase Locked Loop), and their delays should be balanced, so the PLL can compensate the clock waveform with the right phase shift (i.e. remove the clock insertion delay for the i/o paths). If the FB pin is defined as a “clock” pin in the library (where this component came from) then there would be nothing for you to do. This is not the case with your library; the FB pin is simply an “input” pin of the PLL. If nothing is done, you will see the following warning in the log during CTS:

WARNING : I_CLOCK_GEN/I_PLL_SD:FB_CLK is an implicit ignore pin since it is a stop pin

This means that Astro will ignore this pin for CTS purposes.

There are two items in this design that will require your attention: The PLLs, and the SDRAM DDR (Double Data Rate) interface.


Lab 4

1. To consider the FB pin as a clock endpoint, you need to make it a “sync” pin. Enter the following command on the same line, including the single quote:

ataDefineSyncPin (geGetEditCell) "I_CLOCK_GEN/I_PLL_SD" '(("FB_CLK" "rr" 0 0 0))

Please check the online help or the lecture for the details on the various parameters of ataDefineSyncPin command.

2. Repeat the previous step for another instance: “I_CLOCK_GEN/I_PLL_PCI”.

A similar problem needs to be addressed on the SDRAM DDR interface. The interface can be simplified as shown in the following diagram:

Q

CLK D0

D1Q

CLKSDRAM_CLK

DQ_out_0_reg[0]

DQ_out_1_reg[0]

sd_DQ[0]PADI

OEN

PADI sd_CK

I_ORCA_TOP/I_SDRAM_IF

ORCA

sdram_DQ_iopad_0

sdram_CK_iopad

Clock Gating Checks

SD_DDR_CLK

D1

D0

Q

CLKsd_DQ_en_reg[0]

Y

Y

S

S

D0

D0

sd_mux_CK

sd_mux_DQ_out_0

I_CLOCK_GEN/I_PLL_SD

clk

Figure 1. SDRAM DDR Interface

The clock SDRAM_CLK is connected directly to the select pins of muxes that in turn drive the output PADs. This is done because of the tight timing requirement of the DDR SDRAM interface, which can produce data at its output data port on both the rising and the falling clock edges. The select pins will be marked as implicit ignore pins automatically, so you need to define them as explicit sync pins like the ones for PLLs.

The syntax for applying the sync pin attribute is the same as in step 1, but you would have to repeat the process 16 times for every bit in the SDRAM port, plus 2 for the chip generated SDRAM outgoing clock; therefore a script is provided to help you.


Lab 4

3. Look at the script, then execute it in Astro:

load "scripts/clock_sync.cmd"

This completes setting up the design for clock tree synthesis.

4. Save the cell as Ready_for_CTS.

You will need this cell for an optional task at the end of the lab!

Task 5. Execute Default Clock Tree Synthesis

1. Set default options in Clock Common Options:

Select Clock Clock Common Options … Click on “Default”

Click “OK”

Question 3. What is the target skew and latency? (Hint: values can come from the SDC or from this dialog box) .................................................................................................... ....................................................................................................

2. Run the default Clock Tree Synthesis:

Select Clock Clock Tree Synthesis: Clock Tree Synthesis … Click on “Default” Click “OK”

3. STA requires that the explicit sync pins constraint be removed. Remove clock constraint applied earlier with ataDefineSyncPin by entering the following command:

ataPurgeSyncPin (geGetEditCell) "*"


Lab 4

4. Generate and review a Default skew analysis report:

Select Clock Reports: Skew Analysis … Click on “Default” Enter “PCI_CLK, SDRAM_CLK” as Clock Names Select output to File and enter “reports/CTS_skew.rpt” as file name Click “OK” Record the following entries for the SDRAM and PCI clocks using CTS_skew.rpt file:

Table A

Global Skew Longest Delay Shortest Delay

SDRAM_CLK

PCI_CLK

Task 6. Post CTS Timing Analysis

1. After CTS, change the settings in the Timing Setup Panel to use the actual clock delay information instead of the ideal clock for timing analysis and fspost-CTS optimization to follow. (Use the back side of job aid “D” to verify).

Select Timing AstroTime: Timing Setup … Click Parasitics tab Make sure "Max" and "Min" are set for “Operating Cond”. Select “Apply” Click Model tab Make sure "Max" and "Min" are set for “Operating Cond” and Make sure Elmore is set for Delay Model. Select “Apply” Click Optimization tab Set the “Target Hold Slack” to 0.1. Select “Apply” Click Enviroment tab Select “Ignore Clock Uncertainty”, “Enable Mixed Clock/Signal Edges”, “Enable Recovery/Removal Arcs”, “Enable Clock Gating Checks” Unselect “Ignore Propagated Clock” and “Enable Ideal Network Delay” Select “Apply” Click “Hide” to close the Timing Setup Panel.

2. Save the cell as CTS.

3. Generate a report using ataReportSummary and record the results for CTS in Table 1 on page 4-12..

4. Reconnect and optimize the scan chains:

Select PrePlace Scan Chain: Optimize/Delete Scan Chain … Set Mode to “Optimize” Click “OK”


Lab 4

5. See the Message/Input Area for the Initial and Final wire length numbers for the six scan chain groups ScanGroup_pad_iopad_0 through 5.

Note: There are about 3x reduction in wire length after scan chain optimization. This generally translates into an easier to route design!

6. Generate a report using ataReportSummary and record the results for the Scan Optimize row in Table .

Task 7. Perform Post-Place Optimization Phase 2

Even if setup or hold timings are fine in your design at this point, performing PPO2 can still have advantages. Specifically, PPO2 can perform area recovery, which may simplify the subsequent routing steps.

1. Run a default Post-Place Optimization Phase 2 with Remove Buffer option:

Select PostPlace Optimization: Post Placement Optimization… Click on “Default” Select the “Remove Buffers” option Click “OK”

At the completion of this step, you should see the string “* PPO Finished”. The runtime is approximately 1½ minutes.


3. Generate a report using ataReportSummary and record the results for the PPO2 row in Table .

Notice the large number of max transition and max capacitance violations. If you generate a detailed timing report, you can observe that most of these are prefixed with a “NDT’ attribute, which means “don’t touch net”. These nets are “don’t touch” since they represent the “logical” connection between the pad pin of the IO Pads and the design Input/Output ports. In the physical domain, there is no such net. The IO pads can drive capacitance well in the 100 pf range, you can therefore disregard the violations on the NDT nets. Astro marks them as violations, because by default the maximum allowed transition and capacitance is 2 ns and 2 pf respectively. (See the Optimization tab of the Timing Setup Panel). At this point if you wanted to do more optimizations on the clock tree you could use the Astro Clock Tree Optimization (CTO) routine. This is not necessary for this design.

4. For a more accurate congestion analysis, generate the Global Route congestion map:

Select Route Global Route: Global Route… Select the “congestion map only” option Click “OK”


Lab 4

Question 4. Does congestion still exist in the RAM channels and under the vertical straps? ....................................................................................................

Note: Make sure the standard cells are visible. Answer the following questions.

Question 5. Are there any cells placed under M3 or M4 straps, or in the hard placement blockages? ....................................................................................................

Question 6. Did Astro place any cells in the soft blockage area between the rams in the lower left corner of the design? ....................................................................................................

5. If you finished and have at least 15 min to spare, you should try the optional task below without exiting the Astro. You can exit Astro if you are not going through the optional task:

Select Tools Quit Click “OK” Select “Discard All” when prompted to Save Cells Click “OK”

You have taken a design through placement and CTS.

Table for recording the optimization progress Record the delays and the number of timing, transition and capacitance violations for each step. The expected values can be found in the back for comparison.

Setup Slack # viol

Hold Slack # viol

Num Trans

Num MaxCap

Ideal

PrePlace

Placed

Refined

PPO1

CTS

Scan Optimize

PPO2

Table 1 Lab 4-12 CTS and Post Place Optimizations

Synopsys Astro 1

Lab 4

Task 8. Optional: Improve Clock Tree Skew & Insertion Delay

In most cases it is very important to reduce the skew and the insertion delay in clock trees. By reducing the skew, meeting setup timing becomes easier, and by reducing the insertion delay, input/output non-PLL paths are easier to implement.

Often, before CTS has been run, there might be buffers in the clock tree that can degrade the quality of the final clock tree with regards to insertion delay and skew optimization.

In this task you will learn how to analyze existing clock tree structures, and how to clean up the clock tree to give CTS the most flexibility.

1. Close and discard the current open cell:

Select Cell Close … Click “Discard All” Click “OK”

2. Open the saved cell Ready_for_CTS.

3. Activate the Interactive CTS:

Select Clock Adv Clock Tree Management: Interactive Clock Tree … You should see the following:

4. Type the name of the clock you want to edit in the field shown above, SDRAM_CLK, and select “Load” to initialize the dialog box with the clock information.

When the clock tree is loaded, you will see all the cells that belong to it in the lower panel of the dialog box.


Lab 4

5. Once the clock is loaded and displayed, select the “Info” tab.

You will notice that by default you do not see the reference or Master names of the cells, so it will be hard to determine what elements in an existing clock tree you can remove.

6. Enable the “Master Name” and select the 3 elements (click-hold-drag the mouse over the elements) between the PLL and the first register then click on “Display” button.

You should now see the master names “mx02d0” and “bufbd7”.

Look at the “iCTS” window, the two back-to-back bufbd7 buffers are common to all FFs (all the FFs are driven by these buffers) and can be deleted.


Lab 4

7. Select the “ECO” tab.

This is where you can make changes to the existing clock tree.

Select the two bufbd7 cells and delete them.

Note: this screenshot shows one buffer has already been deleted!

8. Repeat the above procedure with PCI_CLK (steps 4 through 6).

Note: You have to “Clear” the current clock first (on the Data tab), before you can load a new one.

Cancel the iCTS dialog box when complete.

Modifying the clock tree using iCTS caused Astro to mark the clock as synthesized.

9. Reset the CTS synthesized flag for all clocks:

Select Clock Utilities: Mark Clock Tree … Click “Reset Net Synthesized flag” Click “OK”


Lab 4

Question 7. What one step do you have to do for this design before CTS can be run correctly? . ................................................................................................... . ...................................................................................................

10. Run clock tree synthesis as shown before (or use your job-aid for help)

11. Analyze the clock skew for the clocks SDRAM_CLK and PCI_CLK and compare to the results from the previous run in Task 5.

Table B

Skew Longest Delay Shortest Delay

SDRAM_CLK

PCI_CLK

Question 8. Was there any improvement in skew and/or insertion delay? ....................................................................................................

12. Display the clock tree structure graphically in the Cell window.

Invoke iCTS Click Data tab and load SYS_CLK Click Browse tab then click “Select Buffers” Click Cross-Probe tab then unselect “cell” option and select “output” Click “Highlight” button.

The Cell window should display flylines between the clock buffer outputs (selected from the Browse tab) with a different color code for each level of buffer in the clock tree structure.

To remove flylines and cancel iCTS:

Click Unhighlight button Click Cancel to close iCTS dialog box.



Answers / Solutions

Question 1. Has the congestion improved and is timing the same or better compared to the floorplan used in lab 3? Has run-time improved for both placement and S&R?

Question 2. The congestion is virtually eliminated while timing has also improved. This design is ready for the next step. You should have also noticed of the short run-time of the “Search and Repair” optimization since the improvement is not required.

Question 3. Explain how the new floorplan makes it possible to eventually eliminate congestion while improving timing at the same time?

Since vertical and horizontal straps are defined with their preferred routing directions, Astro can route the standard cells with less interference from the straps, hence lowering the congestion. The congestion under the vertical straps is greatly reduced since you told Astro not to place standard cells there. The new floorplan also moves the RAMs apart thereby providing more routing resources in the channels.

Question 4. What is the target skew and latency?

If you look at the SDC file, you will notice the clock uncertainty settings. During the lecture you learned these values would not be taken into account by default. By default Astro uses the value from the Clock Common Option dialog box 0.

Latency: there is one clock that has a latency value associated with it – SD_DDR_CLK. CTS will try to build a latency of 2 ns on that clock.

Record the following entries for the SDRAM and PCI clocks:

Table A

Global Skew Longest Delay Shortest Delay

SDRAM_CLK 0.040 1.081 1.041

PCI_CLK 0.139 1.208 1.069



Question 5. Does congestion still exist in the RAM channels and under the vertical straps?

No.

Question 6. Are there any cells placed under M3 or M4 straps, or in the hard placement blockages?

No.

Question 7. Did Astro place any cells in the soft blockage area between the rams in the lower left corner of the design?

Yes. If you zoom into the soft blockage area, you will notice a few buffers that “slipped” into that area, which is completely legal.

Question 8. What one step do you have to do for this design before CTS can be run correctly?

Define the sync pins. You can run the following command as it defines all the required sync pins.

load "scripts/clock_sync.cmd"

Table C

Skew Longest Delay Shortest Delay

SDRAM_CLK 0.044 1.027 0.983

PCI_CLK 0.138 1.119 0.981

Question 9. Was there any improvement in skew and/or insertion delay?

The clock skew should be about the same, but the insertion delays have improved up to 89 ps for PCI clock.



Table of the resulting optimization progress

Setup Slack # viol

Hold Slack # viol

Num Trans

Num MaxCap

Ideal 0.401 0 -1.021 58 50 115

PrePlaced -0.739 126 -0.904 30 2227 128

Placed -0.096 4 -0.946 30 248 125

Refined -0.096 4 -0.946 30 248 125

PPO1 0.027 0 -0.946 30 60 115

CTS 0.302 0 0.014 0 60 115

Scan Optimize 0.170 0 0.023 0 60 115

PPO2 0.109 0 0.100 0 44 116

Table 1



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Design Setup

DeSyn

5

Learning Objectives



• Verify that all required input data files and models are available prior to beginning the setup steps

• Adding .LM view to a Milkyway library

• Describe what each setup step does and why it is needed

• Identify if some of the order-dependent steps were skipped or done out of sequence, and then correct the problem (e.g. reading netlist before creating lib; expanding before attaching ref libs)

sign Setup Lab 5-1 opsys 20-I-022-SLG-003

Lab 5

Background Lab 5A Design Setup

The purpose of lab 5A is to explore what the necessary design setup steps are, what they do and why you need to do them. You will also familiarize yourself with the menus/commands, and the resulting GUI views and UNIX data structures.

Lab 5-2 Design Setup Synopsys Astro 1

Lab 5


All files for this lab are located in the lab5a directory under your home directory.

The following directories and files will be used or created in this lab:

Lab5a/ design_data/ Contains the ORCA design input data:

orca.v ORCA design Verilog netlist

design_lib_orca/ ORCA physical design library created in this lab



accessed during this lab: ref_lib/ Link to I/O, standard cell and macro designs

cb13special_fr_lm/ LM view libraries

cb13fs120_tsmc_fr_lm/

cb13io320_4lm_tsmc_fr_lm/

ram32x32_fr_lm/

ram32x64_fr_lm/

ram16x128_fr_lm/


cb13_4m_tlu.tf Tech file with TLU models


Design Setup Lab 5-3 Synopsys Astro 1

Lab 5

Lab 5A Instructions

Task 1. Create MilkyWay Library and Read the Netlist

1. Invoke Astro from lab5a directory.

Make sure you log the output and the command files with a Desing_Setup_5A prefix.

2. Switch to the Data Prep menu to begin the design setup phase:

Select Tools Data Prep

3. Create the design library:

Select Library Create … Enter “design_lib_orca” for Library Name Select “Set Case Sensitive” option

Note: If this option is not selected, Astro will convert all names to uppercase, which can lead to problems with other tools downstream.

Click “OK”

Question 1. Was the library created? ....................................................................................................

You have to supply the technology file when creating the library:

Enter “tech/cb13_4m_tlu.tf” for Technology File Name Click “OK”

Note: You will not see a confirmation that the library was created.

Question 2. What new files and directories were created? .................................................................................................... ....................................................................................................


Lab 5

4. Attach the reference libraries: 4. Attach the reference libraries:

Select Library Add Ref … Enter “design_lib_orca” (created in previous step) for Library Name Enter “ref_lib/cb13special_fr_lm” for Ref Library Name

Select Library Add Ref … Enter “design_lib_orca” (created in previous step) for Library Name Enter “ref_lib/cb13special_fr_lm” for Ref Library Name

s Astro 1

Repeat for each library

All the reference libraries are in the ref_lib directory. Use the command “ls –ld ref_lib/*lm” to display all LM view reference libraries in a different shell window, then cut & paste the correct library names into the dialog box.

Click “Apply” You will not see any feedback in the Message/Input Area as to whether the library was added as a reference library. You will see an error message if the library was not found.

Repeat for all the other LM view reference libraries. There are six in all.

Click “Cancel” to close the dialog box.

5. It is a good practice to have Astro display the attached reference libraries, to ensure that they were added successfully:

Select Library Show Refs … Enter “design_lib_orca” for Library Name Click “OK”

If it does not list the six libraries then go back to previous step to load the missing libraries.

6. Now that the design library has been created and reference libraries are attached, read the Verilog netlist:

Select Netlist In Verilog In … Enter “design_data/orca.v” for Verilog File Name Enter “design_lib_orca” for Library Name

Note: The default “Net Name for 1’b0 and 1’b1” are set to VSS and VDD respectively. These settings match orca.v netlist.

Click “OK”

Question 3. What directories were created in your design library after this step? ....................................................................................................

The top-level instance in orca.v is called ORCA. Astro refers to this instance view as ORCA.NETL. ORCA is the name of the top-level cell and .NETL extension is the convention Astro uses for netlist view.


Lab 5

Task 2. Expand the Netlist

In order for Astro to operate on the design, the netlist needs to be flattened. This is achieved by “expanding” the netlist. In addition, this step verifies that layout views (FRAM) of all referenced instances are available in the Milkyway library.

1. Expanding the netlist:

Select Netlist In Expand … Enter “design_lib_orca” in the Library Name Enter “ORCA.NETL” created earlier in the Unexpanded Cell Name Enter “ORCA.EXP” in the Expanded Cell Name

Note: .EXP extension is the convention Astro uses for expanded netlist view.

Click on Global Net Options button

This option provides the global net patterns for Power and Ground connections. The logical netlist from synthesis usually does not contain Power and Ground nets, VDD and VSS respectively. You need to add these nets and ensure that they are associated with the standard cell power/ground pins.

Repeat for VDD

Enter “VSS” for both Net Name and Port Pattern Click “Apply” to add the specification.

Notice the Number Defined counter incremented by 1. Repeat for “VDD” Click “Hide” to close the sub dialog box. Clicking “Ok” to expand the netlist.

Question 4. Look at the command output in the Message/Input area; was the netlist expanded? How do you know? ....................................................................................................

.....................................................................................................

Question 5. What is the total cell instance count for the ORCA design? ....................................................................................................

Question 6. What new directories were created in the design library? ....................................................................................................


Lab 5

Task 3. Create Cell and Bind Netlist

Similar to the layout views for standard cells and IO or Macro cells, you need to create a layout view or container for the flat design. In Milkyway this layout view is called a “CEL” view.

1. Select the menu Cell Create … to create a new cell.

You should see a message stating: “Library not open”. Even though you just created the design library, it is not opened automatically.

2. The design library needs to be opened before creating a cell:

Select Library Open … Enter “design_lib_orca” as the Library Name Click “OK”

3. Now create the cell:

Select Cell Create … Enter “ORCA” as the Cell Name Click “OK”

Question 7. What new views have appeared in the design library? ....................................................................................................

A new Cell Window ORCA.CEL has opened, but with no content. The cell has been created, but no content assigned or loaded yet.

Binding the netlist is the process of “binding” your Verilog netlist (ORCA.EXP) to the CEL view you just created.

4. Bind the expanded netlist:

Select Design Setup Netlist: Bind Netlist … Enter expanded netlist “ORCA.EXP” in the Net Cell field Click “OK”

Once this is done, select the button “fit with margin” (or press “f” on your keyboard) in your Cell Window.

What you are seeing are FRAM or abstract views of every single instantiated standard cell, IO and macro cell from the expanded netlist. They are stacked up at the origin (lower left corner) of the cell.

Notice also that there is no change to the UNIX directory structure.

Question 8. Where are the FRAM views stored? ....................................................................................................


Lab 5

Task 4. Hierarchy Preservation

Remember that P&R is done on flat designs. For easier simulation/verification (e.g. being able to use the same simulation testbench) and back-annotation/STA of the design after layout, the post-layout netlist must contain the same hierarchical structure as the pre-layout netlist.

This implies that logic gates connected to the subblock borders must maintain their logical functionality (cannot add/remove pins, and cannot transform/optimize logic functions that cross hierarchical boundaries). The only exception here is Clock Tree Synthesis (CTS), which has to add ports to the subdesigns.

By default Astro ignores hierarchical boundary restrictions, which allows for maximum optimization of the design. If you want a hierarchical netlist to be output, you must explicitly tell Astro to preserve the hierarchy. Note that this will restrict the optimization that Astro can do at the boundaries. If you do not care about preserving the hierarchy after layout, these steps can be skipped.

1. Initialize the hierarchy:

Select Cell Hierarchy Preservation: Initialize Hierarchy Information … Enter “ORCA.CEL” as the Flattened Cell Name Enter “ORCA.NETL” as the Hierarchical Top Cell Name Click “OK”

This function will extract the hierarchical port information from the original netlist (NETL) and add it to the flattened top cell (CEL). This information will be used by commands such as ataLoadSDC, which may apply constraints on hierarchical ports that are no longer available in the flattened netlist.

2. Preserve all the cells from optimization:

Select Cell Hierarchy Preservation: Mark Module Instances Preserve … Enter “ORCA.CEL” as the Flattened Cell Name Select “All Module Instances” option Click “OK”

Once the module instances are marked as preserved, they do not allow creation or deletion of any ports. Be aware that CTS and CTO are exceptions to the rule; you might see extra ports on preserved module instances after CTS or CTO.


Lab 5

Task 5. Save and Exit

Now that you have prepared the design for place & route steps, you should save the cell to the Milkyway database. This can be performed using either the “Save !” or the “Save As …” functions.

1. Save the current open cell, which is ORCA.CEL in this case:

Select Cell Save !

You should see the following message: Save cell ORCA.CEL;1 successfully.

It is recommended that you save the cells as you progress using your own more descriptive names, e.g. “ORCA_design_setup”.

2. Save the design under a new name of your choosing:

Select Cell Save As … Enter “ORCA_design_setup” for Cell Name Click “OK”

Note: Subsequence “Save !” still save to the current open cell (ORCA.CEL) and not the new cell name (ORCA_design_setup). In other words, “Save As” does not make the new cell the current cell open.

3. Quit Astro.

Congratulations! You have performed design setup.


Lab 5

Background Lab 5B Adding LM View & Perform Design Setup

The .LM view stores the Synopsys library .db information. The .LM view enables the optimization and timing analysis processes in Astro to use the same timing library as Design Compiler, Physical Compiler and PrimeTime tools. Because the delay model to be used is now determined by the reference timing library (based on the .LM view), Astro uses the same cell delay calculator as PrimeTime. It is recommended that you use .LM views, and not .TIM views, to get the best SDC and timing correlation. When .TIM and .PWR views exist, as well as .LM view, Astro will use .LM view first.


Lab 5


All files for this lab are located in the lab5b directory under your home directory.


Lab5b/ design_data/ Contains the RISC design input data:

RISC_CORE.v RISC design verilog netlist

RISC_CORE.sdc RISC design SDC constraint file

design_lib_risc/ RISC physical design library created in this

lab scripts/

fp.cmd Astro scheme script used to build floorplan



accessed during this lab: ref_lib/ Link to I/O, standard cell and macro designs

cb13fs120_tsmc_fr_lm

ram16x128_fr_lm

db/ Link to standard cell and macro .db files cb13fs120_tsmc_max.db

cb13fs120_tsmc_min.db

cb13fs120_tsmc_typ.db


cb13_4m_typ.itf

cb13_4m_typ.tluplus

cb13_4m.map




Lab 5

Lab 5B Instructions

Task 1. Adding LM View to a Milkyway Library

1. Invoke Astro from lab5b directory.

Make sure you log the output and the command files with a Desing_Setup_5B prefix.

2. Add .LM view to a reference library:

Select Tools Data Prep Select Cell Library Library Preparation … Enter “ref_lib/cb13fs120_tsmc_fr_lm” as the Library Name Click “Import Logic Model DB” button to expand the dialog box Click “Select DB” button to import the .LM view from the .db files Enter “db/cb13fs120_tsmc_max.db”, “db/cb13fs120_tsmc_min.db”, “db/cb13fs120_tsmc_typ.db” for the Max, Min and Typical DB Files. Click OK.


Lab 5

Task 2. Set up RISC_CORE for initial Timing Analysis

The purpose of the remaining lab is for you to set up a design efficiently using the provided job aid. The job aid lists all necessary steps, in the correct order. If you run into difficulties, consult the help pages that Astro provides, or ask your instructor.

1. Given the following “spec”, which lists all the input data, perform all design setup steps outlined in the Job Aid A.

Note: Ignore the message “Inconsitent Data For Layer 13”

Design Library Name: design_lib_risc Technology file: tech/cb13_4m_tlu.tf Reference Libraries: ref_lib/cb13fs120_tsmc_fr_lm ref_lib/ram16x128_fr_lm TLUplus data: (if you get stuck, check the Answer section for help) star_rcxt/cb13_4m* Verilog netlist: design_data/RISC_CORE.v Top-level design name: RISC_CORE Hierarchical instances to preserve: (Use “Module Instances Listed In File” option. Consult the online help) I_ALU I_CONTROL Final Cell saved as: RISC_CORE_design_setup

2. In order to perform a timing check, you need to connect the Power/Ground connections throughout the netlist, and initialize the floorplan.

Since you have not been shown how to floorplan yet, you will need to load a predefined command file from within Astro:

load "scripts/fp.cmd"


Lab 5

3. Perform timing setup and verify that the new .LM view is used for the cb13fs120_tsmc_fr library.

Use Job Aid C as needed.

Activate the TLU+ model, apply the SDC file design_data/RISC_CORE.sdc, and perform a timing data check.

If the timing check was performed without errors and the Message/Input window indicates that LM view is used for cb13fs120_tsmc_fr library then this confirm that you had successfully performed all the necessary steps.

4. Exit Astro.

Congratulations! You have performed design setup for both TLU and TLU+ models. The design is now ready for detailed floorplanning.


Lab 5

Optional: Background Lab 5C Debugging Design Setup Problems

The purpose of these mini-labs (tasks 1 - 4) is to debug specific setup problems. You will be given several situations in which you are expected to uncover, and as appropriate, correct different problems. Try not to jump to the Answer section too quickly, instead try to debug the problem on your own.

Perform as many of these mini-labs as possible to gain the most benefit.


Lab 5


All files for this lab are located in the lab5c directory under your home directory.


Lab5c/ design_data/ Contains the RISC design input data:

RISC_CORE.v RISC design verilog netlist

RISC_CORE1.v RISC design verilog netlist ECOed

RISC_CORE.sdc RISC design SDC constraint file

design_lib1/ Task 1 design library created in this lab




scripts/

bug3_mark_cells.txt List of instances file

debug1.cmd Task 1 debug exercise script




fp.cmd Astro scheme script used to build floorplan


ref_lib/ Link to I/O, standard cell and macro designs




tech2.tf Tech file with TLU models


Lab 5

Lab 5C Instructions

Task 1. Netlist vs. reference Lib Mismatches

1. From lab5c directory, start Astro and load the debug1.cmd script as follow:

unix% Astro –load scripts/debug1.cmd

The script will set up a design library called “debug_lib1” and perform design setup steps up to loading the Verilog netlist.

2. Expand the RISC_CORE netlist.

Question 9. Was there any “WARNING” during netlist expansion? If yes, what can you do to fix the problem? .................................................................................................... ....................................................................................................

3. Exit Astro.

Task 2. Technology file problems

1. Start Astro and load a debug2.cmd script:


The script will set up a design library “debug_lib2” using the tech file “tech/tech2.tf”, attach and display the reference libraries.

2. Look through the log displayed in the Message/Input area, examine the ERROR messages and determine the cause for this failure.

Question 10. What was the problem? What could you do to fix it? .................................................................................................... ....................................................................................................

3. Edit “tech/tech2.tf” to fix the problem and rerun the “debug2.cmd” script to see if the problem was fixed. Quit Astro when the problem is solved.


Lab 5

Task 3. Explore Hierarchy problems

1. Start Astro and load the debug3.cmd script:


The script will set up a design library called “debug_lib3” and execute all setup steps including hierarchy preservation and timing setup.

2. Perform a timing data check.

Question 11. Was the check successful? What is the problem? .................................................................................................... ....................................................................................................

3. Fix the problem you uncovered.

4. Rerun the script using the same command as in step 1, and make sure you have no more Errors.

5. Exit Astro.

Task 4. Graduation: Script debugging

Your task is to debug a script given to you, and correct the mistakes using an editor. Continue to correct and run the command file until you have no more Errors.

1. Start Astro and load the debug4.cmd script:


Question 12. Give a summary of the problems found? .................................................................................................... .................................................................................................... . ................................................................................................... . ...................................................................................................



Answers / Solutions

Lab 5A

Question 1. Was the library created?

Notice the error message

ERROR: Technology file name is not valid

For the library to be created you need to supply a valid technology file. The technology file may contain a TLU model. If a TLU model is not contained, a TLUplus model needs to be provided later.

Question 2. What new files and directories were created?

A new directory named “design_lib_orca” should have been created, containing three files: lib, lib_1 and lib_bck.

Question 3. What directories were created in your design library after this step?

You should see a new directory that was created inside “design_lib_orca”: NETL. This directory in turn will contain one file for each hierarchical block. The NETL view is a binary representation of the original design netlist.

Question 4. Look at the command output in the Message/Input area; was the netlist expanded? How do you know?

Yes, the netlist was expanded. Note the “Expand netlist completes successfully” message.

Question 5. What is the total cell count for the ORCA design?

The total cell instance count is 22,293.

Question 6. What new directories were created in the design library?

You should see a new directory, “design_lib_orca”: EXP. It contains a binary, flattened version of the top-level cell ORCA.

Design Setup Lab 5-19 Synopsys 20-I-022-SLG-003


Question 7. What new views have appeared in the design library?

A new directory called CEL is created in the design library, which will contain the ORCA CEL view.

Question 8. Where are the FRAM views stored?

They are located in the FRAM directory of the respective reference libraries, e.g. ref_lib/ram16x128_fr_lm/FRAM

Lab 5B

TLU+ models

To attach the TLU+ model, call the menu Tech File ITF to TLU+ … from the Data Prep menu and fill in the fields as follows:

Library Name: design_lib_risc Nom CapTable File: star_rcxt/cb13_4m_typ.tluplus Nom ITF File: star_rcxt/cb13_4m_typ.itf Star-RCXT Mapping File: star_rcxt/cb13_4m.map

Note: You may choose to select the min and max files instead, which is the better and more complete way to perform this task!

Remember: After creating the cell, you need to select tluplus in the timing setup panel!

Preserving only select modules

To preserve a subset of the modules in the design, you need to create a simple text file and add one instance name per line of the instances that you want to preserve. The correct file for this lab is ./.solution/cells_to_preserve.txt. Specify this file on the Cell Hierarchy Preservation: Mark Module Instances Preserved … dialog box, after selecting the “Module Instances Listed In File” button.

Solution

A solution script is provided that performs all the tasks required for Lab B. The file is called .solution/risc.cmd



Lab 5C

Question 9. Was there any “WARNING” during netlist expansion? If yes, what can you do to fix the problem?

Expanding the netlist should have produced the following Warning messages:

WARNING : There is no instance in netlist cell bufbd9.NETL.

WARNING : Physical definition of cell bufbd9 may be missing or of wrong type.

The Verilog netlist has instantiated a component called “bufbd9”, which is not available in any of the reference libraries. This points to data-mismatch. There is not much you can do at this point, except contacting the developer of the netlist or the reference library and trying to clear up the problem.

Question 10. What was the problem? What could you do to fix it?

The tech file has an incorrect metal layer name. Instead of the metal layer being called “METAL2” it was called “METAL22” – possibly just a typo. To fix it just edit the file and make the above change.

Question 11. Was the check successful? What is the problem?

The timing data check was not successful. You may have noticed the following Error messages:

ERROR : Cannot find module instance I_ALLLU. ERROR : failed to mark all module instances in file xxMarkHierPres. ERROR : failed to load hierarchical CG.

This indicates that something went wrong while marking the instances that need preservation. Fix the affected files and retry.

Question 12. Give a summary of the problems found?

Need to open design library before cell can be created. Missing Star-RCXT mapping file. Hierarchy must be first initialized before it can be marked. The timing constraint was removed after SDC was loaded.


Floorplanning

FlooSyno

6

Learning Objectives


After completing this lab, you should be able to perform Chip-Level Floorplanning, or Block-Level Floorplanning. You will be able to:

• Define the core and placement row structure

• Define locations for Signal, P/G and Corner pads or pins

• Optimize macro placement (Chip-level only)

• Define power/ground rings and straps

• Create a scheme script file to reproduce the entire floorplan

• Create placement blockages (Chip-level only)

• Floorplan a rectilinear block (Block-level only)

rplanning Lab 6-1 psys 20-I-022-SLG-003

Lab 6

Background

There are two labs available for this unit: Lab 6A and Lab 6B.

Lab6A deals with Chip Level Floorplanning and Lab6B deals with Block Level Floorplanning (starts on page 6-14). Each lab takes approximately 90 minutes to complete; you should select the lab that best fits your needs and consider the other lab as an optional lab if time permits.

In this lab, you will create a floorplan similar to the one shown below following specifications/guidelines. Move/transform a macro to the best possible location based on the connectivity, then implement the P/G structure. You will also perform floorplan exploration and verify the P/G connectivity.

Lab 6-2 Floorplanning Synopsys Astro 1

Lab 6

Relevant Files and Directories (Lab 6A)

All files for this lab are located in the lab6a directory under your home directory.


Lab6a/ design_data/ Contains the ORCA design input data:

initial.tdf Starting tdf file final.tdf Golden tdf file

scripts/ define_soft_blockages.cmd

Placement soft blockages script

place_macros.cmd Script to Place the macros place_pci_pll.cmd Script to Place the pci_pll macro set_pad_fillers.cmd Script to provide pad filler names

design_lib_orca/ ORCA physical design library that contains Design_Setup cell to be used by this lab






Floorplanning Lab 6-3 Synopsys Astro 1

Lab 6

Lab 6A Instructions

Task 1. Setup The Floorplan

Using the design that has been through the Design Setup step, you will create the power/ground/corner pads and define chip size and placement rows.

1. Start Astro from the lab6a directory.

Make sure to log the output and the commands.


3. Open the cell named Design_Setup.

This design is ready for floorplaning.

4. Look at the top section of the tdf file design_data/initial.tdf and see how power/ground/corner pads are instantiated.

Question 1. Why is it necessary to create power/ground/corner pad instances? ....................................................................................................

Question 2. What is the syntax to place a corner pad instance? ....................................................................................................

5. Load the tdf file:

Select Design Setup TDF: Load TDF… Enter design_data/initial.tdf for TDF File Name Click “OK”

6. Create the initial floorplan:

Select Design Setup Floorplan: Set Up Floorplan … Select width & height option Set Row/Core Ratio to 1.0 Set Core Width x Height to 1290 x 1290 Select Horizontal Row, Double Back and Flip First Row options Set Core To Left/Right/Top/Bottom spacing as 60 Click “OK”

Observe how the pads are placed around a core area (red box), standard cells are stacked on the right and the macros are placed on the top. Placement rows are defined in the core area.


Lab 6

7. Turn on the placement rows visibility:

Select Option Window … (or click “Window option” of the Cell View Select row from the Visible Objects group at the top Click Apply, Redraw then Cancel from the Window Options dialog box.

8. Zoom-in to the lower left of the core area and verify that it is setup with abutted horizontal rows, back to back with the first row flipped.

Question 3. For vertical row core area, where would you look to verify the rows are setup correctly? ....................................................................................................

Task 2. Modify The Pad Ordering

In this task, you will output the pad ordering to a tdf file and edit it to change the ordering on a couple of P/G pads to meet ‘design specifications’.

1. Output all the pads to a tdf file:

Select Design Setup TDF: Dump I/O Pins … Enter design_data/output.tdf for File Name Select side+order option Click “OK”

Note: The output.tdf contains the current pad ordering for each side of the chip.

2. Edit the design_data/output.tdf file so that the P/G pads are in increasing order as vdd2left, vdd1left, vss1left, vss2left in the same way the right, top and bottom sides are defined.

There is a solution tdf file that you can compare by running the following command in the UNIX shell from lab6a directory.

unix% diff design_data/output.tdf .solution/output.tdf

3. Load the modified tdf file:

Select Design Setup TDF: Load TDF… Enter design_data/output.tdf for TDF File Name Click “OK”


Lab 6

4. Run the axgPlanner as in Task 1 step 6 so Astro can update the changes from the new TDF.

Load the following command file to run the axgPlanner with same parameters set in Task 1 step 6.

load "scripts/ioReplacePads.cmd"

Note: Floorplanner JupiterXT has a function called ioReplacePads used to update the pads ordering.

Task 3. Modify The Pad Placement

In this task, you will create wider spacing between certain pads to meet ‘packaging guidelines’.

Observe how the pads are distributed evenly on each side of the pad ring by default. This is usually ok, however, if the chip package required the pads near the corners to have wider separation to avoid shorts between the bond wires then the pads location must be modified to meet the required spacing.

Instead of providing the exact pad’s xy coordinates in the tdf file, an easier method may be to insert filler pads where spacing is needed. You are given a modified tdf file with filler pads instantiated and inserted to create spacing between the pads near the corners. Take a look at the modified tdf file design_data/final.tdf to see how this is done.

1. Load the given tdf file design_data/final.tdf then update the changes again.

Observe how the pads near the corners are moved due to the inserted filler pads. Also observe that there are empty spaces around the pad ring (pads are not abutted). Zoom-in real close to see these small gaps (look at the inside corner of the top left pad area).

2. Fill the remaining gaps around the four sides with filler pads of various sizes:

Select PostPlace Filler Cell: Add Pad Fillers …. Either load the set_pad_fillers.cmd script or type in the list below in the Filler field:

load "scripts/set_pad_fillers.cmd"

pfeed10000.FRAM, pfeed05000.FRAM, pfeed02000.FRAM, pfeed01000.FRAM, pfeed00500.FRAM, pfeed00200.FRAM, pfeed00100.FRAM, pfeed00050.FRAM, pfeed00010.FRAM, pfeed00005.FRAM

Click “OK” and observe all the gaps are filled with filler pads.


Lab 6

Question 4. What is the purpose of the pad fillers? ....................................................................................................

Question 4. What is the purpose of the pad fillers? ....................................................................................................

3. Make logical connections to P/G pins of the newly added power/ground/corner pads and the standard/macro cells:

3. Make logical connections to P/G pins of the newly added power/ground/corner pads and the standard/macro cells:

Net Name Net Name Port Pattern Port Pattern Net Type Net Type

ys Astro 1

1 VDD VDD Power

2 VDDO VDDO Power

3 VDDQ VDDQ Power

4 VSS VSS Ground

5 VSSO VSSO Ground

6 VSSQ VSSQ Ground

Table 1: P/G Net Name and Port Pattern

Table 1 above shows the association between the Net Names and their Port Pattern for the design. Perform the following for each of the six combination listed in the table.

Select PreRoute Connect Ports to P/G… Click “Default” Select Macro, Std/Module Cell, Pad for Cell Types Select Update Tie Up/Down option Set the Net Name, Port Pattern and Net Type (from the Table 1 above).

Repeat for each case

Make sure net and port names are correct.

Click “Apply”. Answer OK if Astro ask you to change net type or create it. Repeat for each case from the Table 1 Click “Cancel” when complete

4. Complete the physical P/G connection for the pad ring:

Select PreRoute Pad Rings … Click “Default” Click “OK”

Observe the pad interconnects where the pad fillers were placed. The other pads already have these power/ground built-in.

5. Save the cell as Initialized_Floorplan.


Lab 6

Task 4. Place Macro Instance Based On Flylines

In this task, you will use “flylines” to determine the best possible placement for a macro instance. You will also learn to transform (rotate/flip) the macro instance.

1. Before starting this task, zoom to an area that encloses the entire floorplan and the unplaced macros.

2. Turn off the row visibility from the Window Option panel.

3. Highlight the macro cell connections:

Select Query Flyline: Show Net Connections … Select “Ignore Connections To Standard Cells” Click “OK”

The “flylines” help guide where the macros should be placed.

4. To help get started, load the following script to place some of the macros:

load "scripts/place_macros.cmd"

5. Redraw the Cell Window.

6. Clear and update the flylines:

Select Query Flyline: Show Net Connections … Click “Clear” Click “OK”

Observe in the Cell Window that all macros except for one are placed in the core area. You will place this macro in the following steps.

7. Select the macro to be moved:

Select Select (De)select by Name … Enter “I _CLOCK_GEN/I_PLL_PCI” for Name Select “Type” cell Click “OK”

Note: Instance can also be selected using bind key as follow: type ‘p’ in the Cell Window then click the instance to be selected.

The color of the instance changes from yellow to wClicke when selected.

8. Zoom-in to the top-left region of the core area covering the selected macro and about 4 pads from both left and topsides.


Lab 6

9. Based on the flyline, move the instance into the core area near the pad that it connected to:

Select Modify Move … or press the bind key ‘m’ Set Snap to None in the Move dialog box

This allows free movement of the selected instance.

Click on the selected instance to get a reference point for the move.

Move the instance then click again to set the instance in place.

Click “Cancel” or press the Esc key to close the dialog box.

10. Reduce the flyline length further by flipping the instance around the x-axis:

Select Modify Transform … or press the bind key ‘t’. Select the appropriate transform option from the Transform dialog box. Click on the instance to start the transform. Reposition the instance then click again to complete the transform.

Try again if it did not work the first time.

Click “Cancel” or press the Esc key to close the dialog box.

11. Deselect all instances:

Select Select Deselect: Deselect All!

12. Remove the flylines:

Select Query Flyline: Show Net Connections … Click “Clear” Click “cancel”

13. Load the following solution script to see how the macro should have been placed:

load "scripts/place_pci_pll.cmd"

Remember to redraw the Cell Window to see the change.


Lab 6

Task 5. Add Placement Blockages

In this task, the floorplan is first explored then blockages are added to remove congestion hot spots if they exist.

In order to explore the floorplan for potential congestion problems, the design must be placed.

1. Perform timing setup so the design can be placed in the next step by running the given timing setup script:

load "scripts/timing_setup.cmd"

Performing timing+congestion driven placement without the In-Placement Optimization option saves some runtime. Do not perform PrePlacement Optimization since basic placement is good enough for early floorplan exploration.

There are patches of congestion, especially between the RAM macros.

2. Zoom-in to a congested area and check for high overflow.

Standard cells placed near and between the macros create most of the congestion.

3. Unplace the standard cells:

Select PostPlace Unplace Cells … Select “Keep Macro Placement” Click “OK”

4. Create soft placement blockages around the macros:

Select PrePlace Placement Blockage: Create Soft Blockage Draw four rectangle soft blockages to cover the macros

Draw a rectangle by using the mouse (in the same way you would to zoom into an area). Do not worry if you make mistake.

Press the Esc key to cancel the command when finished.

5. Load the following soft placement blockage solution script to see how the blockages should have been defined:

load "scripts/define_soft_blockages.cmd"

Remember to redraw the Cell Window to see the changes.


Lab 6

Question 5. What is the difference between soft and hard placement blockages? ....................................................................................................

6. Save the cell as Macros_Floorplanned.

Task 6. Create Power/Ground Structure

In this task, you will create P/G structure for the floorplan with the given specification.

Note: It is easy to make a mistake in this task. Use the Apply button whenever possible so the command can be ‘Undo’ne. Once the command dialog box is closed, it cannot be undone.

1. Create the core ring:

Select PreRoute Rectangular Rings … Select Around: Core Enter VDD, VSS (separated by a comma) for Net Names (s) Set Width on all sides to 20.0 Set L-Layer and R-Layer to METAL2 (18 from tech file) Set B-Layer and T-Layer to METAL3 (22 from tech file) Set Offsets on each side to1.0 Click “OK”

Note: If you do not know the metal layer numbering from the tech file, click the METAL hatch pattern button to bring up an Edit Layer Panel, select a layer from there then click Hide.

Question 6. What is the purpose of a core ring? ....................................................................................................

2. Create six vertical P/G straps:

Select PreRoute Straps … Set Vertical for Direction option Set Start X at 715 Enter VDD, VSS for Net Names(s) Set Width to 7.5 Set Layer to METAL2 Set Configure by Step & Stop Set Step to 168, Stop to 1600 Set Pitch within Group to 10.0 Click “Apply”.


Lab 6

Note: Make sure there are six pairs of VDD/VSS created. If not click “Undo” then make the necessary corrections.

3. Similarly, use the following options to create a single horizontal P/G strap.

Direction: Horizontal Start Y: 1100 Net Names(s): VDD, VSS Width: 10 Layer: METAL3 Configure by Step & Stop: Step = 0, Stop = 1100 Click “Apply” and if the strap is created correctly, click “Cancel”

4. Create the P/G ring around the two macros located in the lower left of the core area: I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/REG_FILE_A_RAM and I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/REG_FILE_B_RAM.

Press the bind key “p” for picking the two objects Select both macros by clicking each of the macro at a time Select PreRoute Rectangular Rings … Select Around: Selected as a Group Enter VDD, VSS for Net Name(s) Select Left and Bottom for Skip Side(s) Set R-Width/T-Width to 7.5 Set R-Layer to METAL2, T-Layer to METAL3 Set Offsets to 0 Select RL and TL for Extend Click “Apply”

Note: If the macro ring is created incorrectly, click “Undo” and make the necessary corrections.

Click “Cancel” when complete Select Select Deselect: Deselect All! to deselect all instances

5. Create the P/G ring for a single instance I_CLOCK_GEN/I_PLL_PCI using same parameters as in step 4 but with appropriate Skip Side(s) and Extend options.

Question 7. For what reason would you use smaller widths on macro rings compared to the core ring? ....................................................................................................

6. PreRoute the pads and macros:

Select PreRoute Macros/Pads … Click “Default” Click “OK”

Note: Observe the macros and pads are connected to P/G rings and straps.


Lab 6

7. Perform placement again now that P/G structures are built.

Analyze the Global Route congestion map.

You will see almost no congestion.

8. PreRoute the standard cells:

Select PreRoute Standard Cells … Click “Default” Click “Fill All Empty Rows” (near the bottom of the dialog box) Click “OK”

Note: All the rows should have VDD/VSS rails.

9. Unplace the standard cells but keep the macros placement.

10. Save the cell as Floorplanned.

Task 7. Verify P/G Structure Based On Floorplan Exploration

Once the power structure is complete, you need to verify that all the macros and pads are connected to the power structure correctly.

1. Verify the P/G connectivity:

Select PreRoute Verify P/G Connectivity … Select ignore the Std Cell Pin Connect, because you only want to verify the pads and the macros Click “OK”

Note: If Astro reports any errors, look at the errors by loading the error file with: Verify Init Errors: Load Error Cell … then ask Astro to start with: Verify Show Errors: Show First Error ! There should not be any errors, but if there are and you have not been able to fix them, ask the instructor for assistance.

Question 8. What is the command to verify the P/G structure? ....................................................................................................

2. Exit Astro. Congratulations! You have completed Lab 6A.


Lab 6

Lab 6B: Block Level Floorplanning

Traditionally, block level designs are performed in rectangular shapes; however, to make the best use of available space in the top-level floorplan, chip designers often create hierarchical layouts containing a mix of rectangular and rectilinear (L, U, T, and ‘+’) shaped macros.

In this lab, you will set up a block level floorplan per specifications similar to below. You will create core power rings and straps and verify congestion is OK.


Lab 6


All files for this lab are located in the lab6b directory under your home directory.

The following directories and files will be used or created during this lab:

Lab6b/ design_data/ Contains the ORCA design input data:

rpin_default.tdf Astro default tdf file rpin_modified.tdf Final tdf file

scripts/ define_soft_blockage.cmd

Placement soft blockage script

lab6b_macros_fp.cmd Script to Place the macros

place_RAMA.cmd Script to Place the RAM A macro timing_setup.cmd Script to perform timing setup

modify_pin.cmd Script to change the pins metal layer

design_lib_risc/ RISC physical design library that contains the Design_Setup cell to be used by this lab






Lab 6

Lab 6B: Instructions

Task 1. Create The Rectilinear Floorplan

Using the design that has been through the Design Setup step, you will create an L-shaped rectilinear floorplan and placement rows.

1. Start Astro from the lab6b directory.

Make sure to log the output and the commands.

2. Open the library design_lib_risc.

3. Open the cell named Design_Setup.

This design is ready for floorplaning.

4. Create a rectilinear floorplan:

Select Design Setup Floorplan: Set Up Rectilinear Floorplan … Select Shape-Based and True Length options Set True Core Length: a=195, b=250, c=177, d=180 Select Horizontal, Double Back and Start from First Row Set Core To Left/Bottom spacing as 15, Core To Right/Top spacing as 0 Click “OK”

Question 9. What command is used for creating a rectilinear floorplan? ....................................................................................................

5. Turn ON the placement rows visibility:

Select Option Window … (or click “Window option” of the Cell View.

Select row from the Visible Objects group at the top.

Click Apply, Redraw then Cancel from the Window Options dialog box.

6. Zoom-in to the lower left of the core area and verify that it is setup with abutted double back horizontal rows and start from the first row.

Zoom out to see the entire rectilinear view. The red square is the standard cell region and the yellow ‘L’ shape is the cell boundary.

7. Turn OFF the placement rows visibility (following the instructions from step 5 above)


Lab 6

8. Place the macro pins: 8. Place the macro pins:

Select Design Setup Floorplan: (Rectilinear) Pin Placement! Select Design Setup Floorplan: (Rectilinear) Pin Placement!

Note: The pins are placed along the cell boundary. If you want to see them, zoom in near the cell boundary.

Note: The pins are placed along the cell boundary. If you want to see them, zoom in near the cell boundary.

Task 2. Check/Modify Pin Layers Task 2. Check/Modify Pin Layers

ys Astro 1

The power ring/straps use the top metal layers (M3 and M4); you want the pins defined on M1 and M2. This allows easy access to the pins without shorting to P/G defined later around the rectilinear boundary.

1. Dump the default rpin file:

Select Design Setup Dump Floorplan … Enter design_data/rpin_default.tdf as File Name Unselect all options except for io cell placement option Click “OK”

2. Make sure you see the entire rectilinear (to select the pins along the six sides).

Select Options Window … Unset all Selectable Objects except for pin Click Apply, Redraw then Cancel Select Select Select: Select by Window (Draw a box barely enclosing the left edge as shown. The pins highlighted when selected).

Press the bind key “q” to query all selected pins and look in the Message/Input Area to verify the pins are currently on M3.

Select Modify Modify … to modify the selected pins layer

Enter 14 and 0 in the two fields next to the Layer option as shown. Set Direction option to “left” (this allows the pins to access from the left side when this macro is instantiated in the chip level). Click “OK”


Lab 6

3. Select Select Deselect: Deselect All ! to deselect all the pins. Load the following command to modify the other 5 sides of the rectilinear:

load “scripts/modify_pins.cmd”

Note: Top and bottom pins are defined on M2 since the preferred routing direction is vertical.

4. Dump the new rpin:

Select Design Setup Dump Floorplan … Enter “design_data/rpin_modified.tdf” as the File Name Select only io cell placement option for dumping Click “OK”

5. Find the changes by comparing the two rpins by running the following command in the UNIX shell from lab6b directory.

unix% diff design_data/rpin_default.tdf design_data/rpin_modified.tdf

Note: Basically, everything has changed. Once you get the modified rpin file you could continue to make more changes by editing this text file and load it back into Astro using design_planning Load TDF … without having to go through this Task 2 again.

6. Save the cell as Initialized_Floorplan.

Task 3. Place Macro Instance

In this task, you will learn to move and place the macro into the core area.

1. Before starting this task, zoom to an area that encloses the entire floorplan and the two unplaced macros.

2. To help get started, load the following script to place one of the macros:

load "scripts/lab6b_macro_fp.cmd"

3. Redraw the cell window:

Select Views Redraw ! (or click the redraw button from the Cell Window)

4. Set all Selectable Objects back to selectable in the Window Options panel.


Lab 6

5. Select the unplaced macro:

Select Select (De)select by name … Enter “I_REG_FILE/REG_FILE_A_RAM” as the Instance name Select “cell instance” for Type Click “OK”

Note: An instance can also be selected using bind key as follows: type ‘p’ in the Cell Window then click the instance to be selected.

The color of the instance changes from yellow to wClicke when selected.

6. Move the instance into the core area and next to the other macro:

Select Modify Move … Set snap to None in the pop up dialog box.

This allows free movement of the selected instance.

Click on the selected macro to get a reference point for the move.

Move the macro to the lower left then click again to set the macro in place.

Click “Cancel” to close the Move dialog box.

7. Deselect all instances:

Select Select Deselect: Deselect All!

8. Load the following macro placement solution script to see how the macro should have been placed:

load "scripts/place_RAMA.cmd"

9. Redraw the Cell Window to update the view.


Lab 6

Task 4. Add Placement Blockage

In this task, you will add placement blockages to prevent congestion around the macros.

1. Create soft placement blockages around the macros:

Select PrePlace Placement Blockage: Create Soft Blockage Draw a single soft blockage to cover the two macros

Draw a rectangle by using the mouse in the same way you would zoom to an area. Do not worry if it did not work correctly.

Press the Esc key to cancel the command when finished.

2. Load the following soft placement blockage solution script to see how the blockages should have been drawn:

load "scripts/define_soft_blockage.cmd"

3. Redraw the Cell Window to update the view.

Question 10. What is the difference between soft and hard placement blockages? ....................................................................................................

4. Save the cell as Macros_Floorplan.


Lab 6

Task 5. Create Power/Ground Structure Task 5. Create Power/Ground Structure

ys Astro 1

In this task, you will create the P/G structure for the floorplan by following the given specification.

Note: It is easy to make a mistake in this task. Use the Apply button whenever possible so the command can be undone. Once the command dialog box is closed, it cannot be undone.

1. Create the P/G ring around the macros I_REG_FILE/REG_FILE_A_RAM and I_REG_FILE/REG_FILE_B_RAM.

Press the bind key “p” for picking an object Select both as a group by click each of the macro one at a time Select PreRoute Rectangular Rings … Choose Selected as a Group option Enter VDD, VSS for Net Name(s) Skip Left and Right Sides Set B-Width/T-Width to 5.0 Set B-Layer/T-Layer to METAL3 (tech layer 22) Set Offsets Bottom/Top: to 1 Set Extend for BL, BH, TL and TH Click “Apply”

If you do not know the metal layer numbering from tech file, click the METAL hatch pattern buttons to bring up an Edit Layer Panel. Select a layer from there then click Hide.

If the macro rings are created incorrectly, click “Undo” to make corrections

Click “Cancel” when completed Select Select Deselect: Deselect All! To deselect all instances

2. Create two vertical P/G straps with the following options:

Select PreRoute Straps … Set Vertical direction Set Start X at 5 Enter VDD, VSS for Net Names(s) Set Width to 5 Set Layer to METAL4 (tech layer 26) Configure by Step & Stop with Step = 193, Stop = 200 Set Pitch within Group to 5.5 Select At Core Bdry for Low Ends and High Ends Select Extend to Boundaries and Generate Pins and Force options. Click “Apply”

If the two straps are created incorrectly, click “Undo” to make corrections

Click “Cancel” when completed


Lab 6

Question 11. What reason would there be to use Top Layers (Metal3 and Metal4 in this lab) for Power rings/straps? . ................................................................................................... . ...................................................................................................

3. Zoom-in to a horizontal or vertical strap at the boundary and observe VDD and VSS pins created at the boundary.

4. Associate standard cells VDD and VSS to the P/G structure.

The table below shows the association between the Net Names and their Port Pattern for the design.

Net Name Port Pattern Net Type

1 VDD VDD Power

2 VSS VSS Ground

Table 1: P/G Net Name and Port Pattern

Select PreRoute Connect Ports to P/G… Click “Default” Select Update Tie Up/Down option Enter VDD for Net Name Enter VDD for Port Pattern Set the Net Type to Power Click “Apply” Answer OK if Astro ask you to change net type Repeat for VSS case Click “Cancel” when completed

5. PreRoute the macros:

Select PreRoute Macros/Pads … Click “OK”

Power Structure is now complete.

The next step is to verify that congestion is OK. In order to explore the floorplan for potential congestion problems, the design must be placed first.

6. Perform timing setup so design can be placed in the next step by running the given timing setup script:

load “scripts/timing_setup.cmd”

Repeat for VSS


Lab 6

7. Perform timing+congestion driven placement without the In-Placement Optimization option to save some runtime.

Do not perform PrePlacement Optimization since basic placement is good enough for early floorplan exploration.

8. Analyze the Global Route congestion map.

There should be no congestion.

9. PreRoute the standard cells to create physical VDD and VSS connections:

Select PreRoute Standard Cells … Click “Default” Click “Fill All Empty Rows” (near the bottom of the dialog box) Click “OK”

Note: All the rows should have VDD/VSS rails.

10. Unplace the standard cells but keep the macros placement:

Select PostPlace Unplace Cells … Select “Keep Macro Placement” Click “OK”

11. Save the cell as Floorplanned.

Task 6. Verify P/G Structure

Verify the connectivity to the P/G structure once the power plan is complete.

1. Verify the P/G connectivity:

Select PreRoute Verify P/G Connectivity … Select ignore the Std Cell Pin Connect since you just want to verify the pins and the macros. Click “OK”

Note: There should be no errors found for VSS or VDD. If Astro had reported errors, you can load the errors using Verify Init Errors: Load Error Cell … then view the errors using Verify Show Errors: Show First Error !

Question 12. What is the command to verify the P/G structure? ....................................................................................................


Lab 6

Task 7. Create Macro Abstract

Once the design is P&R, it can then be generated as an abstract macro for integrating into chip level. Use the current cell as an exercise for this.

1. Save the cell as risc_core.

2. Generate macro abstract (risc_core.FRAM) for risc_core.CEL saved in step 1:

Select Cell Make Macro Abstract… Enter Cell Name as risc_core Click “OK”

Note: Normally the settings must be set for a design’s specific requirement when creating a macro abstract. Please see the help page for detailed information about these settings.

3. Open the abstract view to see what it looks like:

Select Cell Open … Enter risc_core.FRAM for Cell Name Click “OK”

4. Quit Astro. Congratulations! You have completed Lab 6B.

If you have ~25 minutes to spare, you may want to run the first few tasks of Lab 6A. You will not be able to complete the lab but you may learn something about chip level tdf.



Answers / Solutions

Question 1. Why is it necessary to create power/ground/corner pad instances?

Unlike signal pads, power/ground/corner pads are not usually instantiated in the netlist. Instead, they are instantiated in a tdf file.

Question 2. What is the syntax to place a corner pad instance?

pad "<cornerpad_instance_name>" "<side>"

Where <side> is bottom, right, top or left.

Question 3. For vertical row core area, where would you look to verify the rows are setup correctly?

Lower left corner.

Question 4. What is the purpose of the pad fillers?

The purpose of the pad fillers is to fill the ‘gap’ between the pads so that a continuous pad power/ground ring can be created. They also serve as nwell required for manufacturing.

Question 5. What is the difference between soft and hard placement blockages?

‘Soft blockage’ allows Astro to place buffers etc in the blocked area during optimization/CTS/CTO etc. where as ‘hard blockage’ does not allow placing any thing under any circumstances.

Question 6. What is the purpose of a core ring?

A core ring is the bridge between power/ground pads and the power/ground nets of the standard cell rows and macros.

Question 7. For what reason would you use smaller widths on macro rings compared to the core ring?

Core ring provides power to the entire core area, where as macro ring provides power only to the specific macro area. Macro is a subset of the core and so macro rings are smaller than core rings.



Question 8. What is the command to verify the P/G structure?

AxgVeriPGConn

Question 9. What command is used for creating a rectilinear floorplan?

AxgRectiPlanner

Question 10. What is the difference between soft and hard placement blockages?

‘Soft blockage’ allows Astro to place buffers etc in the blocked area during optimization/CTS/CTO etc.

‘hard blockage’ does not allow placing any thing under any circumstances.

Question 11. What reason would there be to use Top Layers (Metal3 and Metal4 in this lab) for Power rings/straps?

Usually standard cells are created using the lower level metals. In order not to interfere with the standard cells and to provide a smooth signal routing, power rings/straps are created using the top layer metals.

Question 12. What is the command to verify the P/G structure?

AxgVeriPGConn


RouSyno

Routing
7
ting Lab 7-1 psys 20-I-022-SLG-003

Learning Objectives


In the previous lab, the standard cells were placed, the clock trees were synthesized and the post-placement timing optimization was done. In this lab, the design will be routed, and if necessary, post-route optimizations will be done. You will also perform timing analysis between steps.


• Route clock nets

• Perform global routing

• Perform track assignment

• Perform detail routing

• Perform post-route timing optimizations

• Perform post-route timing analysis

• Run Design Rule Checking (DRC) for mask design rule violations

• Fix DRC violations with Search and Repair

Lab 7

Background

By this point the ORCA design has been optimized, macros and standard cells have been placed and its clock trees have been inserted. The remaining work is routing the design and optimizing it to meet timing. This lab does not take advantage of all available features in Astro. For more information refer to the Astro User’s Guide.

The ORCA design at the end of the Placement and CTS stages is projected to meet timing post-route. If you route this design, as is, with the current constraints that prediction is borne out. To do so, would provide little opportunity to explore some of the routing related optimization steps.

Starting with the very best placement possible is the key to quick and successful routing. For educational purposes, however, some timing violations are introduced in to the ORCA design so that the router and related optimization steps can fix them.

Lab 7-2 Routing Synopsys Astro 1

Lab 7



The following directories and files will be created or used during this lab:

lab7/ .avntrc User defined settings/functions

design_data Will contain files generated/used by Astro

orca_final.v Astro output Verilog for final STA

orca_final.spef.gz Astro output SPEF for final STA

design_lib_orca/ ORCA physical design library that contains the PPO2 cell to be used by this lab

reports/ Astro report files generate during this lab scripts/ Script used during this lab

fm_compare.tcl Formality run script to compare pre/post Astro netlist

func_run.tcl PrimeTime run script to setup ORCA for STA

orca_pt_constraints.tcl ORCA constraint file for PrimeTime

orca_pt_clocks.tcl ORCA clocks constraint file for PrimeTime

orca_pt_ioconst.tcl ORCA IOs constraint file for PrimeTime






Routing Lab 7-3 Synopsys Astro 1

Lab 7

Lab 7 Instructions

Task 1. Start Astro, Open Library and Cell



3. Open the cell named PPO2.

Astro is designed to accurately predict the routing capacitance during placement and CTS to improve timing convergence. It is not expected that any significant increase in negative slack will occur between post-placement timing results and post-route timing results.

This design has already met timing at the end of CTS and specifically PPO2. To learn a few more optimization functions available during the routing phase, the cell PPO2 provided for this lab is purposely saved with a modified orca.sdc so that PPO2 has some timing violations.

Note: Modified orca.sdc set the clock uncertainty of 0.5 and 0.25 to SYS_CLK and SYS_2x_CLK respectively. All other clocks get clock uncertainty of zeros.


Lab 7

Task 2. Design Analysis

This design has just completed post-placement optimization and CTS. You should make sure that no significant setup or hold timing violations exist prior to routing. If both setup and hold slacks are positive or nearly so, then the design is ready for routing.

Note: The cell PPO2 for this lab has a few timing violation due to the “added” clock uncertainty modified in the orca.sdc. For the purpose of this lab, you should leave the “Ignore Clock Uncertainty” option from the Timing Setup panel disabled. You can use this same method to model clocks jitter.

1. Verify and set the following options (in addition to the settings saved with PPO2 cell) on the timing setup panel before performing timing analysis:

Select Timing AstroTime: Timing Setup … Click Parasitics tab Make sure "Max" and "Min" are set for “Operating Cond”. Click “Apply” Click Model tab Make sure "Max" and "Min" are set for “Operating Cond” and Make sure Elmore is set for Delay Model. Click “Apply” Click Optimization tab Set the “Target Hold Slack” to 0.1. Click “Apply” Click Environment tab Enable “Enable Mixed Clock/Signal Edges”, “Enable Recovery/Removal Arcs”, “Enable Clock Gating Checks” Click “Hide” to close the Timing Setup Panel.

Question 1. What is the main benefit of using an Elmore model to calculate net delay?

....................................................................................................

....................................................................................................

2. Generate and save a timing report to a file which shows the worst setup/hold with histogram:

Select Timing AstroTime: Timing Report … Click “Default” Select “Show Histogram” option Select File option Enter reports/ppo2_timing.rpt as File name Click “OK”


Lab 7

Answer the following questions using timing information from this report.

Question 2. Is the “Propagated Clock” ignored? Are “Recovery/Removal Arcs”, “Mixed Clock/Signal Paths” and “Enable Clock Gating Checks” enabled? (Verify from the Design Setup section at the top of the Astro Timing Report)?

.....................................................................................................

Question 3. From the Slack Histogram section, what is the worst slack of the setup timing?

....................................................................................................

Question 4. Is there a hold time violation? . ...................................................................................................

Question 5. What has to be done to fix the setup timing of the worst path in clock group SYS_CLK?

....................................................................................................

From the timing analysis above, ORCA has setup timing violations due to the timing path delay. The worst setup slack violates by about 5% of the SYS_CLK period. This is considered a big violation at this stage you will try to fix these timing problems during the routing phase using Astro Post-Route Optimization.


Lab 7

Task 3. Set Automatic Routing Options

Astro can route the design in many different ways. The options should be set prior to any routing.

1. Set the routing options:

Select Route Setup Route Common Options … Click “Default” Select “Timing Driven” under both Global Routing and Track Assign Select “check and fix” for “Same Net Notch” Select “check and fix” for “Wire/Contact End-of-line Rule”

The above 2 options reduce the number of shapes causing DRC problems

Select “signal routing too” for “Merge Fat Wire On” Click “OK”

Task 4. Route the Clock Nets

You are now ready to route the clock nets.

1. Route the clocks:

Select Route Route Net Group … Click “Default” Select “All clock nets” under Net Name(s) From to route all clock nets Click “OK”

Question 6. What is the advantage for routing clocks before other signals? .................................................................................................... ....................................................................................................

2. Zoom into an area to see routed clock nets:

Click the user defined bind key “F8” over the Cell window Enter 1000,1000 for Center: X,Y and 300 for Window Size (+/-) Click “Zoom” Click “Cancel”


Lab 7

3. The resulting clock nets can better be displayed in the layout view by turning off some of the other objects:

Select “Window option” button Turn off visibility of polygon, contact, text, pin, cell instance and row under Visible Objects (Everything but path) Click “Route Type” button Turn off "std cell pin conn" for Visible Route Type Click “Apply”, “Redraw” then “Cancel”

Question 7. What layers have been predominantly used to route the clocks? .................................................................................................... ....................................................................................................

4. Reset the visibility of polygon, contact, text, pin, cell instance and row back on.

5. Save the cell as Clocks_Routed.

Task 5. Global Route

The global router will determine the course from the source to each destination of a net as a series of Gcells through which the net will cross. In addition, the global router will determine the metal layer of a net’s routing.

Note: Be sure that “timing driven” is specified for global routing in the route common options dialog box before beginning the global routing.

1. Run the global router:

Select Route Global Route: Global Route … Click “Default” Click “OK”

The “Speed” selection gives a coarse tradeoff between runtime and quality of the resulting global route.

Default setting of “medium” is recommended for a design with low congestion.


Lab 7

2. Examine the congestion map:

(Route Global Route: Display Congestion Map …)

Note: Use the "(un)set_congestion_view" user defined commands that were introduced in the placement lab to enhance visibility.

Question 8. What conclusions can you draw from the congestion map? ....................................................................................................

.....................................................................................................

.....................................................................................................

3. Save the cell as GR.

The next step is to verify the timing and max trans/cap and deterimine if they need to be fixed prior to running Track Assignment.

4. Run a timing report for setup/hold violations.

Save the report to "reports/gr_timing.rpt".

Use the report to answer the following questions.

Question 9. Is the slack better or worse than PPO2 result from Task 2 report? ....................................................................................................

Question 10. Should you run the Global Route optimization? ....................................................................................................

5. Run the Global Route optimization to fix the remaining violations, enter the following command in the Message/Input area:

astPostRouteOpt

Click “Default” Select “Global Route” under Routing Phase Unselect “Purge Filler” under Flow Control

Warning: Selecting this option will purge all standard cell fillers, standard cell spares, pad fillers and tap cells.

Click “OK”.


Lab 7

6. Save the cell as GR_Optimized.

7. Generate a timing report and save it to “reports/gr_opt_timing.rpt “.

Question 11. Were the setup violations fixed after Global Route optimization? . ...................................................................................................

Task 6. Track Assign

Global route has completed. The next step is to perform Track Assign.

1. Perform Track Assign:

Select Route Track Assign !

2. Save the cell as TA.

3. Run a timing report for setup, hold, max cap and max transition violations.

Save the report to "reports/ta_timing.rpt".

Question 12. Is the timing still met after track assignment? ....................................................................................................

4. Run the Track Assignment Optimizations to improve setup/hold further by trying to meet the setup and hold cost of 0.1 (make the slack of at least 0.1 before stop optimizing) set in the Timing Setup panel:

astPostRouteOpt

Click “Default” Select “Track Assign” under Routing Phase Unselect “Purge Filler” under Flow Control Click “OK”

5. Save the cell as TA_Optimized.

6. Run a timing report and save it to “reports/ta_opt_timing.rpt”.

Question 13. Has the slack improved for the SYS_2x_CLK from the previous step? . ...................................................................................................

Track Assign is complete and timing is met.


Lab 7

Task 7. Detail Route

Detail route is run to complete the routing of the cell.

1. Run the detail router:

Select Route Detail Route: Initial Detail Route … Click “Default” Select to “Skip” Track Assignment Click “OK”

Note: Setting Search & Repair Loop to 0 speed up the detail route. If DRC violations remain after detail route then S&R can be invoked to help.

Question 14. How many unresolved DRCs remain after detailed routing? Do you need Search and Repair loops? ....................................................................................................

2. Run Search&Repair to fix the DRCs:

Select Route Detail Route: Search & Repair… Click “Default” (Search Repair Loop should be 50) Click “OK”

Question 15. In which order would the Global Route (GR), Track Assign (TA), Search&Repair (S&R) and Detail Route (DR) run? . ...................................................................................................

3. Change the Delay Model to Arnoldi in the Timing Setup panel’s Model tab, since you now have all signals detail routed.

4. Save the cell as DR.

5. Generate a timing report for setup, hold, max cap and max transition violations.

Save the report to "reports/dr_timing.rpt".

Using this report, answer the following questions.

Question 16. Which LPE mode is used to generate the timing report? ....................................................................................................


Lab 7

Question 17. Is the timing still met after detailed route? ....................................................................................................

Question 18. Should you run the Detail Route optimization? ....................................................................................................

Task 8. Final Design Analysis and Repair

1. Run the design rule check (DRC) program to check for mask rule violations:

Select Verify DRC … Click “Default” Enter “DR_drc.err” for Error Cell Name Select “List Error Summary Immediately” Click “OK”

Question 19. Do you see any errors reported? ....................................................................................................

Note: All DRC related commands are in the “Verify” menu. If you do not see a DRC error summary window or you have accidentally closed it, give the command: geListErrorSummary (Verify Init Errors: List Error Summary!) to redisplay the summary without a complete rerun of DRC checks. To highlight the first error, use Verify Show Errors: Show First Erorr! or other show error commands.

2. Fix the remaining DRC errors, run Search&Repair again using the “rerun DRC” option:

Select Route Detail Route: Search & Repair… Set Search Repair Loop to 5 Enable “rerun DRC” option Click “OK”

Note: To verify that all DRCs have been removed rerun Verify DRC. You can skip this step in this lab, since the report will tell you that there is no DRC violation.


Lab 7

3. Generate a PR Summary:

Select Query List PR Summary ! Answer the following question using the information at the bottom of the report.

Question 20. What is the total wire length for the signal wiring? ....................................................................................................

4. Save the cell as DR_final.

Task 9. Optional: STA Signoff

1. Write out a hierarchical Verilog netlist:

Select Cell Hierarchy Preservation: Hierarchical Verilog Out … Click “Default” Enter DR_final.CEL for Flattenned Cell Name Enter signoff_data/orca_final.v for File Name Select these additional options in addition to the default options: No power/ground nets, No Corner Pad Cell instances, No Pad Filler Cell instances, No Core Filler Cell instances, No Unconnected Cell instances Unselect the “Output 1’b1 for Power…” Click “OK”

2. Write out RC annotation in SPEF:

Select Timing Parasitic Output: SPEF Out … Click “Default” Unselect “Reduce RLC Tree” Select Compress file near the bottom of the dialog box to create .gz file Enter signoff_data /orca_final.spef as the Output file Click “OK”

3. Verify the two files were generated then quit Astro.

4. Start PrimeTime from lab7 directory:

unix% primetime –f script/func_run.tcl

5. From PrimeTime GUI generate the histogram:

Click Endpoint Slack Histogram button from the toolbar Choose either max (setup) or min (hold) Click “OK”


Lab 7

For more about using PrimeTime see the PrimeTime User Guide or attend the Synopsys PrimeTime workshops.

6. To get default textual timing report, type the following on the command line:

report_timing

7. When finnished quit PrimeTime:

quit


Lab 7

Task 10. Optional: Formality – Logical Equivalence

1. Run the comparison of orca.v and orca_final.v. from the lab 7 directory UNIX command line:

unix% formality –f scripts/fm_compare.tcl

Question 21. Did the circuit compare? ....................................................................................................

2. Use the (File Exit) menu in the Formality GUI to exit.

Congratulations! You have completed Lab 7.



Answers / Solutions

Question 1. What is the main benefit of using an Elmore model to calculate net delay?

Less runtime is required to calculate net delay. Elmore model should be used before the design is routed. Once routed, Arnoldi model should be used for added accuracy.

Question 2. Is the “Propagated Clock” ignored? Are “Recovery/Removal Arcs”, “Mixed Clock/Signal Paths” and “Enable Clock Gating Checks” enabled? (Verify from the Design Setup section at the top of the Astro Timing Report).

The “Propagated Clock” is not ignored. “Recovery/Removal Arcs”, “Mixed Clock/Signal Paths” and “Enable Clock Gating Checks” are enabled. This is the correct setting after CTS.

Question 3. From the Slack Histogram section, what is the worst slack of the setup timing? The worst setup slack is about -0.36.

Question 4. Is there a hold time violation?

No. All hold paths have positive slack as indicated from the slack histogram.

Question 5. What has to be done to fix the setup timing of the worst path in clock group SYS_CLK?

The Arrival time (mostly path delay) must be reduced to less than the Required time.

Question 6. What is the advantage for routing clocks before other signals?

It is recommended to route clock nets to get the most direct routing. Timing analysis can be done right after clock routing to isolate potential problems early and at incremental steps for easy fixing if problems do show up.

Question 7. What layers have been predominantly used to route the clocks? Metal2 (Yellow) and Metal3 (Red)


Lab 7

Question 8. What conclusions can you draw from the congestion map? The 1-D congestion bars show no significant congestion. There is a small over-run scattered across the core area that will have little affect on routing. This design is NOT congested.

Question 9. Is the slack better or worse than PPO2 result from Task 2 report?

The slack is about the same but you can conclude that this value is more accurately calculated because the Global Route is complete.

Question 10. Should you run the Global Route optimization?

Yes. It should be run to fix setup violations.

Question 11. Were the setup violations fixed after Global Route optimization?

Yes!

Question 12. Is the timing still met after track assignment?

The slack is positive; however, Astro can still improve this slack even further.

Question 13. Has the slack improved for the SYS_2x_CLK from the previous step?

Yes. The slack for SYS_2x_CLk is improved and met the setup cost of .1 set in the Timing Setup panel.

Question 14. How many unresolved DRCs remain after detailed routing? Do you need Search and Repair loops? Over 100s. These violations exist because DR was told not to run a Search and Repair loop. Yes, you should run repair loops to fix the unresolved DRCs.

Question 15. In which order would the Global Route, Track Assign, Search&Repair and Detail Route run? GR, TA, DR, S&R



Question 16. Which LPE mode is used to generate the timing report?

For LPE Auto mode, “Real_RC” mode is used since all signal nets are routed. The extraction mode is indicated at the top of the timing report in the Design Setup section.

Question 17. Is the timings still met after detailed route? Yes.

Question 18. Should you run the Detail Route optimization?

No. The design has no timing violations and you completed all the routing.

Question 19. Do you see any DRC errors reported? Yes. If you want to see the violation enter the command: geFirstError. Rerun Search and Repair, this time with the “rerun DRC” button selected (on). Use a small number of loops, 5.

Question 20. What is the total wire length for the signal wiring?

At the bottom of the PR Summary report, Signal Wiring Statistics (the total wire length for signal wiring) is: approximately: Total Wire Length (count): 1398406 (220708)

Question 21. Did the circuit compare?

Yes: See the “Verification Succeeded” in bright green in the upper right corner of the formality GUI You should also see a total of 0 “Failing (not equivalent) compare points in the text summary in the GUI and the UNIX window.


DFM - Design for

Manufacturing

DesSyno

8

Learning Objectives


In the previous labs, the standard cells were placed, the clock trees were synthesized, post-placement timing optimization and routing were completed. In this lab, the design will be taken through the final steps before output to GDSII format..


• Fix antenna violations

• Perform contact optimization for timing and yield improvement

• Perform DFM steps including:

• Fill notch/gap

• Metal filling

• Wide metal slotting

• Perform LVS

• Perform DRC

ign for Manufacturing Lab 8-1 psys 20-I-022 -SLG-003

Lab 8

Background

The starting cell completed from the Routing lab is used in this lab. The steps performed in this lab are usually necessary for 130nm and below process. At 90nm and below, these steps are critical to manufacturing yield and device’s performance.

SI will not be discussed in this lab due to the workshop’s time constraint and the complexity of the topic. Attend the Synopsys Astro Crosstalk virtual classroom training as a follow on to this workshop.

Lab 8-2 Design for Manufacturing Synopsys Astro 1

Lab 8




lab8/ .avntrc User defined settings/functions

design_lib_orca/ ORCA physical design library that contains DR_final cell to be used by this lab

reports/ Astro report files generate during this lab

scripts/ Scripts used during this lab optContacts.cmd Optimize the contacts

zoom_optCont.cmd Close-up view of optimized contacts

zoom_power.cmd Close-up view of VDD/VSS cuts



accessed during this lab: design_data/ Contains the ORCA design input data:

ref_lib/ Link to I/O, standard cell and macro designs star_rcxt/ Link to parasitic TLU+ model files


cb13_4m_antenna.cmd Antenna rule file


Design for Manufacturing Lab 8-3 Synopsys Astro 1

Lab 8

Lab Instructions

Task 1. Start Astro, Open Library and Cell



3. Open the cell named DR_final.

Task 2. Fix antenna violations

1. To install a set of antenna rules, load the following command file:

load "tech/cb13_4m_antenna.cmd"

2. Setup the antenna checking method:

Select Route Setup HPO Signal Route Options … Set Charge-Collecting Antenna mode to “advanced” Click “OK”

Alternatively, the command: axSetIntParam "droute" "doAntennaConx" 4 can be used to set up the method of calculating antenna ratio.

3. Check the current antenna ratio violations:

axReportAntennaRatio (geGetEditCell)

Violations will be reported in the log file or Message/Input Area following the “@@@@ Total nets not meeting constraints” string.

Question 1. Does the cell have any antenna violations?

.....................................................................................................

Question 2. When repairing antenna violations what command would you use to perform metal jumping?

.....................................................................................................


Lab 8

4. Repair the antenna violations by running Search & Repair with a loop of 10.

Question 3. Were the antenna violations cleared?

.....................................................................................................

5. Turn off atenna rule:

Select Route Setup HPO Signal Route Options … Set Charge-Collecting Antenna mode to “ignore” Click “OK”

Task 3. Add Filler Cells

1. To see before and after filler cells added, turn off the detailed route visible:

Click Window option button from the Cell window Click Route Type button at the top right of Window Options panel Unselect Visible Route Type for “detailed route” Click “Apply”, “Redraw” then “Cancel”.

Notice the empty areas not occupied by the standard cells in the core area.

2. Add filler cells between the standard cells:

Select PostPlace Filler Cell: Add Core fillers … Enter feedth9, feedth3, feedth as “Master Cell Name(s) With Metal” Enter VDD into “Connect to Power Net” field Enter VSS into “Connect to Ground Net” field Click “OK”

The empty areas in the core area are filled with “filler” cells from the library.

Question 4. In which order were the filler cells added?

.....................................................................................................

3. Make logical connections for P/G ports of the added filler cells:

Select PreRoute Connect Ports to P/G… Click “Default” Select Update Tie Up/Down option Set VDD for both Net Name and Port Pattern Select Power (VDD) or Ground (VSS) Net Type Click “Apply”. Click “Cancel” when complete

Repeat for VSS

4. Turn detailed route back to visible.


Lab 8

Task 4. Optimize Contacts

1. Zoom into an area where there are a couple of contacts:

load “scripts/zoom_optCont.cmd”

Observe how a single via is used to create a connection between two metal layers.

2. Look at the file “scripts/optContacts.cmd” then load it as follow:

load “scripts/optContacts.cmd”

Note: The contact list should include all contacts used for signal routing. The command file above instructs Astro to replace each contact cell in the left column with 2 contact cells in the second column.

3. Refresh the display and observe the contacts you looked at before.

Question 5. Do you now see two contacts replacing each single contact you observed previously?

.....................................................................................................

4. Run Search&Repair to remove new DRC violations: (Route Detail route: Search & Repair)

5. The design rule check program must be run to find new DRC violations created by the optimization of new contacts:

Select Verify DRC … Click “Default” Enter 100 for Maximum Errors Select “List Error Summary Immediately” Click “OK”

There should be a few DRC violations reported from above.

6. Run Search&Repair again and use the “rerun DRC” option:

Select Route Detail Route: Search & Repair… Set Search Repair Loop to 5 Enable “rerun DRC” option Click “OK”


Lab 8

Note: All the DRCs are removed after this S&R. It is critical that the design is DRC clean before performing metal slotting and metal filling below. To verify the design is DRC clean, you would rerun Verify DRC. You can skip this step in this lab; the report will tell you that there is no DRC violation.

Task 5. Slotting the VDD and VSS Traces

1. Set the view in the Cell window to see 200 um of the VDD and VSS ring on the top center of the chip by loading the given scheme command:

load “scripts/zoom_power.cmd”

SideSpaceOpenSlot SideClearance

Width LengthEndSpace

2. Cut slots into the VDD and VSS traces for reliability and metal density rule compliance:

Select PreRoute Slot Wires … Click “Default” Enter VDD, VSS for Net Name(s) Enter 10.0 for CutWidth Enter 100.0 for CutLength Enter 1.25 for Width Enter 5.0 for Length Enter 2.0 for SideSpace Enter 3.0 for EndSpace Enter 2.0 for SideClearance Enter 2.0 for EndClearance Select Stagger option Click “OK” or “Apply”.

Note: If you use the Apply button, you can undo the operation easily. Test the undo feature and/or additional sets of parameters if you have some extra time.


Lab 8

Task 6. Fill Notch/Gap and Wire Tracks

This procedure makes sure that DRC notches and gaps between shapes on the same layer are “fixed”.

1. Fill notch and gap to remove DRC violations:

Select Route Utility Fill Notch/Gap … Click “Default” Click “OK”

One of the very last steps before final physical verification is metal filling to meet the metal density rules. This will use up most of the remaining routing resources, so it must be executed after, all routing and related optimizations, and antenna rule fixing.

2. Zoom into the location where you observed the single contact being doubled:

load “scripts/zoom_optCont.cmd”

3. Add additional metal fill for wire density and planarization:

Select Route Utility Fill Wire Track … Click “Default” Select “self” in the Output to field Select specify for “Tie to net” then enter VSS into Net Name Set From Metal option to 2 Set To Metal option to 3 Click “OK”

Question 6. Does it make a difference in which order the metal fill or the fill notch/gap commands are run?

.....................................................................................................

Question 7. What happens if you do not select self?

.....................................................................................................

Question 8. Do the metal patterns of the CEL view look any different? (To see the density of the metal uniformity, turn off visibility of all but one metal layer at a time).

.....................................................................................................

4. Save the cell as DFM_Final.


Lab 8

Task 7. Optional: Verify LVS, DRC and Timings

1. Run LVS check to make sure that Astro’s layout in the physical domain, describes the same circuit the verilog specifies:

Select Verify LVS … Click “Default” Select “List Error Summary Immediately” Click “OK”

Question 9. After LVS are there any Open or Short Errors?

.....................................................................................................

There are many new metal shapes, each with multiple possibilities of creating mask design rule violations.

2. Run the design rule check program to check for mask rule violations:

Select Verify DRC … Click “Default” Enter 100 for Maximum Errors Select “List Error Summary Immediately” Click “OK”

This runs for a few minutes.

Question 10. Is the design DRC clean? If not, what should you do?

.....................................................................................................

3. Generate a timing report and make sure all timing is OK.

There should not be any timing violations.

Congratulations! You have completed Lab 8.



Answers / Solutions

Question 1. Does the cell have any antenna violations? Yes.

Question 2. When repairing antenna violations what command would you use to perform metal jumping? After setting the antenna rules you would then run the Search and Repair (axgSearchRepair) command with a small loop count, ~10, to make the corrections.

Question 3. Were the antenna violations cleared? Yes. Note: do not rely on the output of the Search & Repair run. You should run axReportAntennaRatio again.

Question 4. In which order were the filler cells added? feeth9, feedth3 then feedth. (from left to right as specified in the dialog box.

Question 5. Do you now see two contacts replacing each single contact you observed previously? Two.

Question 6. Does it make a difference in which order the metal fill or the fill notch/gap commands are run? Yes, if you run metal fill first, the fill notch/gap command runs much slower since there are so many more metal traces to check.

Question 7. What happens if you do not select self? A new view (.FILL) is created to store metal fill information. You must specify the new name.



Question 8. Do the metal patterns of the CEL view look any different? Yes, the contact is now surrounded by metal tracks. After LVS are there any Open or Short Errors? No!

Question 9. Is the design DRC clean? If not, what should you do? Yes, it is clean. If not, try rerunning Search&Repair with the rerun DRC button selected.


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