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AVR 8-Bit Microcontroller ATmega8A Data Sheet

Introduction

The ATmega8A is a low-power CMOS 8-bit microcontroller based on the AVR® enhanced RISCarchitecture. By executing powerful instructions in a single clock cycle, the ATmega8A achievesthroughputs close to 1 MIPS per MHz. This empowers system designer to optimize the device for powerconsumption versus processing speed.

Features

• High-performance, Low-power AVR 8-bit Microcontroller• Advanced RISC Architecture

– 130 powerful instructions - most single-clock cycle execution– 32 x 8 general purpose working registers– Fully static operation– Up to 16 MIPS throughput at 16 MHz– On-chip 2-cycle multiplier

• High Endurance Nonvolatile Memory segments– 8 KB of In-System Self-programmable Flash program memory– 512B EEPROM– 1 KB internal SRAM– Write/erase cycles: 10,000 Flash/100,000 EEPROM– Data retention: 20 years at 85°C/100 years at 25°C(1)

– Optional boot code section with independent lock bits• In-system programming by on-chip boot program• True read-while-write operation

– Programming lock for software security• Microchip QTouch® library support

– Capacitive touch buttons, sliders and wheels– QTouch and QMatrix acquisition– Up to 64 sense channels

• Peripheral Features– Two 8-bit timer/counters with separate prescaler, one compare mode– One 16-bit timer/counter with separate prescaler, compare mode, and capture mode– Real-time counter with separate oscillator– Three PWM channels– 8-channel ADC in TQFP and QFN/MLF package

© 2017 Microchip Technology Inc. Datasheet Complete 40001974A-page 1

• Eight channels 10-bit accuracy– 6-channel ADC in PDIP package

• Six channels 10-bit accuracy– Byte-oriented two-wire serial interface– Programmable serial USART– Master/slave SPI serial interface– Programmable watchdog timer with separate on-chip oscillator– On-chip analog comparator

• Special Microcontroller Features– Power-on Reset and programmable Brown-out Detection– Internal calibrated RC oscillator– External and internal interrupt sources– Five sleep modes: Idle, ADC noise reduction, power-save, power-down, and standby

• I/O and Packages– 23 programmable I/O lines– 28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF

• Operating Voltages– 2.7 - 5.5V

• Speed Grades– 0 - 16 MHz

• Power Consumption at 4 MHz, 3V, 25°C– Active: 3.6 mA– Idle mode: 1.0 mA– Power-down mode: 0.5 μA

AVR 8-Bit Microcontroller


Table of Contents

Introduction......................................................................................................................1

Features.......................................................................................................................... 1

1. Description.................................................................................................................9

2. Configuration Summary...........................................................................................10

3. Ordering Information................................................................................................11

4. Block Diagram......................................................................................................... 12

5. Pin Configurations................................................................................................... 135.1. Pin Descriptions......................................................................................................................... 155.2. Accessing 16-bit Registers.........................................................................................................17

6. I/O Multiplexing........................................................................................................20

7. Resources............................................................................................................... 22

8. Data Retention.........................................................................................................23

9. About Code Examples.............................................................................................24

10. Capacitive Touch Sensing....................................................................................... 2510.1. QTouch Library...........................................................................................................................25

11. AVR CPU Core........................................................................................................ 2611.1. Overview.................................................................................................................................... 2611.2. ALU – Arithmetic Logic Unit....................................................................................................... 2711.3. Status Register...........................................................................................................................2711.4. General Purpose Register File...................................................................................................3011.5. Stack Pointer..............................................................................................................................3111.6. Instruction Execution Timing...................................................................................................... 3211.7. Reset and Interrupt Handling..................................................................................................... 33

12. AVR Memories.........................................................................................................3512.1. Overview.................................................................................................................................... 3512.2. In-System Reprogrammable Flash Program Memory................................................................3512.3. SRAM Data Memory.................................................................................................................. 3612.4. EEPROM Data Memory............................................................................................................. 3812.5. I/O Memory.................................................................................................................................3912.6. Register Description...................................................................................................................39

13. System Clock and Clock Options............................................................................ 4613.1. Clock Systems and their Distribution..........................................................................................46


13.2. Clock Sources............................................................................................................................ 4713.3. Crystal Oscillator........................................................................................................................ 4813.4. Low-frequency Crystal Oscillator................................................................................................4913.5. External RC Oscillator................................................................................................................5013.6. Calibrated Internal RC Oscillator................................................................................................5113.7. External Clock............................................................................................................................ 5113.8. Timer/Counter Oscillator.............................................................................................................5213.9. Register Description...................................................................................................................52

14. Power Management and Sleep Modes................................................................... 5414.1. Sleep Modes.............................................................................................................................. 5414.2. Idle Mode....................................................................................................................................5514.3. ADC Noise Reduction Mode...................................................................................................... 5514.4. Power-down Mode..................................................................................................................... 5514.5. Power-save Mode...................................................................................................................... 5514.6. Standby Mode............................................................................................................................ 5614.7. Minimizing Power Consumption.................................................................................................5614.8. Register Description...................................................................................................................57

15. System Control and Reset.......................................................................................5915.1. Resetting the AVR...................................................................................................................... 5915.2. Reset Sources............................................................................................................................5915.3. Internal Voltage Reference.........................................................................................................6215.4. Watchdog Timer......................................................................................................................... 6315.5. Timed Sequences for Changing the Configuration of the Watchdog Timer............................... 6315.6. Register Description...................................................................................................................64

16. Interrupts................................................................................................................. 6816.1. Interrupt Vectors in ATmega8A.................................................................................................. 6816.2. Register Description...................................................................................................................73

17. External Interrupts................................................................................................... 7617.1. Register Description...................................................................................................................76

18. I/O Ports.................................................................................................................. 8018.1. Overview.................................................................................................................................... 8018.2. Ports as General Digital I/O........................................................................................................8118.3. Alternate Port Functions.............................................................................................................8418.4. Register Description...................................................................................................................93

19. 8-bit Timer/Counter0..............................................................................................10419.1. Features................................................................................................................................... 10419.2. Overview.................................................................................................................................. 10419.3. Timer/Counter Clock Sources.................................................................................................. 10519.4. Counter Unit............................................................................................................................. 10519.5. Operation..................................................................................................................................10619.6. Timer/Counter Timing Diagrams.............................................................................................. 10619.7. Register Description.................................................................................................................106



20. Timer/Counter0 and Timer/Counter1 Prescalers................................................... 11120.1. Overview...................................................................................................................................11120.2. Internal Clock Source................................................................................................................11120.3. Prescaler Reset........................................................................................................................ 11120.4. External Clock Source.............................................................................................................. 11120.5. Register Description................................................................................................................. 112

21. 16-bit Timer/Counter1............................................................................................11421.1. Features................................................................................................................................... 11421.2. Overview...................................................................................................................................11421.3. Accessing 16-bit Registers....................................................................................................... 11721.4. Timer/Counter Clock Sources...................................................................................................11921.5. Counter Unit............................................................................................................................. 11921.6. Input Capture Unit.................................................................................................................... 12021.7. Output Compare Units..............................................................................................................12221.8. Compare Match Output Unit.....................................................................................................12421.9. Modes of Operation..................................................................................................................12521.10. Timer/Counter Timing Diagrams.............................................................................................. 13321.11. Register Description.................................................................................................................134

22. 8-bit Timer/Counter2 with PWM and Asynchronous Operation.............................15022.1. Features................................................................................................................................... 15022.2. Overview.................................................................................................................................. 15022.3. Timer/Counter Clock Sources.................................................................................................. 15122.4. Counter Unit............................................................................................................................. 15122.5. Output Compare Unit............................................................................................................... 15222.6. Compare Match Output Unit.....................................................................................................15422.7. Modes of Operation..................................................................................................................15522.8. Timer/Counter Timing Diagrams.............................................................................................. 15922.9. Asynchronous Operation of the Timer/Counter........................................................................16122.10. Timer/Counter Prescaler.......................................................................................................... 16322.11. Register Description.................................................................................................................163

23. SPI – Serial Peripheral Interface........................................................................... 17323.1. Features................................................................................................................................... 17323.2. Overview.................................................................................................................................. 17323.3. SS Pin Functionality................................................................................................................. 17623.4. Data Modes..............................................................................................................................17723.5. Register Description.................................................................................................................178

24. USART - Universal Synchronous and Asynchronous serial Receiver andTransmitter.............................................................................................................18324.1. Features................................................................................................................................... 18324.2. Overview.................................................................................................................................. 18324.3. Clock Generation......................................................................................................................18524.4. Frame Formats.........................................................................................................................18824.5. USART Initialization................................................................................................................. 189



24.6. Data Transmission – The USART Transmitter......................................................................... 19024.7. Data Reception – The USART Receiver.................................................................................. 19224.8. Asynchronous Data Reception.................................................................................................19624.9. Multi-Processor Communication Mode.................................................................................... 19924.10. Accessing UBRRH/UCSRC Registers.....................................................................................20024.11. Register Description.................................................................................................................20124.12. Examples of Baud Rate Setting............................................................................................... 210

25. TWI - Two-wire Serial Interface............................................................................. 21425.1. Features................................................................................................................................... 21425.2. Overview.................................................................................................................................. 21425.3. Two-Wire Serial Interface Bus Definition..................................................................................21625.4. Data Transfer and Frame Format.............................................................................................21725.5. Multi-master Bus Systems, Arbitration and Synchronization....................................................22025.6. Using the TWI...........................................................................................................................22225.7. Multi-master Systems and Arbitration...................................................................................... 23925.8. Register Description.................................................................................................................241

26. AC - Analog Comparator....................................................................................... 24826.1. Overview.................................................................................................................................. 24826.2. Analog Comparator Multiplexed Input......................................................................................24826.3. Register Description.................................................................................................................249

27. ADC - Analog to Digital Converter.........................................................................25327.1. Features................................................................................................................................... 25327.2. Overview.................................................................................................................................. 25327.3. Starting a Conversion...............................................................................................................25527.4. Prescaling and Conversion Timing...........................................................................................25527.5. Changing Channel or Reference Selection..............................................................................25727.6. ADC Noise Canceler................................................................................................................ 25827.7. ADC Conversion Result........................................................................................................... 26227.8. Register Description.................................................................................................................263

28. BTLDR - Boot Loader Support – Read-While-Write Self-Programming................ 27228.1. Features................................................................................................................................... 27228.2. Overview.................................................................................................................................. 27228.3. Application and Boot Loader Flash Sections............................................................................27228.4. Read-While-Write and No Read-While-Write Flash Sections...................................................27328.5. Boot Loader Lock Bits.............................................................................................................. 27528.6. Entering the Boot Loader Program...........................................................................................27628.7. Addressing the Flash During Self-Programming......................................................................27728.8. Self-Programming the Flash.....................................................................................................27828.9. Register Description.................................................................................................................285

29. MEMPROG- Memory Programming......................................................................28829.1. Program and Data Memory Lock Bits...................................................................................... 28829.2. Fuse Bits.................................................................................................................................. 28929.3. Signature Bytes........................................................................................................................291



29.4. Calibration Byte........................................................................................................................29129.5. Page Size.................................................................................................................................29129.6. Parallel Programming Parameters, Pin Mapping, and Commands..........................................29229.7. Parallel Programming...............................................................................................................29429.8. Serial Downloading.................................................................................................................. 30229.9. Serial Programming Pin Mapping.............................................................................................302

30. Electrical Characteristics – TA = -40°C to 85°C.................................................... 30730.1. DC Characteristics................................................................................................................... 30730.2. Speed Grades.......................................................................................................................... 30930.3. Clock Characteristics................................................................................................................30930.4. System and Reset Characteristics........................................................................................... 31030.5. Two-wire Serial Interface Characteristics................................................................................. 31130.6. SPI Timing Characteristics....................................................................................................... 31330.7. ADC Characteristics.................................................................................................................314

31. Electrical Characteristics – TA = -40°C to 105°C.................................................. 31631.1. DC Characteristics................................................................................................................... 316

32. Typical Characteristics – TA = -40°C to 85°C........................................................31932.1. Active Supply Current...............................................................................................................31932.2. Idle Supply Current...................................................................................................................32332.3. Power-down Supply Current.................................................................................................... 32632.4. Power-save Supply Current..................................................................................................... 32732.5. Standby Supply Current........................................................................................................... 32832.6. Pin Pull-up................................................................................................................................33132.7. Pin Driver Strength...................................................................................................................33332.8. Pin Thresholds and Hysteresis.................................................................................................33732.9. Bod Thresholds and Analog Comparator Offset...................................................................... 34232.10. Internal Oscillator Speed..........................................................................................................34432.11. Current Consumption of Peripheral Units.................................................................................35132.12. Current Consumption in Reset and Reset Pulsewidth.............................................................354

33. Typical Characteristics – TA = -40°C to 105°C......................................................35633.1. ATmega8A Typical Characteristics...........................................................................................356

34. Register Summary.................................................................................................385

35. Instruction Set Summary....................................................................................... 387

36. Packaging Information...........................................................................................39136.1. 32-pin 32A................................................................................................................................39136.2. 28-pin 28P3..............................................................................................................................39236.3. 32-pin 32M1-A..........................................................................................................................393

37. Errata.....................................................................................................................39437.1. ATmega8A, rev. L.....................................................................................................................394



38. Appendix A: Revision History................................................................................ 396

The Microchip Web Site.............................................................................................. 398

Customer Change Notification Service........................................................................398

Customer Support....................................................................................................... 398

Microchip Devices Code Protection Feature............................................................... 398

Legal Notice.................................................................................................................399

Trademarks................................................................................................................. 399

Quality Management System Certified by DNV...........................................................400

Worldwide Sales and Service......................................................................................401



1. DescriptionThe AVR® core combines a rich instruction set with 32 general purpose working registers. All the 32registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers tobe accessed in one single instruction executed in one clock cycle. The resulting architecture is more codeefficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATmega8A provides the following features: 8 KB of In-System Programmable Flash with Read-While-Write capabilities, 512 B of EEPROM, 1 KB of SRAM, 23 general purpose I/O lines, 32 generalpurpose working registers, three flexible timer/counters with compare modes, internal and externalinterrupts, a serial programmable USART, one byte oriented two-wire serial interface, a 6-channel ADC(eight channels in TQFP and QFN/MLF packages) with 10-bit accuracy, a programmable Watchdog timerwith internal oscillator, an SPI serial port, and five software selectable power saving modes. The Idlemode stops the CPU while allowing the SRAM, timer/counters, one SPI port, and interrupt system tocontinue functioning. The Power-down mode saves the register contents but freezes the oscillator,disabling all other chip functions until the next Interrupt or Hardware Reset. In Power-save mode, theasynchronous timer continues to run, allowing the user to maintain a timer base while the rest of thedevice is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules exceptasynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode,the crystal/resonator oscillator is running while the rest of the device is sleeping. This allows very faststart-up combined with low-power consumption.

Microchip offers the QTouch library for embedding capacitive touch buttons, sliders and wheelsfunctionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers robustsensing and includes fully debounced reporting of touch keys and includes Adjacent Key SuppressionTM(AKSTM) technology for unambiguous detection of key events. The easy-to-use QTouch Composer allowsyou to explore, develop and debug your own touch applications.

The device is manufactured using Microchip’s high density nonvolatile memory technology. The on-chipISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, bya conventional nonvolatile memory programmer, or by an on-chip Boot program running on the AVR core.The Boot program can use any interface to download the application program in the Application Flashmemory. Software in the Boot Flash section will continue to run while the Application Flash section isupdated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-SystemSelf-Programmable Flash on a monolithic chip, the ATmega8A is a powerful microcontroller that providesa highly flexible and cost effective solution to many embedded control applications.

The device is supported with a full suite of program and system development tools including: CCompilers, macro assemblers, program debugger/simulators, In-Circuit Emulators, and evaluation kit.

AVR 8-Bit MicrocontrollerDescription


2. Configuration SummaryFeatures ATmega8A

Pin count 32

Flash (KB) 8

SRAM (KB) 1

EEPROM (Bytes) 512

General Purpose I/O pins 23

SPI 1

TWI (I2C) 1

USART 1

ADC 10-bit 15 ksps

ADC channels 6 (8 in TQFP and QFN/MLF packages)

AC propagation delay Typ 400 ns

8-bit Timer/Counters 2

16-bit Timer/Counters 1

PWM channels 3

RC Oscillator +/-3%

Operating voltage 2.7 - 5.5V

Max operating frequency 16 MHz

Temperature range -40°C to +105°C

AVR 8-Bit MicrocontrollerConfiguration Summary


3. Ordering InformationSpeed (MHz) Power Supply Ordering Code(2) Package(1) Operational Range

16 2.7 - 5.5V

ATmega8A-AUATmega8A-AUR(3)

ATmega8A-PU

ATmega8A-MU

ATmega8A-MUR(3)

32A32A

28P3

32M1-A

32M1-A

Industrial (-40oC to 85oC)

ATmega8A-ANATmega8A-ANR(3)

ATmega8A-MN

ATmega8A-MNR(3)

ATmega8A-PN

32A32A

32M1-A

32M1-A

28P3

Extended (-40oC to 105oC)

Note: 1. This device can also be supplied in wafer form. Please contact your local Microchip sales office for

detailed ordering information and minimum quantities.2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances

(RoHS directive). Also Halide free and fully Green.3. Tape and Reel

Package Type

32A 32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)

28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

32M1-A 32-pad, 5 x 5 x 1.0mm body, lead pitch 0.50mm, Quad Flat No-Lead/Micro Lead FramePackage (QFN/MLF)

AVR 8-Bit MicrocontrollerOrdering Information


4. Block DiagramFigure 4-1. Block Diagram

CPU

USART

ADCADC[7:0]AREF

RxDTxDXCK

I/OPORTS

SRAM

EXTINT

FLASH

NVM programming

TC 0(8-bit)

SPI

ACAIN0AIN1

ADCMUX

EEPROMEEPROMIF

TC 1(16-bit)

OC1A/BT1ICP1

TC 2(8-bit async)

TWISDASCL

InternalReference

Watchdog Timer

Power management

and clock control

VCC

GND

Power SupervisionPOR/BOD &

RESET

XTAL2/TOSC2

RESET

XTAL1/TOSC1

INT[1:0]

T0

MISOMOSISCKSS

OC2

PB[7:0]PC[6:0]PD[7:0]

Clock generation

1/2/4/8MHzCalib RC

1MHz int osc

32.768kHz XOSC

External clock

8 MHzCrystal Osc

DATABUS

12MHzExternal RC Osc

PARPROG

SerialProgramming

AVR 8-Bit MicrocontrollerBlock Diagram


5. Pin ConfigurationsFigure 5-1. PDIP

1

2

3

4

5

6

7

8

9

13

10

11

12

14

GND

15

20

19

18

17

16

GND

24

23

22

21

28

27

26

25

AREF

AVCC

VCC

(RESET) PC6

(RXD) PD0

(TXD) PD1

(INT0) PD2

(INT1) PD3

(XCK/T0) PD4

(XTAL1/TOSC1) PB6

(XTAL2/TOSC2) PB7

(T1) PD5

(AIN0) PD6

(AIN1) PD7

(ICP1) PB0 PB1 (OC1A)

PB2 (SS/OC1B)

PB3 (MOSI/OC2)

PB4 (MISO)

PB5 (SCK)

PC0 (ADC0)

PC1 (ADC1)

PC2 (ADC2)

PC3 (ADC3)

PC4 (ADC4/SDA)

PC5 (ADC5/SCL)

AVR 8-Bit MicrocontrollerPin Configurations


Figure 5-2. TQFP Top View

1

2

3

4

32 31 30 29 28 27 26

5

6

7

8

24

23

22

21

20

19

18

17

25

9 10 11 12 13 14 15 16

PD0

(RX

D)

PD1

(TX

D)

PD2

(INT0

)

PC6

(RES

ET)

PC2

(AD

C2)

PC3

(AD

C3)

PC4

(AD

C4/S

DA

)

PC5

(AD

C5/S

CL)

PC0 (ADC0)

PC1 (ADC1)

GND

ADC6

AVCC

PB5 (SCK)

AREF

ADC7

(INT1) PD3

(XCK/T0) PD4

GND

VCC

GND

VCC

(XTAL1/TOSC1) PB6

(XTAL2/TOSC2) PB7

(T1)

PD

5

(AIN

0) P

D6

(AIN

1) P

D7

(ICP1

) PB0

(OC1

A) P

B1

(SS/

OC1

B) P

B2

(MO

SI/O

C2) P

B3

(MIS

O) P

B4



Figure 5-3. MLF Top View

1

2

3

4

32 31 30 29 28 27 26

5

6

7

8

24

23

22

21

20

19

18

17

25

9 10 11 12 13 14 15 16

PD0

(RX

D)

PD1

(TX

D)

PD2

(INT0

)

PC6

(RES

ET)

PC2

(AD

C2)

PC3

(AD

C3)

PC4

(AD

C4/S

DA

)

PC5

(AD

C5/S

CL)

PC0 (ADC0)

PC1 (ADC1)

GND

ADC6

AVCC

PB5 (SCK)

AREF

ADC7

(INT1) PD3

(XCK/T0) PD4

GND

VCC

GND

VCC

(XTAL1/TOSC1) PB6

(XTAL2/TOSC2) PB7

(T1)

PD

5

(AIN

0) P

D6

(AIN

1) P

D7

(ICP1

) PB0

(OC1

A) P

B1

(SS/

OC1

B) P

B2

(MO

SI/O

C2) P

B3

(MIS

O) P

B4NOTE:The large center pad underneath the MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the PCB to ensure goodmechanical stability. If the center pad is left unconneted, thepackage might loosen from the PCB.

5.1 Pin Descriptions

5.1.1 VCCDigital supply voltage.

5.1.2 GNDGround.

5.1.3 Port B (PB7:PB0) – XTAL1/XTAL2/TOSC1/TOSC2Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port Boutput buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The PortB pins are tri-stated when a reset condition becomes active, even if the clock is not running.



Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillatoramplifier and input to the internal clock operating circuit.

Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillatoramplifier.

If the Internal Calibrated RC Oscillator is used as chip clock source, PB7:6 is used as TOSC2:1 input forthe Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.

The various special features of Port B are elaborated in Alternate Functions of Port B and System Clockand Clock Options.

5.1.4 Port C (PC5:PC0)Port C is an 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port Coutput buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The PortC pins are tri-stated when a reset condition becomes active, even if the clock is not running.

5.1.5 PC6/RESETIf the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristicsof PC6 differ from those of the other pins of Port C.

If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longerthan the minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulselength is given in Table 30-5. Shorter pulses are not guaranteed to generate a Reset.

The various special features of Port C are elaborated in Alternate Functions of Port C.

5.1.6 Port D (PD7:PD0)Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port Doutput buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The PortD pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATmega8A as listed in AlternateFunctions of Port D.

5.1.7 RESETReset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even ifthe clock is not running. The minimum pulse length is given in Table 30-5. Shorter pulses are notguaranteed to generate a reset.

5.1.8 AVCCAVCC is the supply voltage pin for the A/D Converter, Port C (3:0), and ADC (7:6). It should be externallyconnected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC througha low-pass filter. Note that Port C (5:4) use digital supply voltage, VCC.

5.1.9 AREFAREF is the analog reference pin for the A/D Converter.

5.1.10 ADC7:6 (TQFP and QFN/MLF Package Only)In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter. These pinsare powered from the analog supply and serve as 10-bit ADC channels.



5.2 Accessing 16-bit RegistersThe TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bitdata bus. A 16-bit register must be byte accessed using two read or write operations. The 16-bit timer hasa single 8-bit register for temporary storing of the High byte of the 16-bit access. The same temporaryregister is shared between all 16-bit registers within the 16-bit timer. Accessing the Low byte triggers the16-bit read or write operation. When the Low byte of a 16-bit register is written by the CPU, the High bytestored in the temporary register, and the Low byte written are both copied into the 16-bit register in thesame clock cycle. When the Low byte of a 16-bit register is read by the CPU, the High byte of the 16-bitregister is copied into the temporary register in the same clock cycle as the Low byte is read.

Not all 16-bit accesses uses the temporary register for the High byte. Reading the OCR1A/B 16-bitregisters does not involve using the temporary register.

To do a 16-bit write, the High byte must be written before the Low byte. For a 16-bit read, the Low bytemust be read before the High byte.

The following code examples show how to access the 16-bit Timer Registers assuming that no interruptsupdates the temporary register. The same principle can be used directly for accessing the OCR1A/B andICR1 Registers. Note that when using “C”, the compiler handles the 16-bit access.

Assembly Code Example(1)

:.; Set TCNT1 to 0x01FFldi r17,0x01ldi r16,0xFFout TCNT1H,r17out TCNT1L,r16; Read TCNT1 into r17:r16in r16,TCNT1Lin r17,TCNT1H :.

C Code Example(1)

unsigned int i; :./* Set TCNT1 to 0x01FF */TCNT1 = 0x1FF;/* Read TCNT1 into i */i = TCNT1; :.

Note: 1. See About Code Examples.

The assembly code example returns the TCNT1 value in the r17:r16 Register pair.

It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occursbetween the two instructions accessing the 16-bit register, and the interrupt code updates the temporaryregister by accessing the same or any other of the 16-bit Timer Registers, then the result of the accessoutside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code updatethe temporary register, the main code must disable the interrupts during the 16-bit access.

The following code examples show how to do an atomic read of the TCNT1 Register contents. Readingany of the OCR1A/B or ICR1 Registers can be done by using the same principle.



Asesmbly Code Example(1)

TIM16_ReadTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ; Restore global interrupt flag out SREG,r18 ret

C Code Example(1)

unsigned int TIM16_ReadTCNT1( void ){ unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into i */ i = TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i;}


The assembly code example returns the TCNT1 value in the r17:r16 Register pair.

The following code examples show how to do an atomic write of the TCNT1 Register contents. Writingany of the OCR1A/B or ICR1 Registers can be done by using the same principle.

Assembly Code Example(1)

TIM16_WriteTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Set TCNT1 to r17:r16 out TCNT1H,r17 out TCNT1L,r16 ; Restore global interrupt flag out SREG,r18 ret

C Code Example(1)

void TIM16_WriteTCNT1( unsigned int i ){ unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNT1 to i */ TCNT1 = i; /* Restore global interrupt flag */ SREG = sreg;}




The assembly code example requires that the r17:r16 Register pair contains the value to be written toTCNT1.

Related LinksAbout Code Examples



6. I/O MultiplexingEach pin is by default controlled by the PORT as a general purpose I/O and alternatively it can beassigned to one of the peripheral functions.

The following table describes the peripheral signals multiplexed to the PORT I/O pins.

Table 6-1. 32-Pin TQFP and MLF: PORT Function Multiplexing

No PAD32 EXTINT ADC/AC OSC T/C # 0 T/C # 1 USART I2C SPI

1 PD[3] INT1

2 PD[4] T0 XCK0

3 GND

4 VCC

5 GND

6 VCC

7 PB[6] XTAL1/TOSC1

8 PB[7] XTAL2/TOSC2

9 PD[5] T1

10 PD[6] AIN0

11 PD[7] AIN1

12 PB[0] ICP1

13 PB[1] OC1A

14 PB[2] OC1B SS0

15 PB[3] OC2 MOSI0

16 PB[4] MISO0

17 PB[5] SCK0

18 AVCC

19 ADC6 ADC6

20 AREF

21 GND

22 ADC7 ADC7

23 PC[0] ADC0

24 PC[1] ADC1

25 PC[2] ADC2

26 PC[3] ADC3

27 PC[4] ADC4 SDA0

28 PC[5] ADC5 SCL0

29 PC[6]/RESET

30 PD[0] RXD0

AVR 8-Bit MicrocontrollerI/O Multiplexing



31 PD[1] TXD0

32 PD[2] INT0

Table 6-2. 28-Pin PDIP: PORT Function Multiplexing


1 PC[6]/RESET

2 PD[0] RXD0

3 PD[1] TXD0

4 PD[2] INT0

5 PD[3] INT1

6 PD[4] T0 XCK0

7 VCC

8 GND

9 PB[6] XTAL1/TOSC1

10 PB[7] XTAL2/TOSC2

11 PD[5] T1

12 PD[6] AIN0

13 PD[7] AIN1

14 PB[0] ICP1

15 PB[1] OC1A

16 PB[2] OC1B SS0

17 PB[3] OC2 MOSI0

18 PB[4] MISO0

19 PB[5] SCK0

20 AVCC

21 AREF

22 GND

23 PC[0] ADC0

24 PC[1] ADC1

25 PC[2] ADC2

26 PC[3] ADC3

27 PC[4] ADC4 SDA0

28 PC[5] ADC5 SCL0

AVR 8-Bit MicrocontrollerI/O Multiplexing


7. ResourcesA comprehensive set of development tools, application notes and datasheets are available for downloadon http://www.atmel.com/avr.

AVR 8-Bit MicrocontrollerResources


http://www.atmel.com/avr

8. Data RetentionReliability Qualification results show that the projected data retention failure rate is much less than 1 PPMover 20 years at 85°C or 100 years at 25°C.

AVR 8-Bit MicrocontrollerData Retention


9. About Code ExamplesThis datasheet contains simple code examples that briefly show how to use various parts of the device.These code examples assume that the part specific header file is included before compilation. Be awarethat not all C compiler vendors include bit definitions in the header files and interrupt handling in C iscompiler dependent. Please confirm with the C compiler documentation for more details.

AVR 8-Bit MicrocontrollerAbout Code Examples


10. Capacitive Touch Sensing

10.1 QTouch LibraryThe QTouch® library provides a simple to use solution to realize touch sensitive interfaces on most AVR®

microcontrollers. The QTouch library includes support for the QTouch and QMatrix™ acquisition methods.

Touch sensing can be added to any application by linking the appropriate QTouch library for the AVRmicrocontroller. This is done by using a simple set of APIs to define the touch channels and sensors, andthen calling the touch sensing API’s to retrieve the channel information and determine the touch sensorstates.

The QTouch library is FREE and downloadable from QTouch Library . For implementation details andother information, refer to the QTouch Library User Guide - also available for download from theMicrochip website.

AVR 8-Bit MicrocontrollerCapacitive Touch Sensing


http://www.microchip.com/developmenttools/productdetails.aspx?partno=atmel+qtouch+libraryhttp://ww1.microchip.com/downloads/en/DeviceDoc/doc8207.pdf

11. AVR CPU Core

11.1 OverviewThis section discusses the AVR core architecture in general. The main function of the CPU core is toensure correct program execution. The CPU must therefore be able to access memories, performcalculations, control peripherals, and handle interrupts.

Figure 11-1. Block Diagram of the AVR MCU Architecture

Register file

Flash program memory

Program counter

Instruction register

Instruction decode

Data memory

ALUStatus register

R0R1R2R3R4R5R6R7R8R9

R10R11R12R13R14R15R16R17R18R19R20R21R22R23R24R25

R26 (XL)R27 (XH)R28 (YL)R29 (YH)R30 (ZL)R31 (ZH)

Stack pointer

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separatememories and buses for program and data. Instructions in the Program memory are executed with asingle level pipelining. While one instruction is being executed, the next instruction is pre-fetched from theProgram memory. This concept enables instructions to be executed in every clock cycle. The Programmemory is In-System Reprogrammable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clockcycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALUoperation, two operands are output from the Register File, the operation is executed, and the result isstored back in the Register File – in one clock cycle.

AVR 8-Bit MicrocontrollerAVR CPU Core


Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Spaceaddressing – enabling efficient address calculations. One of the these address pointers can also be usedas an address pointer for look up tables in Flash Program memory. These added function registers arethe 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and aregister. Single register operations can also be executed in the ALU. After an arithmetic operation, theStatus Register is updated to reflect information about the result of the operation.

The Program flow is provided by conditional and unconditional jump and call instructions, able to directlyaddress the whole address space. Most AVR instructions have a single 16-bit word format. EveryProgram memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot program section and the Applicationprogram section. Both sections have dedicated Lock Bits for write and read/write protection. The SPMinstruction that writes into the Application Flash memory section must reside in the Boot program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack.The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is onlylimited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in thereset routine (before subroutines or interrupts are executed). The Stack Pointer SP is read/writeaccessible in the I/O space. The data SRAM can easily be accessed through the five different addressingmodes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional global interruptenable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vectortable. The interrupts have priority in accordance with their Interrupt Vector position. The lower theInterrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI,and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locationsfollowing those of the Register File, 0x20 - 0x5F.

11.2 ALU – Arithmetic Logic UnitThe high-performance AVR ALU operates in direct connection with all the 32 general purpose workingregisters. Within a single clock cycle, arithmetic operations between general purpose registers orbetween a register and an immediate are executed. The ALU operations are divided into three maincategories: arithmetic, logical, and bit functions. Some implementations of the architecture provide apowerful multiplier supporting both signed/unsigned multiplication and fractional format. See theInstruction Set section for a detailed description.

11.3 Status RegisterThe Status Register contains information about the result of the most recently executed arithmeticinstruction. This information can be used for altering program flow in order to perform conditionaloperations. Note that the Status Register is updated after all ALU operations, as specified in theInstruction Set Reference. This will in many cases remove the need for using the dedicated compareinstructions, resulting in faster and more compact code.



The Status Register is not automatically stored when entering an interrupt routine and restored whenreturning from an interrupt. This must be handled by software.



11.3.1 SREG – The AVR Status Register

Name: SREGOffset: 0x3F [ID-0000035c]Reset: 0x00Property: When addressing I/O Registers as data space the offset address is 0x5F

When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. Whenaddressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offsetaddresses.

Bit 7 6 5 4 3 2 1 0 I T H S V N Z C

Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0

Bit 7 – I Global Interrupt EnableThe Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interruptenable control is then performed in separate control registers. If the Global Interrupt Enable Register iscleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enablesubsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLIinstructions, as described in the Instruction Set Reference.

Bit 6 – T Bit Copy StorageThe Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination forthe operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, anda bit in T can be copied into a bit in a register in the Register File by the BLD instruction.

Bit 5 – H Half Carry FlagThe Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCDarithmetic. See the “Instruction Set Description” for detailed information.

Bit 4 – S Sign Bit, S = N ⊕ VThe S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement OverflowFlag V. See the “Instruction Set Description” for detailed information.

Bit 3 – V Two’s Complement Overflow FlagThe Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction SetDescription” for detailed information.

Bit 2 – N Negative FlagThe Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “InstructionSet Description” for detailed information.

Bit 1 – Z Zero FlagThe Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction SetDescription” for detailed information.



Bit 0 – C Carry FlagThe Carry Flag C indicates a Carry in an arithmetic or logic operation. See the “Instruction SetDescription” for detailed information.

11.4 General Purpose Register FileThe Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve therequired performance and flexibility, the following input/output schemes are supported by the RegisterFile:

• One 8-bit output operand and one 8-bit result input.• Two 8-bit output operands and one 8-bit result input.• Two 8-bit output operands and one 16-bit result input.• One 16-bit output operand and one 16-bit result input.

The following figure shows the structure of the 32 general purpose working registers in the CPU.

Figure 11-2. AVR CPU General Purpose Working Registers7 0 Addr.

R0 0x00

R1 0x01

R2 0x02

…

R13 0x0D

General R14 0x0E

Purpose R15 0x0F

Working R16 0x10

Registers R17 0x11

…

R26 0x1A X-register Low Byte

R27 0x1B X-register High Byte

R28 0x1C Y-register Low Byte

R29 0x1D Y-register High Byte

R30 0x1E Z-register Low Byte

R31 0x1F Z-register High Byte

Most of the instructions operating on the Register File have direct access to all registers, and most ofthem are single cycle instructions.

As shown in the figure above, each register is also assigned a Data memory address, mapping themdirectly into the first 32 locations of the user Data Space. Although not being physically implemented asSRAM locations, this memory organization provides great flexibility in access of the registers, as the X-,Y-, and Z-pointer Registers can be set to index any register in the file.

11.4.1 The X-register, Y-register and Z-registerThe registers R26:R31 have some added functions to their general purpose usage. These registers are16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X,Y and Z are defined as described in the following figure.



Figure 11-3. The X-, Y- and Z-Registers15 XH XL 0

X-register 7 0 7 0

R27 (0x1B) R26 (0x1A)

15 YH YL 0

Y-register 7 0 7 0

R29 (0x1D) R28 (0x1C)

15 ZH ZL 0

Z-register 7 0 7 0

R31 (0x1F) R30 (0x1E)

In the different addressing modes these address registers have functions as fixed displacement,automatic increment, and automatic decrement (see the Instruction Set Reference for details).

11.5 Stack PointerThe Stack is mainly used for storing temporary data, for storing local variables and for storing returnaddresses after interrupts and subroutine calls. Note that the Stack is implemented as growing fromhigher to lower memory locations. The Stack Pointer Register always points to the top of the Stack. TheStack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located.A Stack PUSH command will decrease the Stack Pointer.

The Stack in the data SRAM must be defined by the program before any subroutine calls are executed orinterrupts are enabled. Initial Stack Pointer value equals the last address of the internal SRAM and theStack Pointer must be set to point above start of the SRAM, see Figure Data Memory Map in SRAM DataMemory.

See table below for Stack Pointer details.

Table 11-1. Stack Pointer instructions

Instruction Stack pointer Description

PUSH Decremented by 1 Data is pushed onto the stack

CALLICALLRCALL

Decremented by 2 Return address is pushed onto the stack with a subroutine call orinterrupt

POP Incremented by 1 Data is popped from the stack

RETRETI

Incremented by 2 Return address is popped from the stack with return from subroutine orreturn from interrupt

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actuallyused is implementation dependent. Note that the data space in some implementations of the AVRarchitecture is so small that only SPL is needed. In this case, the SPH Register will not be present.

Related LinksSRAM Data Memory



11.5.1 SPH and SPL - Stack Pointer High and Stack Pointer Low RegisterBit 15 14 13 12 11 10 9 8

0x3E SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH

0x3D SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

7 6 5 4 3 2 1 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value0

0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

11.6 Instruction Execution TimingThis section describes the general access timing concepts for instruction execution. The AVR CPU isdriven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internalclock division is used.

The following figure shows the parallel instruction fetches and instruction executions enabled by theHarvard architecture and the fast-access Register File concept. This is the basic pipelining concept toobtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions perclocks, and functions per power-unit.

Figure 11-4. The Parallel Instruction Fetches and Instruction Executions

clk

1st Instruction Fetch1st Instruction Execute

2nd Instruction Fetch2nd Instruction Execute

3rd Instruction Fetch3rd Instruction Execute

4th Instruction Fetch

T1 T2 T3 T4

CPU

The next figure shows the internal timing concept for the Register File. In a single clock cycle an ALUoperation using two register operands is executed, and the result is stored back to the destinationregister.

Figure 11-5. Single Cycle ALU Operation

Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

clkCPU



11.7 Reset and Interrupt HandlingThe Atmel AVR provides several different interrupt sources. These interrupts and the separate ResetVector each have a separate Program Vector in the Program memory space. All interrupts are assignedindividual enable bits which must be written logic one together with the Global Interrupt Enable bit in theStatus Register in order to enable the interrupt. Depending on the Program Counter value, interrupts maybe automatically disabled when Boot Lock Bits BLB02 or BLB12 are programmed. This feature improvessoftware security. See the section Memory Programming for details.

The lowest addresses in the Program memory space are by default defined as the Reset and InterruptVectors. The complete list of Vectors is shown in Interrupts . The list also determines the priority levels ofthe different interrupts. The lower the address the higher is the priority level. RESET has the highestpriority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to thestart of the boot Flash section by setting the Interrupt Vector Select (IVSEL) bit in the General InterruptControl Register (GICR). Refer to Interrupts for more information. The Reset Vector can also be moved tothe start of the boot Flash section by programming the BOOTRST Fuse, see Boot Loader Support –Read-While-Write Self-Programming.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. Theuser software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can theninterrupt the current interrupt routine. The I-bit is automatically set when a Return from Interruptinstruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the InterruptFlag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order toexecute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. InterruptFlags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interruptcondition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set andremembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or moreinterrupt conditions occur while the global interrupt enable bit is cleared, the corresponding InterruptFlag(s) will be set and remembered until the global interrupt enable bit is set, and will then be executedby order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts donot necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled,the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one moreinstruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restoredwhen returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. Nointerrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLIinstruction. The following example shows how this can be used to avoid interrupts during the timedEEPROM write sequence.

Assembly Code Example

in r16, SREG ; store SREG valuecli ; disable interrupts during timed sequencesbi EECR, EEMWE ; start EEPROM write



sbi EECR, EEWEout SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;cSREG = SREG; /* store SREG value *//* disable interrupts during timed sequence */_CLI();EECR |= (1

12. AVR Memories

12.1 OverviewThis section describes the different memories in the ATmega8A. The AVR architecture has two mainmemory spaces, the Data memory and the Program Memory space. In addition, the ATmega8A featuresan EEPROM Memory for data storage. All three memory spaces are linear and regular.

12.2 In-System Reprogrammable Flash Program MemoryThe ATmega8A contains 8K bytes On-chip In-System Reprogrammable Flash memory for programstorage. Since all AVR instructions are 16- or 32-bits wide, the Flash is organized as 4K x 16 bits. Forsoftware security, the Flash Program memory space is divided into two sections, Boot Program sectionand Application Program section.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega8A ProgramCounter (PC) is 12 bits wide, thus addressing the 4K Program memory locations. The operation of BootProgram section and associated Boot Lock Bits for software protection are described in detail in BootLoader Support – Read-While-Write Self-Programming. Memory Programming contains a detaileddescription on Flash Programming in SPI- or Parallel Programming mode.

Constant tables can be allocated within the entire Program memory address space (see the LPM – LoadProgram memory instruction description).

Timing diagrams for instruction fetch and execution are presented in Instruction Execution Timing.

AVR 8-Bit MicrocontrollerAVR Memories


Figure 12-1. Program Memory Map

$000

$FFF

Application Flash Section

Boot Flash Section

Related LinksBTLDR - Boot Loader Support – Read-While-Write Self-ProgrammingMEMPROG- Memory ProgrammingInstruction Execution Timing

12.3 SRAM Data MemoryThe figure below shows how the Atmel AVR ATmega8A SRAM Memory is organized.

The lower 1120 Data memory locations address the Register File, the I/O Memory, and the internal dataSRAM. The first 96 locations address the Register File and I/O Memory, and the next 1024 locationsaddress the internal data SRAM.

The five different addressing modes for the Data memory cover: Direct, Indirect with Displacement,Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address given by theY- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-increment, theaddress registers X, Y and Z are decremented or incremented.



The 32 general purpose working registers, 64 I/O Registers, and the 1024 bytes of internal data SRAM inthe ATmega8A are all accessible through all these addressing modes. The Register File is described inGeneral Purpose Register File.

Figure 12-2. Data Memory MapRegister File

R0R1R2

R29R30R31

I/O Registers$00$01$02

...

$3D$3E$3F

...

$0000$0001$0002

$001D$001E$001F

$0020$0021$0022

...

$005D$005E$005F

...

Data Address Space

$0060$0061

$045E$045F

...

Internal SRAM

Related LinksGeneral Purpose Register File

12.3.1 Data Memory Access TimesThis section describes the general access timing concepts for internal memory access. The internal dataSRAM access is performed in two clkCPU cycles as described in the figure below.



Figure 12-3. On-chip Data SRAM Access Cycles

clk

WR

RD

Data

Data

Address Address Valid

T1 T2 T3

Compute Address

Rea

dW

rite

CPU

Memory Vccess Instruction Next Instruction

12.4 EEPROM Data MemoryThe Atmel AVR ATmega8A contains 512 bytes of data EEPROM memory. It is organized as a separatedata space, in which single bytes can be read and written. The EEPROM has an endurance of at least100,000 write/erase cycles. The access between the EEPROM and the CPU is described bellow,specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM ControlRegister.

Memory Programming contains a detailed description on EEPROM Programming in SPI- or ParallelProgramming mode.

Related LinksMEMPROG- Memory Programming

12.4.1 EEPROM Read/Write AccessThe EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in the table "EEPROM Programming Time". A self-timingfunction, however, lets the user software detect when the next byte can be written. If the user codecontains instructions that write the EEPROM, some precautions must be taken. In heavily filtered powersupplies, VCC is likely to rise or fall slowly on Power-up/down. This causes the device for some period oftime to run at a voltage lower than specified as minimum for the clock frequency used. See PreventingEEPROM Corruption for details on how to avoid problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer tothe description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction isexecuted. When the EEPROM is written, the CPU is halted for two clock cycles before the next instructionis executed.

12.4.2 EEPROM Write during Power-down Sleep ModeWhen entering Power-down sleep mode while an EEPROM write operation is active, the EEPROM writeoperation will continue, and will complete before the Write Access time has passed. However, when thewrite operation is completed, the Oscillator continues running, and as a consequence, the device does



not enter Power-down entirely. It is therefore recommended to verify that the EEPROM write operation iscompleted before entering Power-down.

12.4.3 Preventing EEPROM CorruptionDuring periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low forthe CPU and the EEPROM to operate properly. These issues are the same as for board level systemsusing EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regularwrite sequence to the EEPROM requires a minimum voltage to operate correctly. Second, the CPU itselfcan execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be doneby enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does notmatch the needed detection level, an external low VCC Reset Protection circuit can be used. If a resetoccurs while a write operation is in progress, the write operation will be completed provided that thepower supply voltage is sufficient.

12.5 I/O MemoryThe I/O space definition of the ATmega8A is shown in Register Summary.

All ATmega8A I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the INand OUT instructions, transferring data between the 32 general purpose working registers and the I/Ospace. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI andCBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBICinstructions. Refer to the instruction set section for more details. When using the I/O specific commandsIN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data spaceusing LD and ST instructions, 0x20 must be added to these addresses.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/Omemory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBIinstructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thusclearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

The I/O and Peripherals Control Registers are explained in later sections.

Related LinksRegister Summary

12.6 Register Description



12.6.1 EEARL – The EEPROM Address Register Low

Name: EEARLOffset: 0x1E [ID-000004d0]Reset: 0xXXProperty: When addressing I/O Registers as data space the offset address is 0x3E


Bit 7 6 5 4 3 2 1 0 EEARn[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W Reset x x x x x x x x

Bits 7:0 – EEARn[7:0] EEPROM Address [n = 7:0]The EEPROM Address Registers – EEARH and EEARL – specify the EEPROM address in the 512 bytesEEPROM space. The EEPROM data bytes are addressed linearly between 0 and 511. The initial value ofEEAR is undefined. A proper value must be written before the EEPROM may be accessed.

.



12.6.2 EEARH – The EEPROM Address Register High

Name: EEARHOffset: 0x1F [ID-000004d0]Reset: 0x0XProperty: When addressing I/O Registers as data space the offset address is 0x3F


Bit 7 6 5 4 3 2 1 0 EEAR8

Access R/W Reset x

Bit 0 – EEAR8 EEPROM Address 8Refer to EEARL.



12.6.3 EEDR – The EEPROM Data Register

Name: EEDROffset: 0x1D [ID-000004d0]Reset: 0x00Property: When addressing I/O Registers as data space the offset address is 0x3D


Bit 7 6 5 4 3 2 1 0 EEDRn[7:0]

Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0

Bits 7:0 – EEDRn[7:0] EEPROM Data [n = 7:0]For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM inthe address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the dataread out from the EEPROM at the address given by EEAR.

• EEDR[7] is MSB• EEDR[0] is LSB



12.6.4 EECR – The EEPROM Control Register

Name: EECROffset: 0x1C [ID-00000594]Reset: 0x00Property: When addressing I/O Registers as data space the offset address is 0x3C


Bit 7 6 5 4 3 2 1 0 EERIE EEMWE EEWE EERE

Access R/W R/W R/W R/W Reset 0 0 x 0

Bit 3 – EERIE EEPROM Ready Interrupt EnableWriting EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE tozero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE iscleared.

Bit 2 – EEMWE EEPROM Master Write EnableThe EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. WhenEEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at the selectedaddress. If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been written to one bysoftware, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit foran EEPROM write procedure.

Bit 1 – EEWE EEPROM Write EnableThe EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and dataare correctly set up, the EEWE bit must be written to one to write the value into the EEPROM. TheEEMWE bit must be written to one before a logical one is written to EEWE, otherwise no EEPROM writetakes place. The following procedure should be followed when writing the EEPROM (the order of steps 3and 4 is not essential):

1. Wait until EEWE becomes zero.2. Wait until SPMEN in SPMCR becomes zero.3. Write new EEPROM address to EEAR (optional).4. Write new EEPROM data to EEDR (optional).5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The software mustcheck that the Flash programming is completed before initiating a new EEPROM write. Step 2 is onlyrelevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash isnever being updated by the CPU, step 2 can be omitted. See Boot Loader Support – Read-While-WriteSelf-Programming for details about boot programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM MasterWrite Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM



access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. Itis recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems.

When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software canpoll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is haltedfor two cycles before the next instruction is executed.

Bit 0 – EERE EEPROM Read EnableThe EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct addressis set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read.The EEPROM read access takes one instruction, and the requested data is available immediately. Whenthe EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.

The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, itis neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Oscillator is used to time the EEPROM accesses. The following table lists the typicalprogramming time for EEPROM access from the CPU.

Table 12-1. EEPROM Programming Time

Symbol Number of Calibrated RC Oscillator Cycles(1) Typ Programming Time

EEPROM Write (from CPU) 8448 8.5ms

Note: 1. Uses 1MHz clock, independent of CKSEL Fuse settings.

The following code examples show one assembly and one C function for writing to the EEPROM. Theexamples assume that interrupts are controlled (for example by disabling interrupts globally) so that nointerrupts will occur during execution of these functions. The examples also assume that no Flash bootloader is present in the software. If such code is present, the EEPROM write function must also wait forany ongoing SPM command to finish.

Assembly Code Example

EEPROM_write: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to data register out EEDR,r16 ; Write logical one to EEMWE sbi EECR,EEMWE ; Start eeprom write by setting EEWE sbi EECR,EEWE ret

C Code Example

void EEPROM_write(unsigned int uiAddress, unsigned char ucData){ /* Wait for completion of previous write */ while(EECR & (1

EECR |= (1

13. System Clock and Clock Options

13.1 Clock Systems and their Di

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