Audio signal processing using modified FIR filters with Common sub- expression sharing (CSS) technique

Kandukuri Sailusha1, Ch. Venugopal Reddy2

1M. Tech Student, Dept. of ECE, Rise Krishna Sai Prakasam group of Institutions, Andhra Pradesh, India.

2Professor and HOD, Dept. of ECE, Rise Krishna Sai Prakasam group of Institutions, Andhra Pradesh, India. Email: sailusha418@gmail.com, venugopalreddy.sai@gmail.com

Abstract: Audio signal processing is an essential step in the recording and recovery of audio signals. Digital Filters are extensively used as important elements in Digital Signal Processing (DSP) of audio information. Major factors influencing the design of an efficient digital filter are computational requirements, memory and finite word length.. In order to meet these requirements, the order of the digital filter must be kept as small as possible by selecting appropriate filter design method. The filter design is configured using FDA tool for all designs of low pass to band stop filters. A minimum order Finite Impulse Response (FIR) digital filter is designed for filtering noise from audio signal. It is synthesized using Xilinx ISE14.5.

Keywords: FIR digital filter. DSP, CSD, FDA tool.

Introduction:

Digital Signal Processing finds applications in many fields of electronics engineering. In the present day, the processing of the audio signal has to be very fast with less power consumption. We need to remove noise from the audio signals in audio signal processing. Therefore Digital Filter is to be designed for removing noise efficiently. Designing Digital Filter is the process of calculating appropriate filter coefficients and to select the order of the Digital Filter. The designed filter can be implemented on Field Programmable Gate Array (FPGA). Digital Filter coefficients can be represented by fixed and floating point formats. In general it can be assumed that fixed point implementations have higher speeds and lower cost. Floating point implementations have higher dynamic range and no need of scaling which may be attractive for more complicated algorithms [1][2][3]. There are various digital filter architectural optimization approaches like pipelining, parallel processing, Distributed Arithmetic, folding etc. used to generate efficient digital filter architecture. In this paper, a Finite Impulse Response (FIR) filter is designed. Filter Design and Analysis (FDA) Tool available in MATLAB is used in this paper.

Digital filter:

The transfer function of a N-point FIR filter is given by

FIR filter is generally implemented in a non-recursive way. FIR filter design essentially consists of two parts i.e., realization and approximation.

Unit sample response hd(n) is determined using the following relation

Audio signal processing using modified FIR filters with Common sub expression sharing (CSS) technique

Truncation of hd(n) to length M-1 is same as multiplying hd(n) by the rectangular window defined as

Thus the unit sample response of the FIR filter becomes

Frequency response of the truncated FIR filter is given by the convolution of Hd(w) with W(w)

And the frequency response is given by

The algorithm presented in this paper can be used to determine the number of bits needed for each coefficient to implement FIR filter with variable precision coefficient. Furthermore CSD representation leads to compensation for the non-uniform distribution of the CSD coefficient set [4].Digital Filter coefficients can be represented using signed2’s complement number system. CSD format can be used for filter representing filter coefficient. It reduces number of 1’s in the filter coefficient thereby reducing complexity in the computation also. The main part of DA based computation is the Look Up Table (LUT), that stores the pre-computed values and can be read out easily. DA based computation is well suited for FPGA realization. Designs of pipe lined architectures are derived for high speed implementation of FIR filter. Filters implemented with Q8.7 representation results in nearly 53% lesser slice LUTs when compared to Q16.14 representation [5].The work in [6] presents the design and implementation of serial and parallel distributed Algorithm for FIR filter. The results of the implementation are analyzed in terms of area and speed. For high order filters, speed of parallel DA architecture becomes 3 times faster than that of conventional FIR filter.

FIR Filter design fundamentals:

FIR filters are used because of their stability. In general, an FIR filter is described by the convolution sum given by

......1 Where bk represent FIR filter coefficient. The realization of equation (1) for M-tap FIR filter is as shown in the fig 1.It uses multiplier, adder and delay blocks. The simplest technique used to design FIR filter is window technique. The use of windows often involves choosing right window. Some windows such as rectangular, yield fast roll off in the frequency domain but have limited attention in stop band along with poor group delay characteristics. Other windows like Blackman have better stop band attenuation and group delay but a wide transition band. The designed frequency response of any Digital Filter is periodic in frequency and can be represented by equation

Kandukuri Sailusha, Ch. Venugopal Reddy

Fig-1: Realization of M-taped FIR filter

Proposed Method:

In proposed technique the filter is configured for FPGA devices and for the filter configuration can be altered for low pass to band pass and from low pass to band stop by altering the FDA in the system generator.

Canonic Signed Digit (CSD) is the process of encoding a binary number such that it contains the fewest number of non-zero bits. Mapping a number to a ternary system {-1, 0, 1} versus a binary system {0, 1} is performed. No two consecutive bits in a CSD number are nonzero. The CSD representation of a number contains the minimum possible number of non-zero bits. Among the n-bit CSD numbers in the range [-1, 1], the average number of non-zero bits is N/3 + 1/9 + O (2-N). Hence, on average, CSD numbers contains about 33% lesser non-zero bits than 2’s complement number

representation. The conversion of W-bit number in SW.(W-1) notation to CSD format is given by, A = a’W-1. a’W-2… a’1 a’0 = 2’s complement number and its CSD representation is aW-1.aW-2… a1 a0.The number of

computations and complexity can be reduced by searching the common sub-expression in coefficient terms before filter implementation and sharing them. This eliminates extra computational complexity. This process is called Common Sub- expression Sharing (CSE).

Simulation Results:

The FCSD architecture are shown in fig 2. Distributed Arithmetic and FCSD architectures are synthesized using Xilinx ISE 9.1 for target device.

Fig-2: Showing MAC based FIR filter

Audio signal processing using modified FIR filters with Common sub expression sharing (CSS) technique

The filter is configured with low pass signal filter where the signal having the frequencies above the reference frequency are attenuated. These are depicted in figs 3 and 4.

Fig-3: Normal Filter characteristics with

reference signal

Fig-4: proposed filter characteristics

Conclusion: Minimum order equi-ripple FIR filter is designed and this modified method results in the filter comparable to other conventional optimal and windowing design methods. FCSD architecture reduces the power consumption. This greatly reduces the computation complexity. The filter can be configured for required characteristics for low pass filter to band stop filter designs, and can therefore be used for wide range of communications needs.

Kandukuri Sailusha, Ch. Venugopal Reddy

References [1] U. Meyer Baese, “Digital signal processing with FPGA”, Springer Publications. [2] Shanthala S & S. Y. Kulkarni “ High speed and low power FPGA implementation of FIR filter for DSP

applications” European Journal of Scientific Research ISSN 1450-216X Vol.31 No.1 (2009), pp.19-28. [3] Floating-Point Number Specification IEEE 754 (1985), "IEEE Standard for Binary Floating-Point

Arithmetic [4] X. Hu, L. S. DeBrunner, and V. DeBrunner, 2002, “An efficient design for FIR filters withVariable precision”, Proc. 2002 IEEE Int. Symp. onCircuits and Systems, pp.365-368, vol.4,May 2002. [5] V. Sudhakar, N. S. Murthy, L. Anjaneyulu, “Area Efficient Pipelined Architecture for Realization of FIR

filter using Distributed Arithmetic”, IPCSIT Press Vol. 31, Singapore. [6] Mahesh babu Ketha, Ch. Venkateshwarlu Kantipudi Raghuram, “Design & FPGA Implementation of

Reconfigurable FIR filter Architecture for DSP Applications”, IJERT ISSN: 2278-0181, Vol.1Issue 7 Sept 2012.

About the Authors:

K. Sailushais currently pursuing M. Tech in ES & VLSI from Rise Krishna Sai Prakasam Group of Institutions, Ongole. She received B. Tech Degree in ECE from Sri SatyaNarayana Engineering College which is affiliated to JNTUK, Kakinada.

Ch. Venugopal Reddy is working as Professor & HOD in the department of ECE, Rise Krishna Sai Prakasam Group of institutions, Ongole, affiliated to JNTU Kakinada, A.P. Has more than 16 years of teaching experience. He got his B. Tech (ECE) from K.S.R.M. Engineering College, Kadapa, A. P., affiliated to S.V University, Tirupathi, and A.P. M. E. (Commn. Sys) from Dr. M.G.R Engg College, Chennai, T.N affiliated to Anna University, Chennai. He is presently pursuing Ph.D. in the area of Digital Image Water Marking and submitted his thesis, Acharya Nagarjuna University, Guntur. He has a good No. of research publications in his credit. His research interests are in the areas of Image Processing, Signal Processing and Communications.