automated electronic design 1.introduction 2.area of problems 3.approaches and solutions 4.other...
DESCRIPTION
Introduction - Digital vs. Analog DIGITALANALOG Circuit scaleLARGESMALL Design methodologyVHDLSCHEMATIC DesignSYSTEMATICINTUITIVE Synthesis systemCURRENTLY USEDNOT YET Behavior of the transistors SIMPLECOMPLEX SalaryHIGHHIGHER???TRANSCRIPT
Automated electronic design
1. Introduction2. Area of problems3. Approaches and solutions4. Other related Ideas 5. Conclusions
By Alexander Mitev
Introduction
• - Why to automate ?• - Time cycles, cost, quality • - Computer design vs. hand made
Introduction
• - Digital vs. Analog
DIGITAL ANALOG
Circuit scale LARGE SMALL
Design methodology VHDL SCHEMATIC
Design SYSTEMATIC INTUITIVE
Synthesis system CURRENTLY USED NOT YET
Behavior of the transistors
SIMPLE COMPLEX
Salary HIGH HIGHER???
Introduction• The art of analog circuit design
Area of problems
• Complex behavior of analog circuits• No common rule how to synthesize• The imperfection of computer modeling • The rising complexity of formal solutions• The highest degree of freedom of analog
circuits• Mostly the solutions in analog design is
approved after simulation or real test.
Available solutions – Genetic programming
-Achieves this goal of automatic programming by genetically breeding a population of computer programs using the principles of Darwinian natural selection and biologically inspired operations.
-Genetic operations include reproduction, crossover (sexual recombination), mutation, and architecture-altering operations patterned after gene duplication and gene deletion in nature.
-The main generational loop of a run of genetic programming consists of the fitness evaluation, Darwinian selection, and the genetic operations.
Available solutions – Genetic programming
-Genome – a collection of genes , representing parameters of the problem to be optimized- Example of genome:
01 1 001 001001Inpu t R esistor R o Transisto r
W id th O utput Im pedance
Available solutions – Genetic programming, example 1
• Goal – Best solution for the transistor widths and resistor value for R1• Genome – 76 bit , approximately 7.5x1025 possible designs
Available solutions – Genetic programming, example 1
• Results:• Result in 163’th generation • Total work time: Pentium 200 - 15 min
Available solutions – Genetic programming, example 2
• Goal – Filter Synthesis• Limitation: bandwidth, minimal component• Fitness calculation:
100..
( ( ), )
( ) ( ) ( )1, ( )10, ( )
i ii F
i GOAL i OUT i
i
i
Fitness W d f f
d f V f V fd f W
Wd f W
Available solutions – Genetic programming, example 2
0V2
1uC4
1K R5
1K
R61mL4
1K R7
1K
R14
1uC5
VOUT
1uC7
1uC8
1K
R8
1mL6
1K R9
1K
R10
1K R11
1mL7
1mL8
1uC9
1uC10
1uC11
1K
R12
1K R13
Best individual at generation 40
Available solutions – Genetic programming, example 2
50 100 150
Fitness
0.0001
50
5 elem ents
34 elem ents
G eneration100 150
Elem ents
- Solution after the 100’th generation - Minimal elements and exact pass bandwidth.- Total CPU time - 7h 43min.
Available solutions – Genetic programming, example 2
0VIN
1uC2
1K R2
1K
R3
1mL2
1K R4
1mL3
1uC3
VOUT
Available solutions – Genetic programming, example 3
- Goal Low pass filter using parallel GA- Genome 400 bytes ; 18000 individuals max- Best result 23’th generation- Total working time 6 SUN workstation 4 hours
Available solutions – Genetic programming: Summary
-Benefits:-Novel approach by simulating natural selection-Mostly with GA could be solved problems faster than by hand.
Shortcoming (regarding this research)-Time dependable -Domain dependable, presently available for filters and amplifiers-No guarantee to solve the problem
Available solutions – Automated design by reusing
• CBR: the basic idea is to solve a new problems by comparing them with old ones that have been solved in the past
• Major method – testing for similarity.• Base with “past experience”, Intelligent retrieval • Intelligent retain – if a new solution is available• Generalizing this idea by considering the common sense
of Intellectual product (IP)
The reuse - cycle
- Retrieval – an IP is selected corresponding to the respective specifications
The reuse - cycle
- Retrieval – an IP is selected corresponding to the respective specifications
- Instantiation: If an IP has been selected the necessary design is instantiated, OR
The reuse - cycle
- Retrieval – an IP is selected corresponding to the respective specifications
- Instantiation: If an IP has been selected the necessary design is instantiated, OR
- The design flow is defined to meet the constraints
The reuse - cycle
- Retrieval – an IP is selected corresponding to the respective specifications
- Instantiation: If an IP has been selected the necessary design is instantiated, OR
- The design flow is defined to meet the constraints
- Retain – if it has been decided to store the synthesized circuit
Solution – Reuse
Design by reuse• Algebraic description of Libraries• Basic requirement : LB, LF library
Kb – behavior to be synthesizedVb – behavior parametersDb- allowed parameters
Kf – design flow to be synthesizedVf – des. flow parametersDf- allowed des. flow parameters
Design by reuse
LB library – parameterized design
LB – store certain design, which can be instantiated
Kb – parameterized specification of the synthesized behavior
Vb – specification parameters
Db – allowed parameters
Design by reuse
• Specifications b and b’ are:• - identical • - equal (same behavior)• - extension b<b’
• Example 32 bit adder and 16 bit adder
Design by reuse
• LF library – design flow for synthesis
LF – store certain design flow
Kf – parameterized design flow
Vf – specification parameters
Db – allowed parameters values
Design by reuse
• Algebraic description of Libraries• Reuse library LIB
( , );;
Ki Kb KfVi Vb VfDi
Ki – parameters for behavior and des. flowVi – both parameters from Vb and Bf Di- allowed parameters values
Design by reuse
• Reuse component IP I = (Ki, Vi, Di)• Instance if |Di|=1• Configurable if |Di|>1
Ki – parameters for behavior and des. flowVi – specification parameters from Vb and Bf Di- allowed parameters values
Design by reuse
Design by reuse
Design by reuse
• Similarity of IP’s
'
'
'( )
: ( ) ( ) [0.1]
( , ') ( ( ), ( )) (0,1]I I
V I I
v V I Iv V V
sim d v d v
SIM I I r sim d v d v
For each parameter in Vi is calculated similarity of the allowed parametersRv – relevance factor, stating the importance ov V for the hole design
Design by reuse• Constraint management
R ds m axId m ax
P d m ax
R ds m ax
Id m ax
Pd m ax
( , )drain d dP f I R
Design by reuse• Constraint management
R ds m axId m ax
Pd m ax
R ds m ax
Id m ax
Pd m ax
Id m in
Rds
( , )drain d dP f I R
Design by reuse - example
• READEE project – CBR technology of design and IP reuse
• Realization as a WEB based service. • Problem domain – selection of DSP processors• Similarity measure – application and DSP-specific
information ( Example : consuming power )• Performance or qualifying is based on abstract table
model including many application orientated properties
Design by reuse - example• DSP operations table:• 1. Operations , such as arithmetic, logic etc.• 2. Performance profile : filter (parameters) ; FFT
(parameters, #simples) ; general purpose options
• Task of evaluation model supporting similarity calculations:
• 1. Clock frequency is derived as a function of consuming power
• 2. User specified performance profile is mapped to the main data code.
Design by reuse - example
DSP function taxonomy
Design by reuse - summaryBenefits:- Knowledge based approach - No iterations, quick solution (if there is a solution)- With retain mechanism – theoretically provide
solutions for all possible problems
Drawbacks:1. Design for reuse2. Numerous parameters, one another dependable3. In many cases scalable design is impossible
Design by reuse • Define domain of problem set (ex. Noise, gain etc.)• Determine all domain of parameters ( ex. frequency,
resistance, etc). V – V [p1, p1, ….pn]
• Level-1: L1 base - Separate the Analog circuit in simple modules with known parameters (ex. Transistor, capacitor etc).
L1- L1[Ti, Vi]• Leve-2 : L2 base – Topological low level description (CE
transistor, Differ. Pair.)L2 – L2(L1k, Vk)
Design by reuse• Hence we have description of all analog
building blocks• The instantiate base describes all available
design circuits • Now we can reuse different block according
problem specification
( ) [ 2( ), ( )]I t F L k V r
Design by reuse
Q1beta= 100
Q2beta= 100
Q3beta= 100
Q4beta= 100
Q5beta= 100
Q6beta= 100
IEE
300ua
VLO
0
RC
15K R
C2
5K
L1100uh
C1100pf
VC
C10
VR
F0
VB
IAS
-2
C
BB
AA
1
4
3
2
Simplifying of circuit by substitution with building blocks
Ideas for automated electronic design
• By decomposition the circuit into submodules or building blocks we can get these advantages:
• 1. instantiate each block, not the hole circuit• 2. if we symbolic describe behavior of each block we
can make some prediction of the total behavior of the circuit. More important is the reverse operation – to make a relation from behavior to building modules.
Ideas for automated electronic design
• 3. If we can make a complete set of building blocks. It will be one step ahead to use one special case of reuse – software reuse similar to HDL based languages. Presently is available analog extension of VHDL but only for elementary elements ( transistors, diodes)
• Problems : – Rising complexity of symbolic representation with the
size of circuit– Every circuit maintain one symbolic representation,
but not vice versa.
Conclusion, feature work
1. The key of the analog design is in distinguishing of the topologies.
2. Common ontology for analog design. (not seen yet in the topic of automated analog design). Example: Hi-Fi audio amplifier includes: filters, amplifying modules, comparators etc).
3. Each element of this ontology has to be provided with detailed parametric specifications: - all allowed parameters ; - all scalable parameters.
4. We can reuse the elements not the hole circuit
Conclusion, feature work3. Scenario for design flow could be possible to simulate
based on the symbolic description (expression) of the problem by evaluating and/or reusing.
4. Mechanism for decomposition major problem to minor subproblems.