BAG2: A Process-Portable Framework forGenerator-Based AMS Circuit DesignEric Chang∗, Jaeduk Han∗, Woorham Bae∗, Zhongkai Wang∗, Nathan Narevsky∗,

Guanghua Shu†, Frankie Liu†, Borivoje Nikolic∗, Elad Alon∗

∗University of California, Berkeley,†Oracle Labs

Abstract—We present BAG2, a framework for the developmentof process-portable Analog and Mixed Signal (AMS) circuitgenerators. Such generators are parametrized design proceduresthat produce schematics, layouts, and verification testbenchesfor a circuit given top level specifications. This paper expandson previous work by introducing a new universal AMS cir-cuit verification framework using BAG2, and also two newlayout engines, XBase and Laygo, that enable development ofprocess portable layout generators. We have developed variouscomplex circuit generators as driving examples, including atime-interleaved SAR ADC and a SerDes transceiver frontend,designed in TSMC 16nm FFC process. We also verify our claimsof process portability by presenting circuits generated in varioustechnology nodes, including TSMC 28nm, TSMC 16nm, TSMC7nm, Global Foundries 45nm RF-SOI, ST 28nm FD-SOI, andST 22nm FDX..

I. INTRODUCTION

As Moore’s law scaling comes to a stop, circuit designerscan no longer rely on new process technologies to improve theperformance of their circuits; innovation in system architectureand circuit topology is necessary to design next generationsystems. However, stringent and unintuitive design rules ofadvance multi-patterning processes [1], along with increasedinterconnect resistance and capacitance due to dimensionscaling, severely lengthen time spent in post-layout verificationand limit designers’ ability to explore new architectures andtopologies. Moreover, these factors also impose a significantbarrier to migrating AMS circuits to advance processes, pro-hibiting monolithic system integration and introduce perfor-mance degradation due to package/board parasitics.

Several approaches to shorten analog circuits design cyclehave been explored. In [2], circuit design constraints aretransformed into geometric programming problem, and anoptimization solver is used to compute individual deviceparameters from performance specifications. In [3], numericaloptimization is used to refine device parameters with schematicsimulation results to account for discrepancy between actualcircuit model and approximated design equations. In [4], thecircuit optimization process are further refined by incorpo-rating layout parasitics estimated from an automated place-and-route tool for analog circuits. These techniques all focuson computing the circuit parameters and did not address theproblem of DRC clean layout creation. As the result, manuallabor are still required to create the final layout and verify that

it meets performance specification, which often becomes thebottleneck of analog design flow.

To address these problems, John Crossley et al. introducedthe Berkeley Analog Generator (BAG) framework and advo-cated for a generator-centric design approach [5]. Instead ofdesigning one circuit instance, the designer develops a circuitgenerator, which consists of parametrized procedures that pro-duce schematic, layout, and verification testbenches from per-formance specifications. With these generators, designers caneasily incorporate fully automated design iteration loops onaccurate post-layout simulation data in their design procedure,which can produce better circuits in less time. Furthermore,circuit generators can easily generate many circuit instancesfor similar applications with different specifications, whichpromotes design reuse and simplifies complex system design.

Two shortcomings limits the reuse-ability of generators writ-ten in BAG. First, testbench generated by BAG expects a fixedpin interface to its device-under-test. This prevents testbenchgenerators from being shared between similar circuits andleads to duplicated code, which is difficult to maintain anddebug. Second, layout generators are written using Synopsys’PyCell API [6], which is not available for recent technologynodes, thus preventing application of BAG in state-of-the-arttechnologies.

In this paper, we present BAG2, an updated version ofBAG that enables development of process-portable circuitgenerators. We implemented a new universal AMS circuitsverification framework enabled by BAG2’s schematic gener-ation API, and incorporated this methodology into generatordesign flow. We also developed two new layout generationengines, XBase and Laygo, which interfaces with BAG2to provide process independent layout API for designers toprogram layout generators. Using BAG, XBase, and Laygo,we designed a fully automatic time-interleaved SAR ADC andSerDes transceiver frontend generator, verified and taped outin TSMC 16nm. Furthermore, we demonstrate layout processportability by generating various circuit blocks in TSMC28nm, TSMC 16nm, TSMC 7nm, Global Foundries 45nm RFSOI, ST 28nm FD-SOI, and ST 22nm FDX processes with nomodifications necessary.

The rest of the paper is organized as follows. Section IIreviews the generator design flow, using differential amplifieras a driving example. Section III describes the universal

(a) Schematic generator (b) Schematic template

(c) Layout Generator (XBase)(d) Generated Layout

(e) Design script

(f) Simulated result

Fig. 1: Generator design flow example

AMS circuit verification framework. Section IV presents anoverview of key principles that enables process-portable layoutgeneration. Section IV-A presents the XBase layout engine,which provides various classes and functions for writingpassives and analog circuits generators. Section IV-B describesthe Laygo layout engine, an alternative to XBase that operateson hand-designed layout primitives for creating compact, high-speed custom circuits. Section V describes generators devel-oped with these layout engines and summarizes our processportability results. Finally, we conclude and discuss futurework in Section VI.

II. GENERATOR DESIGN FLOW

In this section, we walk through the design process of adifferential amplifier generator to provide an overview of theBAG2 framework. First, like in traditional circuit design, thedesigner create a normal schematic of the circuit, as shownin Figure 1b. This schematic serves as a template for theschematic generator, and BAG2 will create new circuit in-stances by copying and modifying this template. Compared toa purely netlist-based approach, this allows BAG2 to generatehuman readable schematic that integrates well into traditionalmanual design flow. After the schematic template is created,the designer decides on the inputs of the corresponding

(a) Verification framework UML diagram

(b) Measurement configuration

(c) DUT wrapper (d) AC analysis testbench.

Fig. 2: Verification framework example

schematic generator. These parameters are usually low levelstructural parameters (such as transistor dimensions) insteadof high level specifications, as this allows for the reuse ofthe same schematic generator for different design specifi-cations. With inputs of the schematic generator determined,the designer implements the schematic generation routinein a Python class (Figure 1a), which calls various BAG2functions to transform the schematic template into specificcircuit instance. In addition to modifying device dimensions,BAG2 provides API for adding or modifying pins, instances,and instance connections. This allows the designer to freelymodify the underlying circuit structure, such as adding cascodetransistors, creating variable array structure, and so on.

After schematic generator is implemented, the designerdevelop the corresponding layout generator using either XBaseor Laygo (Figure 1c), described in Section IV-A and Sec-tion IV-B, respectively. The inputs to the layout generator aregenerally a super-set of the inputs to the schematic generator,as layout parameters such as aspect ratio and signal wirewidth/spacing are not necessary for schematic generation.After layout generator is finished, designer can use BAG2 togenerate schematic and layout instances with various parame-ter combinations and verify that the generators produce DRC

and LVS clean layouts (Figure 1d).Next, the designer codifies the design procedure into a

design script (Figure 1e), which takes top level specificationsand computes parameters for the schematic and layout gener-ator. Usually, the design procedure uses design equations withpre-characterized technology database to compute an initialstarting point (such as the gm/ID sizing methodology [7]),then iterates on post-extraction simulation results to accountfor unmodeled layout parasitics and converge to the finalsolution.

To run simulations and get circuit performance from simula-tion data, designer simply specify the measurement parametersin a configuration file (Figure 2b), and pass this configurationfile to the universal verification framework. The verificationframework will then setup testbenches, simulate given circuitinstances, and report circuit performance (Figure 1f). Theimplementation of the verification framework is described inSection III.

Using this design flow, as long as the designer avoids hard-coding parameters in the design script and various generators,the design process of any circuit block can be easily repeatedto achieve optimal performance with different specifications orin another technology node. In Section V-A we present post-

Fig. 3: XBase top level UML diagram.

extraction results of differential amplifiers generated using thisflow in various technologies.

III. UNIVERSAL VERIFICATION FRAMEWORK

In traditional analog circuit design, verification testbenchand simulation data processing are often tightly coupled tothe specific circuit and technology node, which limits test-bench reuse-ability and prevents development of a verificationstandard for analog circuits. Previous work has address thisproblem by defining clear interfaces between circuits and teststhat operate on them, then building a hierarchical repository ofreuseable test components that enables the design of circuit-independent tests [8]. We incorporated the same principledeveloped a universal verification framework using BAG2’sschematic generation API. Figure 2a outlines the interfacesbetween design script, verification framework, and variousgenerators.

We walk through the verification flow by continuing the dif-ferential amplifier example in Section II. First, before invokingthe verification framework, the design script generates device-under-test (DUT) wrapper schematics (Figure 2c) for eachtestbench it is going to instantiate. The DUT wrapper servestwo main purposes. First, it transforms the DUT input/outputpin interface to a standard interface defined by the testbench.In Figure 2c, it instantiates two ideal baluns to performdifferential-to-single-ended conversions, and adds various biasvoltage sources. Second, it provides proper loading to theDUT, which can be capacitors, resistors, or even other circuitinstances.

After DUT wrappers are generated, the verification frame-work instantiates one measurement manager for each mea-surement specified in the configuration file (Figure 2b). Eachmeasurement manager instantiates and simulates one or moretestbenches, and post-process simulation data to determine cir-cuit performance. In this example, the measurement managersimply instantiates an AC analysis testbench then computeamplifier gain and bandwidth from the Bode plot. After all

measurements are finished, the results are reported back tothe design script.

With this new approach, an universal verification standardcan be defined for all analog circuits. Complex verificationprocedures simply need to be programmed once by experi-enced designers and can be applied to all circuits.

In the next few sections, we focus on our new layout gen-eration API, which enables the development of truly processportable circuit generators.

IV. PROCESS PORTABLE LAYOUT

There are two key insights behind our solution for process-portable layout generators. First, despite vast differences inthe device geometry and design rules, The layout floor planfor a circuit with a given application is almost always thesame. Figure 4c shows a typical floor plan for an amplifiercircuit. By using vertical wires to connect between transistorand substrate rows, the number of wires naturally scales withnumber of fingers, thus minimizing interconnect resistance andmaximizing transistor current density limit due to electromi-gration constraints. Therefore, by constructing a layout APIthat allows designers to draw various common floor plansand abstract away geometry details of the underlying devices,generators written in this API would be process portable.

Second, complex and unintuitive multi-patterning designrules have driven circuit designers to enforce regular routinggrids even in custom layouts. Therefore, by enforcing a routinggrid system where both the width and spacing of the wiresare quantized, and wires on the same layer must travel inthe same direction (with adjacent layers having alternatingdirections), we can ensure DRC correctness by simply ad-justing the routing grid parameters. Most importantly, layoutgenerators written to draw all wires on routing grid can beeasily ported across different process nodes. As an addedbenefit, for multi-patterning technology nodes where low-levelmetals must be colored explicitly by the user, the coloringcan be automatically done based on the parity of routing trackindex.

(a) AnalogBase after draw_base() (b) AnalogBase after draw_mos_conn() (c) AnalogBase after connect_wires()

Fig. 4: AnalogBase layout in different stages

In the next two sections, we present two layout engines thatimplement these concepts.

A. XBase Overview

The top level UML diagram for XBase is shown in Figure 3.Python abstract base classes are used to encapsulate commonlayout methods and separate process agnostic generators fromprocess specific primitives.TemplateBase is the fundamental class that all layout

generators are based on. It defines two sets of APIs, onehigh level and one low level, that designers call to createlayout geometries. the low level API contains methods suchas add_rect() and add_via(), which draw any primitivegeometries with no restrictions. These methods do not guar-antee DRC correctness and therefore are mostly used in prim-itive implementations. The high level API contains methodssuch as connect_to_track() and connect_wires(),which create wires on the routing grid described by theRoutingGrid class. Layout generators written solely usingmethods in the high level API will be process portable.Finally, TemplateBase defines an abstract method calleddraw_layout(), which must be implemented by its sub-classes to create layout for the specific circuits.

Each different type of layout floor plan is implemented as anabstract subclass of TemplateBase, which provide methodsfor drawing the specific floor plan. AnalogBase is an ab-stract class specialized in drawing layout floor plan for electro-migration rules constrained analog circuits, as describedin Section IV. AnalogBase provides the draw_base()method, which draws rows of transistors and substrate tapsbased on user supplied parameters, such as number of fingersper row, number of rows, number of horizontal routing tracksper row, and so on. It also defines draw_mos_conn() andconnect_to_substrate(), which connects transistorsand substrate taps to the routing grid. To create an amplifiergenerator with this floor plan (represented by Amplifierclass in Figure 3), designers simply sub-class AnalogBaseand implement the draw_layout() method by callingdraw_base() and other related methods with proper pa-rameters.

To enable process portability, abstract primitive classes areused to separate process specific layouts from AnalogBase.These primitive classes define abstract methods that encap-sulates all design rules relevant to the floor plan it supports.Methods in AnalogBase such as draw_base() call thesefunctions and determine how to correctly assemble the primi-tives together. As the result, by simply changing routing gridparameters and implementations of these abstract primitiveclasses, the designer can generate circuits in another processtechnology using the same layout generator.

In addition to AnalogBase, XBase also provides aResArrayBase for drawing resistor arrays. With these twoclasses, many analog circuit generators can be written.

B. Laygo Overview

Laygo stands for LAYout with Gridded Objects, and asthe name implies, it is developed for generating DRC clean-by-construction layouts by placing layout elements on gridsand utilizing relative and symbolic information, rather thanphysical numbers. The main difference of Laygo from XBaseis that Laygo uses manually designed, process-specific layoutprimitives for encapsulating design rules, while XBase usesabstract base classes.

Figure 6 shows the structure of Laygo framework.GridLayoutGenerator is the main class for layout gen-erations. Users create various layout geometries by call-ing functions defined in GridLayoutGenerator, such asrelplace() (for instance placements), route() (for wireroutings), and via() (for via placements).

The relplace() function places instances (whosegeneric information are stored in the TemplateDB object)based on integer grid coordinates on placement grid and rel-ative information with neighboring structures (ref parameterin Figure 7(a)). The GridDB object stores the placementgrid information (x, y resolution) for the placement operation.Since the relplace() function uses abstract grid or relativeinformation between instances, the process portability is guar-anteed if all primitive templates are designed to be alignedwith the process-specific placement grids. The route()function draws routing patterns on predefined routing grids.

(a) transmitter frontend (b) receiver frontend

Fig. 5: SerDes frontend layout photo

Fig. 6: Laygo structure

Similar to the relplace() function, in order to createwires without dealing with physical coordinates, the route()receives integer coordinates on abstract routing grids or targetobjects to connect the routing wire (Figure 7(b)). All integerrouting coordinates are converted to physical coordinates bycombining the integer values and routing grid information(pitches, widths). The via() function places via objects,using a similar method with the aforementioned functions(Figure 7(c)).

The three place and route functions compose the coregenerator flow, while high-level functions that construct morecomplex geometries (by combining the core functions) areprovided as well. It should be noted that any non-uniform gridsin terms of pitch and routing width can be used for placementand routes (as shown in Figure 7), which yields high quality-of-results (by optimizing the grid values for given technology),while still abstracting design rules.

All layout structures are stored in LayoutDB and exportedto LayoutIO, to create the final layout in OpenAccess orGDS format.

Fig. 7: Laygo generation example (a) relplace (b) route (c) via

V. RESULTS

To demonstrate the effectiveness of BAG2, we designeda SerDes frontend layout generator using XBase (Figure 5)and taped out in TSMC 16nm FFC process. The SerDestransceiver is designed for 20 Gb/s, the receiver datapathemploys the dynamic latch and charge integration topology[9], and contains a passive CTLE, 1 tap FFE, and a 3 tap DFE.All transistor sizes and the number of DFE taps in the SerDesfrontend are programmable. The Serdes frontend occupies anarea of 195µm by 110µm, including AC coupling capacitorsand ESD diodes.

We also developed a time-interleaved SAR ADC generatorusing both XBase and Laygo (Figure 10). The generatorconsists of clock distribution and calibration circuitry, fron-tend samplers, reference DACs and buffers, SAR ADCs,and output retimer. The ADC top level specifications are all

(a) Global Foundaries 45nm RF SOI (b) TSMC 28nm (c) TSMC 16nm

Fig. 8: Generated differential amplifier in various processes

Fig. 9: Bode plot of differential amplifiers

programmable, and an instance targeting 9.6 GS/s with 8-wayinterleaving, 6 bits of ENOB with 9 physical output bits istaped out in TSMC 16nm. The total area of the entire ADCis 500µm by 100µm.

A. Process Portability

To validate our claim of process portability, we ran thedifferential amplifier generator presented in Section II (withlayout generators written in XBase) in Global Foundaries RFSOI 45nm, TSMC 28nm, and TSMC 16nm. The amplifiersare designed to drive a 100 fF capacitive load with a targetDC gain of 2, a target 3-dB bandwidth of 4 GHz, and min-imum power consumption. The generated layouts are shownin Figure 8, and the post-extraction Bode plot is shown inFigure 9. The final designs have DC gains of 2.07, 2.22, and2.17, and 3-db bandwidths of 4.12 GHz, 4.15 GHz, and 4.03GHz, respectively. Despite vast differences in design rules andunderlying transistor device physics, our generator is able toproduce valid circuits that closely meets specifications.

To demonstrate layout portability of more complex blocks,Figure 10 shows the generated ADC core layout in TSMC16nm, ST 28nm FD-SOI, and ST 22nm FDX. The ADC coreconsists of sense amplifiers, capacitor banks, and SAR logics.

The generated layout is DRC and LVS clean without manualmodification.

B. TSMC 7nm layout

To validate our layout generation approach in state-of-the-art processes, we generated a LDO regulator, a MOS/MOMdecoupling capacitor, and a StrongArm latch layout in TSMC7nm, showin in Figure 11. These blocks are used in aninjection-locked ring oscillator PLL and the generated layoutsare DRC and LVS clean with no modifications. These resultsfurther prove that our layout generation framework is capableof handling latest technology nodes.

VI. CONCLUSION

A substantial change in AMS circuit design and verificationflow is necessary to continue innovation beyond Moore’s lawscaling. We described a new universal verification frameworkbuilt with testbench generators, which helps define a verifica-tion standard for AMS circuits. We then presented two newlayout generator framework, XBase and Laygo, that enablesdevelopment of process portable circuit generators even withadvance technology nodes. To prove our claim, we designedvarious complex generators and taped out in TSMC 16nm FFCprocess, including a SerDes frontend and a time-interleavedSAR ADC. We further demonstrate process portability byrunning our generators in a variety of technology nodes.

We have shown that generator based design methodologyis a viable path to AMS circuit design automation. As futurework, we plan to explore development of complete SOC gener-ators by integrating BAG with digital synthesis tools and otherhigh level hardware construction languages, such as Chisel[10]. BAG [11], XBase [12], and Laygo [13] are releasedunder open source licenses, and documentations/tutorials arecurrently under active development.

ACKNOWLEDGMENT

This work was funded in part by DARPA CRAFT con-tract HR0011-16-C-0052 in collaboration with Cadence andNorthop Grumman. The authors acknowledge the students,faculty, and sponsors of the Berkeley Wireless Research Cen-ter, and Oracle Labs for supporting development in TSMC7nm.

(a) TISAR ADC core in TSMC 16nm

(b) TISAR ADC core in ST 28nm FD-SOI (c) TISAR ADC core in ST 22nm FDX

Fig. 10: TISAR ADC layout photos

(a) LDO regulator in TSMC 7nm

(b) MOS/MOM decoupling capacitors in TSMC 7nm (c) StrongArm latch in TSMC 7nm

Fig. 11: Various generated layouts in TSMC 7nm

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