batch no.2
TRANSCRIPT
A FAST CRYPTOGRAPHY PIPELINED HARDWARE DEVELOPED IN FPGA WITH
VHDL
PRESENTED BY
K.KALPANA (093J1A0407)
B.DURGA PRASAD (093J1A0418)
L.SHIVA KRISHNA (093J1A0440)
B.HARI KRISHNA (093J1A0419)
GUIDE: P.VANNUR(M.tech),
KOTTAM KRUNAKARA REDDY INSTITUTE OF TECHNOLOGY
CHINNA TEKURU, KURNOOL-518 218
CONTENTS
• ABSTRACT• INTRODUCTION• ADVANCED ENCRYPTION STANDARD• ENCRYPTION BLOCK DIAGRAM• ARCHITECTURE OF AES• ADVANTAGES• DISADVANTAGES• APPLICATIONS• CONCLUSION• FUTURE SCOPE
Key words
• Cryptography• Pipeline• FPGA• AES
ABSTRACT
Main objective :
• The main objective of the project is to increase the speed of encryption and decryption by using pipelined hardware.
• Pipelined hardware cryptography was used to improve performance in order to achieve higher throughput and greater parallelism.
What is FPGA ????
• FPGA stands for field programmable gate array.
Why FPGA ????
What is pipeline?
Four Pipelined Instructions
IF
IF
IF
IF
ID
ID
ID
ID
EX
EX
EX
EX M
M
M
M
W
W
W
W
5
1
1
1
What is parallelism?????
INTRODUCTION
• Cryptography - secret writing
DES-Data Encryption Standard
AES-Advanced Encryption Standard
Which is better (software or hardware based cryptograph)??????
AES-Advanced Encryption Standard
What is AES????
and
why AES????
Encryption phases
1.Subbytes
2.Shift rows
3.Mix columns
4.Addround key
• For decryption algorithm will use respective inverse operations.
SubBytes – A non-linear substitution step where each byte is
replaced with another according to a lookup table (known as S Box).
ShiftRows –
A transposition step where each row of the state is
shifted cyclically a certain number of steps.
MixColumns – A mixing operation which operates on the columns of
the state, combining the four bytes in each column using a linear transformation.
AddRoundKey – It is an XOR operation between the state and the round key.
Key Expansion - Three operations.
1.RotWord
2.SubWord
3.XOR operations
Block diagram of I/O of encryption
Round key
Add round key
Sub bytes
Shift rows
Add round keys
Sub bytes
Shift rows
Mix columns
Add round keys
BUFFER
selector
Block Diagram Of Encryption
AES architecture and its blocks 1.Key expansion 2.Encryption 3.Decryption
Architecture diagram of AES
• High Performance• Time to market• Reprogrammable• Reconfigurable• Long term maintenance
Disadvantages• More expensive.• Power consumption is more.
FUTURE SCOPE
• Micro electronics intends to use this work as part of larger projects such as smart metering in power systems and cryptography interface in data communication.
Conclusion
ThankQ
Queries….???