bc switched-capacitor filter based type-iii compensation for switched-mode buck converters

8/10/2019 BC Switched-Capacitor Filter Based Type-III Compensation for Switched-mode Buck Converters

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Switched-Capacitor Filter based Type-III

Compensation for switched-mode Buck ConvertersG. Bawa1,2and A. Q. Huang1

1North Carolina State University, NC, USA; 2Texas Instruments Inc., TX, USA.

AbstractIn this paper, we present a novel switched-capacitorfilter based Type-III compensation architecture for closed-loop

regulation of fixed-frequency switched-mode Buck converters.

Compared to the conventional all-analog filter, the proposed

compensator can be fully-integrated onto the die resulting in

reduced footprint and cost. In addition, the filter time constants

scale linearly with the Buck converters switching time-period,

resulting in increased programmability and ease-of-use. A

prototype of a voltage-mode PWM controller with

programmable Buck Converter switching frequencies of 0.5 and

1 MHz, has been implemented and validated in a 0.36-m BCD

process, consumes 1.1 mA of static current from a 3.3 V supply,

and occupies ~ 0.65 mm2of active area on-chip.

I. INTRODUCTION

In contemporary battery or line powered computing

applications, the source voltage is typically higher than the

target loads operating voltage. Inductive switched-mode

step-down (or Buck) converters (Fig. 1) can convert the

power highly efficiently (> 90 %) for high load current

requirements (> 1 A). The closed-loop regulation can be

performed using fixed-frequency voltage-mode pulse-width

modulation (PWM) controllers to ensure a power-supply with

low jitter and controlled EMI, by synchronization with

external clock.

Typical power controller Integrated Circuits (ICs) offer

several degrees of programmability through external

components or a digital communications interface [1].

External components include the compensation components

that take up board area and need to be carefully selected. It is

advantageous to integrate these compensation components to

decrease the size and improve the IC usability. This also

reduces the risk and development time for new power

supplies based around the integrated circuit.

The integration of the passive components of the

conventional Type-III analog filter (Fig. 2) for voltage-mode

PWM control is prohibitive at the switching frequencies (fSW

1 MHz) of interest due to prohibitively large component

values. In addition, the RC time constants vary by ~ 40 %

over process, voltage and temperature (PVT) variations.

In contrast, a Switched-Capacitor Filter (SCF) time

constant is given as [2]:

S

I

SS

IS

SCF

SCF

C

C

fC

CT

f==

=1

2

1

(1)

where,fSis the sampling rate; CSand CIare the sampling and

integrating capacitors, respectively. It can be seen that by

controlling the clock (and hence sampling) frequency

accuracy (< 1 %) and capacitor matching accuracy (< 1 %),

SCFcan be made highly accurate (< 2 %), even without on-chip trimming. In addition, it can be deduced from (1) that

fSCFscales linearly with fS, which can be a scaled-up version

of the Buck converters switching frequency (fSW= 1/OSR

fS). Here, OSR can be understood to be the SCFs Over-

Sampling Ratio.

With these concepts in mind, we proceed to thedevelopment of a fully-integrated Type-III compensation for

a voltage-mode PWM controller. The salient features includefrequency-scalability, improved ease-of-use, reduced board

size and power consumption comparable to the conventional

analog filter implementation [1]. Furthermore, the modular

SCF architecture lends itself to Type-II compensation andpotentially other variants of Type-III compensation [3].

II. TYPE-IIISCFARCHITECTURE

The use of conventional Type-III filter (Fig. 2) isnecessitated by ceramic output capacitors, as the high ESR-zero frequency (f

ESR~f

SW= 1 MHz) provides negligible phase-

lead. Thus, the filter places two real zeroes (fZ1,2 ~ 20 KHz)close to the LC double-pole frequency (f

LC ~ 29 KHz) for

phase-boost and Closed-Loop Bandwidth (fCL

~ 100 - 200KHz) extension. Finally, it places a pole-at-origin for highDC regulation; and two poles (f

P1,2~ 550KHz) beyondf

CLand

below fSW

, for finite gain margin (GM > 10 dB) andThis project was supported by the research funding from Texas

Instruments Inc., USA.

Fig. 2. Conventional Type-III filter circuit for HC(s) in Fig. 1.

( )( )( )( )( ) ( )( )3231132233211

||1111)(

CCsRRsCCCsRCsRRRsCsHC

+++

+++=

Fig. 1. Circuit schematic of closed-loop switched-mode Buck converter

with voltage-mode PWM control [4].

L

CRQ

LCLOADN ,

12

( )

2

2

.1

1)()()(

NN

C

SAW

INvdT

s

Q

s

CsR

V

VsGsMsG

++

+==

CRf

VsM

C

ESR

SAW 21,1)( ==

978-1-4673-6146-0/13/$31.00 2013 IEEE


2/4

attenuation of high-frequency switching harmonics. It mustbe understood that while the foregoing discussion considers

fSW = 1 MHz, all the aforementioned frequencies will scale

linearly with fLC for stability, which in-turn scales linearly

withfSWin order to ensure the same VOUTripple[4].The development of the Type-III SCF architecture begins

by judicious partitioning and sequencing of the conventional

filters transfer function into three 1st

order cascaded sections:an Integrator followed by two High Pass Filters (HPFs) (see

Fig. 3). Now, if we treat the output voltage of the Buck ( VOUT

in Fig. 1) as the input to the SCF, we realize that it has adesirable low-frequency component at a cutoff ~ fLC, andundesirable high-frequency switching harmonics at multiples

of fSW. If the worst-case ripple magnitude is 5 % (SNR = 26

dB), it does not meet the Signal-to-Noise Ratio (SNR > 40 dB)requirements for SCFs robustness. Thus, the SCF sampler

cannot be directly exposed to this signal, and an Anti-Aliasing

Filter (AAF) is required. In this prototype, we have realized

the 1st stage as a GmC integrator, and implemented both the

Type-III and AAF functions simultaneously. More details onthe GmC integrator design will be discussed in section III-A.

As a next step, we need to choose the SCF OSR(and hence

fS) carefully. If the OSR is made too low, the realization of

high-frequency poles is difficult. If OSR is made too high, itwould lead to increased capacitor spread for a target time

constant and unit sampling capacitor (CS) size (see (1)). Inaddition, it would lead to increased loading and faster settling

requirements for the SCFs amplifiers at the same time,

making the design extremely power hungry.

In this prototype, we have employed Bi-Linear

Transformation [5] for realizing the high-frequency poles for

the two SC-HPFs. BLT offers the advantage of mapping theentire analog frequencies (-, ) within the Nyquist frequency

(-fS/2, fS/2). By choosing fS/2= fSW (OSR = 2), we make a

reasonable choice for synthesizing the aforementioned Type-III filter poles fP1,2. In addition, as can be deduced from the

foregoing analysis, we have laid the foundation for highlyarea- and power-efficient SCF realization.

Now, a low OSRmakes the AAF requirements for both the

SC-HPFs challenging, since there is no implicit low-pass

filtering in the filters transfer functions [2]. For SC-HPF#1,

these requirements are met by making the integrator

bandwidth (fI) fSW/10, if the worst-case ripple (5 %) isconsidered (see Fig. 4). However, if SC-HPF#2 is directly

cascaded with the previous stage (SC-HPF#1), severe aliasing

distortion is observed. The only remedy is to introduce a

Sample-and-Hold Amplifier (SHA) operating at fS between

the cascaded SCF stages. The SHA breaks the direct

capacitive path from VCOMP1to VCOMP3, and prevents aliasingdistortion, while also resulting in an undesirable yet

deterministic phase-lag of TS/2 [2]. In our prototype, we have

countered this phase-lag by decreasing the target zero

frequency (fZ2 ~ 15 KHz). We have also used a reference

selection buffer, which selects the lower of the bandgap(VBGAP) and soft-start (VSOFT) voltage (Fig. 3). Finally, it is

clear to see from Fig. 3, that a Type-II filter can be realized

by utilizing just the first two filter stages.

III. CIRCUIT IMPLEMENTATION

Unless otherwise mentioned, all the active elements havebeen implemented as PMOS-input based folded-cascode class-

AB amplifiers to account for low Input Common-Mode Range(ICMR), high gain-bandwidth and fast settling requirements.

The notable circuit techniques are discussed as follows:

A. GmC Integrator

The integrator needs to maintain PVT independence andlinear scalability of the Type-III function with fSW. Thus, as

shown in Fig. 3, we use the same bits (BTUNE_F) for configuring

the integratorfIandfSW(and hencefS).

00 2

1;

1)(

C

Gf

sC

GsH

mI

mI ==

(2)

The OTA topology of Fig. 5 is used to implement the Gmstage (in Fig. 3). The 1st stage is a level shifter to allow

operation at low-ICMR during soft-start. The 2nd stage is a

novel all-Bipolar core, with a small-signal Gm= IPTAT2/(2N

1)VT. By choosing a PTAT current source and scaling it withBTUNE_F using a current-DAC, we can achieve PVT

independence and linear scalability for Gm. In addition, by

increasing N, we can make the Gm highly-linear. This is

essential to prevent slewing distortion when large differential-

input signal ( 500 mV ensured by design at worst case

temperature of 40 C) is presented at the input during soft-

Fig. 5. OTA for implementing Gmstage in Fig. 3.

Fig. 4. Anti-aliasing analysis for input sampler of SC-HPF # 1.

Fig. 3. Proposed Type-III SCF Architecture (SCR = Switched-

Capacitor Resistor)


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start and line/load transients. It was observed that prevention

of slewing is a sufficient criterion to prevent any transient

performance degradation; and requirement of a flat linearregion as described in [6] is not necessary. This is a direct

consequence of our Type-III partitioning/sequencing scheme.Finally, we can see from (2) that C0variations still need to be

compensated via trimming.

B. SC-HPF # 1

The schematic of SC-HPF#1 is shown in Fig. 6. The

pole/zero pair is implemented using the BLT switched-capacitor circuit element described in [5]. It can be seen thatthe capacitor samples in both clock half-cycles, hence thesampling rate is doubled. Thus, the clock frequency need onlybef

SW(see Fig. 3). The SCF transfer function is given as:

( )( )

( )( )

1

1

1

12

12

1

1

11

11

12

111

1

11

1

11)(

+

+

+

+=

z

z

C

C

z

z

C

C

C

CzH

aaa

aSCF

(3)

This SCF design is parasitic-sensitive, and the bottom-plate

(~ 5 % of the main capacitance) of the switching capacitor

can introduce asymmetry between the two sampling paths. To

minimize the mismatch, we have divided the switching

capacitor into two equal halves and flipped them to provide

the same (halved) parasitics on the two switching nodes.It was observed that the finite amplifier Gain-Bandwidth

(fGBW

) can limit the high-frequency gain of this SC-HPF, byintroducing a complex-pole at the geometric mean ofeffectivef

GBWandf

Z1(unchanged).

DCCL

ZGBW

PDCCL

ZGBWNEWP

A

ff

fA

fff

_

1

1_

1_1

2

1;

= (4)

Here, ACL_DC

is the closed-loop DC gain of the SCF. fP1

nowonly controls the damping factor () of the complex pole(f

P1_NEW). f

P1_NEW can be accurately controlled by designing

amplifiers for a target fGBW

(= 20 MHz), carefully chosen forthe highest operatingf

SW(= 1 MHz).

C. SC-HPF # 2

To maximize the dynamic range of the filter, the SHA isdesigned to have a rail-to-rail architecture, and has fast settlingrequirements. This can make the SHA very power hungryespecially if it has to drive a large input capacitance for thesucceeding SCF. To alleviate this problem, we haveimplemented the double-sampling version of the T-networkapproach in [7] to implement the low-frequency zero (f

Z2), as

shown in Fig. 7. The effective loading of the SHA is reducedby 5X. The transfer function of novel SC-HPF # 2 is given as:

1

1

1

22

22

1

21

21

21

2121

21

21

21

22

212

1

1.1

1

1.

1

1..1)(

++

++

+=

z

z

C

C

z

C

C

C

CC

C

C

C

C

CzH

a

c

a

c

bc

baSCF

(5)

D. Clocking Scheme

A central clocking scheme is employed which drives the

signal-chain and sawtooth generator for PWM control. Sincethe SCFs employ double-sampling, the duty-cycle inaccuracyof the clock must be low (< 1 %) to minimize path-mismatch[8]. To ensure this, we have generated a master relaxation-oscillator clock (4 f

SW) and divided-by-2 to provide the SHA

clock (2 fSW

). This is further divided-by-2 to drive the twoSCFs with a clock rate =f

SW(see Figs. 3 and 8).

Now, since the SCF architecture is DC-coupled from VCOMP1

to V

COMP(Fig. 3), there is only a range of V

COMPwithin the rail

that can be accommodated (for a given VREF

), withoutsaturating one or more amplifiers in the signal chain. It isdifficult to design a sawtooth that tracks this range, and thesituation is exacerbated during soft-start and line/loadtransients. To maximize the dynamic range, we have used anear rail-to-rail sawtooth with fixed feed-forward gain(V

IN/|V

SAW| = 8/7). The target open-loop DC gain is then set by

the continuous-time gain stage (Fig. 3), which also providespost-filtering for high-frequency switching transientsemanating from the SCF to generate V

COMP.

IV. MEASUREMENT RESULTS

The voltage-mode controller IC is implemented in TIs0.36-m BCD process, occupies ~ 0.7 mm2 of active area

(Fig. 9) and bonded onto a 32-pin QFN package. Highly

Fig. 6. Circuit schematic for SC-HPF # 1.

40 pF

1.25 pF

1.25 pF

1.25 pF

Fig. 8. Proposed clocking scheme for the Type-III SCF Architecture.

Fig. 7. Circuit schematic for SC-HPF # 2.

10 pF

5 pF

3.5 pF 1 pF

1.25 pF

1.25 pF


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linear Poly2-Oxide-Poly1 (1.5 fF/m2)capacitors are used forimplementing all the capacitors described in Figs. 3, 6 and 7.

The total static current drawn from a 3.3 V supply is 1.1 mA,while static current consumption of the proposed Type-III

SCF core is only 0.63 mA. A large portion of the static

current is spent in the associated bias circuitry (0.24 mA), as

the design was not very optimized.For this prototype, we have designed the controller for V

IN

= 3.3 V, VOUT

= 1.0 V,ILOAD

= 1.5 A, and 1-bit configurationfor f

SW= 0.5, 1 MHz (B

TUNE_F = [0, 1]). The power-stage

(drivers and MOSFETs) and LC filter were implemented off-chip on a PCB. For f

SW= 0.5 MHz case, L= 1.5 H and C=

64 F (fLC

~ 16 KHz), while for fSW

= 1 MHz case,L= 1.0 Hand C= 30 F (f

LC~ 29 KHz).

Fig. 10 shows the measured open-loop frequency response

for the two cases off

SW. It can be seen that the filter transferfunction scales linearly withfSW

, and no distortion is observed.At higher frequencies, close tof

SW, we can observe slight gain

peaking in the magnitude response (as described in SectionIII-B), followed by a notch, due to the sample-and-hold effectof the fixed-frequency PWM control scheme. As can beinferred from Fig. 10, the loop is stabilized for both values off

SW, with Phase-Margin (PM) = 63, Gain Margin (GM) = 14

dB andfCL

= 52 KHz whenfSW

= 500 KHz; and PM = 55, GM= 12 dB andf

CL= 95 KHz whenf

SW= 1 MHz.

Fig. 11 shows the measured load step transient response ofthe Buck converter in closed-loop configuration. A load stepof 0 1.5 A is applied and removed at 0.3 A/s. Atf

SW= 500

KHz, the settling time is 50 s, while atfSW

= 1 MHz, it is 20s. To conclude, we were able to validate the closed-loopstability of the proposed compensator via both time- and

frequency-domain experiments. The specifications of theproposed ICare enlisted in Table I.

V. CONCLUSIONS

We have conceived and implemented novel switched-

capacitor filter based Type-III compensation architecture for

closed-loop regulation of Buck Converters. The

compensation is fully-integrated with minimal trimming

requirements, is frequency-scalable, and has moderate powerdissipation. Thus, compared to the conventional analog filter,it can result in lower area/cost and higher

programmability/ease-of-use.

As a larger perspective, we have laid the theoretical

foundations for designing sampled-data analog filter based

Type-III compensation of fixed-frequency switched-modepower converters employing linear PWM control. These

fundamentals can have wider applicability in the future.

REFERENCES

[1]

3-A Step-Down Regulator with Integrated Switcher, Mar. 2011,Texas Instruments, datasheet of chip no. TPS53311.

[2]

R. Gregorian and G. Temes, Analog MOS integrated circuits forsignal processing, Wiley, 1986.

[3] P.Y. Wu, S.Y.S. Tsui and P.K.T. Mok, Area- and Power-EfficientMonolithic Buck Converters with Pseudo-Type III Compensation,

IEEE JSSC, vol. 45, no. 8, pp. 1446-1455, Aug. 2010.

[4]

R.W. Erickson and D. Maksimovic, Fundamentals of PowerElectronics, Kluwer Academic Publishers, 2ndEd., 2000.

[5]

G. Temes, H.J. Orchard and M. Jahanbegloo, Switched-Capacitorfilter design using the Bilinear z-transform,IEEETrans. Cir. and Sys.,vol. 25, no. 12, pp. 1039-1044, Dec. 1978.

[6]

B. Gilbert, The multi-tanh principle: a tutorial overview,IEEE JSSC,vol. 33, no. 1, pp. 2-17, Jan. 1998.

[7]

W.M.C. Sansen and P.M.V. Peteghem, An area-efficient approach tothe design of very-large time constants in switched-capacitorintegrators,IEEE JSSC, vol. 19, no. 5, pp. 772 780, Dec. 1984.

[8]

J.J.F. Rijns and H. Wallinga, Spectral analysis of double-samplingswitched capacitor filters, IEEE JSSC, vol. 38, no. 11, pp. 1269 1279, Nov. 1991.

TABLE I

TYPE-IIISCFCONTROLLER ICSPECIFICATIONS

Parameter Value

Fabrication Technology 0.36-m, BCD process

Active die area (total/filter) ~ 0.65/0.4 mm2

Switching Frequency (fSW) 0.5 and 1.0 MHz

VDD/VIN/VOUT 3.3/3.3/1.0 V

ILOAD(max.) 1.5 A

Output Filter (L/C)1.5 H/64 F @fSW= 0.5 MHz

1.0 H/30 F @fSW= 1.0 MHz

Analog/Filter core static current 800/630 A

Bias + Bandgap static current 300 A

Total static current 1.1 mA

Fig. 11. Load step transient response atfSW= (a) 0.5 and (b) 1.0 MHz

(a) (b)

Fig. 10. Measured loop response of the complete system.

Fig. 9. Die Photo of the controller IC in 0.36-m BCD process.

bc switched-capacitor filter based type-iii compensation for switched-mode buck converters

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