block diagramumw-ic.com/uploadfiles/img/2015/11/10/755e7c08-16fb-4606...it is normally connected to...

UC3842B/43B/44B/45B

1

PIN CONNECTION (TOP VIEW)

DESCRIPTION

The are fixed frequency current-mode PWM controller

circuits. They are specially designed for off line and DC-to-DС converter applications with a minimal number of external components. The internally implemented circuits include a trimmed oscillator for precise duty cycle control, a temperature-compensated reference, a high gain error amplifier, a current sensing comparator, and a high-current totem-pole output ideally suited for driving a power MOSFET. The protection circuitry includes built-in undervoltage lockout and current limiting.

The 3842B and 3844B have UVLO thresholds of 16V (on) and 10V (off). The corresponding thresholds for the 3843B , 3845B , are 8.4V (on) and 7.6V (off). The 3842B and 3843B can operate within 100% duty cycle. The 3844 and 3845B can operate within 50% duty cycle.

The 384XB has start-up current 0.17mA (typ.). The 384XB differs in a higher unity gain bandwidth of the error amplifier.

FEATURES

Low start-up and operating current

High-current totem pole output

Undervoltage lockout with hysteresis

Operating frequency up to 500kHz

BLOCK DIAGRAM

(T is a toggle flip-flop used only in 3844, 3845)

ABSOLUTE MAXIMUM RATINGS

CHARACTERISTIC SYMBOL VALUE UNIT

Supply voltage (low impedance source) VCC 30 V

Output current IO 1 A

Input voltage (analog inputs - pins 2, 3) VI 0.3 to 5.5 V

Error amp output sink current ISink (EA) 10 mA

Power dissipation (TA = 250C) PO 1 W

Storage temperature range TSTG -65 to 150 oC

Lead temperature (soldering 5 sec.) TL 260 oC

Operating temperature range (TJ) TJ_op -40 to +125 oC

Min ESD rating (R = 1.5k, C = 100pF) ESD 2 kV

UC3842B/3843B/3844B/3845B

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ELECTRICAL CHARACTERISTICS (*VCC = 15V, RT = 10k , CT = 3.3nF, TJ = -400C to +1250C, unless otherwise specified)

CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Reference Section

Reference output voltage VRef TJ = 25 C, IRef = 1mA 4.9 5.0 5.1 V

Line regulation VRef 12V VCC 25V 6.0 20 mV

Load regulation VRef 1mA IRef 20mA 6.0 25

Temperature stability Ts 0.4 mV/ºC

Total output variation over Line,

Load, and Temperature

VRef_tot 4.82 5.18 V

Short-circuit output current ISC -30 -75 -180 mA

Oscillator Section

Oscillation frequency f TJ = 25 C 47 52 57 kHz

Oscillation frequency f TJ = Tlow to Thigh 46 58 kHz

Frequency change with voltage f/ VCC 12V VCC 25V 0.5 1.0 %

Frequency change with temperature Ftemp TJ = Tlow to Thigh 4 %

Oscillator amplitude VOsc (peak-to-peak) 1.6 V

Error Amplifier Section

Input bias current IBias VFB = 3V -0.1 -2 A

Input voltage VI(EA) VPin1 = 2.5V 2.42 2.5 2.58 V

Open-loop voltage gain AVOL 2V V0 4V 65 90 dB

Unity gain bandwidth UGBW TJ = 25оC (Note 3) 0.5 0.6 MHz

Power supply rejection ratio PSRR 12V VCC 25 V 60 70 dB

Output sink current ISink VPin2 = 2.7V, VPin1 = 1.1V 2 7 mA

Output source current ISource VPin2 = 2.3V, VPin1 = 5V -0.5 -1.0 mA

High output voltage VOH VPin2 = 2.3V, RL = 15k to GND 5.0 7.0 V

Low output voltage VOL VPin2 = 2.7V, RL = 15k to Pin 8 0.8 1.1

Current Sense Section

Gain GV (Notes 1 and 2) 2.85 3.0 3.15 V/V

Maximum input signal VI(Max) TJ = 250C 0.9 1.0 1.1 V

TJ= Tlow to Thigh 0.85 1.1

Supply voltage rejection SVR 12V VCC 25V (Note 1) 70 dB

Input bias current IBias V Pin3 = 3V -3.0 -10 A

Output Section

Low output voltage VOL ISink = 20mA 0.08 0.4 V

ISink = 200mA 1.4 2.2

High output voltage VOH ISink = 20mA 13 13.5

ISink = 200mA 12 13.0

Output voltage with UVLO

activated

UOL(UVLO) VCC=6V, ISink=1mA 0.1 1.1 V

Rise time tR TJ = 25 C, CL = 1nF (Note 3) 45 150 ns

Fall time tF TJ = 25 C, CL = 1nF (Note 3) 35 150

Undervoltage Lockout Section

Start threshold VTH(St) 3842B/44B 14.5 16.0 17.5 V

3843B/45B 7.8 8.4 9.0

Min. operating voltage VOPR(min) 3842B/44B 8.5 10 11.5 V

(After turn-on) 3843B/45B 7.0 7.6 8.2

PWM Section

Max. duty cycle D(Max) 3842B/43B ; TJ = 25 C 94 96 100 %

3842B/43B ; TJ = Tlow to Thigh 93 100

3844B/45B ; TJ = 25 C 47 48 50

3844B/45B ; TJ = Tlow to Thigh 46 50

Min. duty cycle D(Min) 0

UC3842B/43B/44B/45B


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Total Standby Current

Start up current IST 3843B, 3845B ; TJ = 25 C 0.13 0.3 mA

3843B, 3845B ; TJ = Tlow to Thigh 0.35

3842B, 3844B ; TJ = 25 C 0.2 0.3

3842B, 3844B ; TJ = Tlow to Thigh 0.45

Operating supply current ICC (Opr) VPin3 = VPin2 = 0V 13 17

Zener voltage VZ ICC=25 mA 30 38 V

*Adjust VCC above the start threshold before setting it to 15V.

Note 1: The parameter is measured at a trip point of a latch with VPin2=0.

Note 2: The gain is defined as A= VPin1/ VPin3; 0 VPn3 0.8V.

Note 3: These parameters, although guaranteed, are not 100% tested in production.

PIN FUNCTION

NO. FUNCTION DESCRIPTION

1 COMP This pin is the ERR AMP (Error Amplifier) output and is made for loop compensation.

2 VFB This is an inverting input of the ERR AMP. It is normally connected to the switching power supply output through a resistor

divider.

3 ISENSE A voltage proportional to an inductor current is applied to this input. The PWM uses this information to terminate the output

switch conduction.

4 RT/CT The oscillator frequency and maximum output duty cycle are programmed by connecting resistor RT to VREF and capacitor

CT to ground.

5 GND This pin is the combined control circuitry and power ground.

6 OUT This output directly drives the gate of a power MOSFET. Peak currents up to 1A are sourced and sunk by this pin.

7 VCC This pin is a positive supply of the integrated circuit.

8 VREF This is a reference output. It provides a charging current for capacitor CT through resistor RT

APPLICATION INFORMATION

Fig.1. ERR AMP configuration

UC3842B/43B/44B/45BUMW


R

4

Fig.2. Undervoltage Lockout (UVLO)

Fig.3. Current sense circuit

ERR AMP



R

5

Fig.4. Slope compensation techniques

SCR must be selected for a holding current of less than 0.5mA. A simple two-transistor circuit can be used in place of the SCR as shown

Fig.5. Latched shutdown

VREF

ERR

AMP



R

6

Fig.6. Error amplifier compensation

Fig.7. External clock synchronization

ERR

AMP

ERR

AMP

ERR

AMP



R

7

Fig.8. Soft-start circuit

TYPICAL PERFORMANCE CHARACTERISTICS

Fig.9. Timing resistor vs. Oscillator frequency Fig.10. Output dead-time vs. Oscillator frequency

5VREF

ERR

AMP



R

8

Fig.11. Maximum output duty cycle vs. Timing resistor (3842/43)

Fig.12.Current sense input threshold vs. ERR AMP output voltage Fig.13. Reference short-circuit current vs. Temperature

Fig.14. Supply current vs. Supply voltage

TJ=25oC

TJ=-40oC

TJ=+125oC



R

9

Fig.15. Oscillator and Output waveforms

VREF



R

block diagramumw-ic.com/uploadfiles/img/2015/11/10/755e7c08-16fb-4606...it is normally connected to...

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